DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7, 8, 9, 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blanquart (U.S. Pub. No. 20090108176).
Regarding claim 8, Blanquart discloses:
An image sensor (CMOS image sensor (CIS), par. 10, 24, and abstract), comprising:
a pixel array (pixel array, par. 6, 9, 10, and claims 8, 11) having at least one column of addressable pixels (CMOS image sensor with array of pixels has rows and columns, par. 6, 9, 10, 24), wherein the at least one column of addressable pixels includes at least two pixels (four photodiodes, par. 27, 28, and 30, and Figs. 6, 7, and 9) with each pixel of the at least two pixels including a photodetector (photodiode PD.sub.N, par. 25), a storage gate coupled to the photodetector (capture transistor TX1.sub.N, par. 27, 28, and Figs. 7 and 9), and a first transfer gate coupled to the storage gate (hold transistor TH.sub.N, par. 27, 28, and Figs. 7 and 9);
a readout circuit including
a second transfer gate having an input coupled to an output of each first transfer gate of each of the at least two pixels (transfer transistor TX3 is shared and connected to each transistor TH.sub.N, the four pixel samples are read by transferring charge to the floating diffusion using transfer transistor TX3 and hold transistor TH.sub.N, par. 27, 28, and Figs. 7 and 9), and
a control field effect transistor (FET), wherein a gate of the control FET is configured to receive charge from an output of the second transfer gate (source follower transistor (M3) of CMOS image sensor, where change transferred to the floating diffusion is read using the source follower transistor (M3) by enabling the select signal, par. 10, 24, 27, 28, abstract, and Figs. 7 and 9).
Regarding claim 9, Blanquart further discloses:
first transfer gate of each of the at least two pixels is a FET and the storage gate of each of the at least two pixels is a FET (transistors are part of the CMOS image sensor (CIS), where CMOS is a type of MOSFET, and MOSFET is a type of FET, par. 10, 24, and abstract).
Regarding claim 13, Blanquart further discloses:
a reset switch coupled to the output of the second transfer gate (reset transistor M1 coupled to the hold transistors TH.sub.N and floating diffusion C.sub.FD, where floating diffusion capacitance C.sub.FD is reset by asserting the reset clock RST, par. 25, 27, 28, and Figs. 7 and 9).
Regarding claim 14, see the rejection of claim 8 and note that the limitations of claim 14 were shown and where it was shown that there are four pixels/photodiodes and associated circuitry.
Regarding claim 15, see the rejection of claims 14 and 9 and note that the limitations of claim 15 were shown.
Regarding claim 1, see the rejection of claim 8 and note that the limitations of claim 1 were shown.
Regarding claim 2, see the rejection of claims 1 and 9 and note that the limitations of claim 2 were shown.
Regarding claim 7, Blanquart further discloses:
An imaging system comprising the image sensor of claim 1 (processor-based system 1211 including imager device 1200 as a CMOS imager device, par. 68 and see the rejection of claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blanquart (U.S. Pub. No. 20090108176) in view of Altice et al. (U.S. Pub. No. 20050110093).
Regarding claim 20, Blanquart is silent with regards to the four pixels are arranged in a 2 x 2 grid. Alice discloses this in par. 59-60, 66, and Figs. 9B and 10B where pixel cells 600a, 600b, 600c, and 600d are arranged in a 2 x 2 grid. As can be seen in par. 66 and Fig. 9B this is advantageous in that four pixels arranged on either side of readout and reset circuitry 975 can be read out though the readout and reset circuitry 975 in the middle using a row select signal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the four pixels are arranged in a 2 x 2 grid.
Regarding claim 6, see the rejection of claims 1 and 20 and note that the limitations of claim 6 were shown.
Allowable Subject Matter
Claims 3-5, 10-12, and 16-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, no prior art could be located that teaches or fairly suggests a length of the storage gate FET of each of the at least two pixels is higher than a length of the transfer gate FET of each of the at least two pixels, in combination with the rest of the limitations of the claim.
Regarding claim 4, no prior art could be located that teaches or fairly suggests storage gate of each of the at least two pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal, in combination with the rest of the limitations of the claim.
Claim 5 depends on claim 4 and therefore is objected to.
Regarding claim 10, no prior art could be located that teaches or fairly suggests the length of the storage gate FET of each of the at least two pixels is at least 10 times higher than the length of the transfer gate FET of each of the at least two pixels, in combination with the rest of the limitations of the claim.
Regarding claim 11, no prior art could be located that teaches or fairly suggests the storage gate of each of the at least two pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal, in combination with the rest of the limitations of the claim.
Claim 12 depends on claim 11 and therefore is objected to.
Regarding claim 16, no prior art could be located that teaches or fairly suggests a length of the storage gate FET of each of the four pixels is higher than a length of the transfer gate FET of each of the four pixels, in combination with the rest of the limitations of the claim.
Claim 17 depends on claim 16 and therefore is objected to.
Regarding claim 18, no prior art could be located that teaches or fairly suggests the storage gate of each of the four pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal, in combination with the rest of the limitations of the claim.
Claim 19 depends on claim 18 and therefore is objected to.
Conclusion
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639