DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 3-6, 8-12, 14, 16, and 18-20 are objected to because of the following informalities:
Claim 1:
Line 4 recites “processing operations for neural network processing”, which should be rewritten as “processing operations for the neural network processing” since “neural network processing” mentioned in line 2.
Line 6 recites “perform processing operations”, which should be rewritten as “perform processing the operations”.
Line 7 recites “neural network processing”, which should be rewritten as “the neural network processing”
Lines 7-8 recites “neural network processing”, which should be rewritten as “the neural network processing”
Lines 10-11 recites “neural network processing”, which should be rewritten as “the neural network processing”
Claim 3:
Line 3 recites “a said unresolved dependency”, which should be rewritten as “said unresolved dependency”.
Claim 4:
Line 2 recites “a said unresolved dependency”, which should be rewritten as “said unresolved dependency”.
Claim 5:
Line 2 recites “the neural network”, which is lack of antecedent basis in the claim or it should be written as “the neural network processing” for consistency throughout claim 1.
Claim 6:
Line 2 recites “a said unresolved dependency”, which should be rewritten as “said unresolved dependency”.
Line 3 recite “the graph”, which should be rewritten as “the graph representation” for consistency with claim 5.
Claim 8:
Line 2 recites “the graph representing”, which should be rewritten as “the graph representation representing”..
Claim 9:
Lines 2-3 recite “the graph”, which should be rewritten as “the graph representation”.
Claim 10:
Lines 3-4 recite “the neural network”, which should be rewritten as “the neural network processing”
Claim 11:
Line 3 recites “neural network processing”, which should be rewritten as “the neural network processing”.
Lines 11-12 recite “for neural network processing”, which should be rewritten as “for the neural network processing”.
Claim 12:
Line 2 recites “the indication flag”, which is lack of antecedent basis in the claim.
Claim 14:
Line 3 recites “a said at least one unresolved dependency”, which should be rewritten as “said at least one unresolved dependency”.
Claim 16 contains similar issues as pointed out in claim 1 above. Therefore, claim 16 is objected to under the same rationale.
Claim 18 contains similar issue as pointed out in claim 3 above. Therefore, claim 18 is objected to under the same rationale.
Claim 19 contains similar issue as pointed out in claim 4 above. Therefore, claim 19 is objected to under the same rationale.
Claim 20 contains similar issue as pointed out in claim 5 above. Therefore, claim 20 is objected to under the same rationale.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (Zhao), NPL “Neural network processing assembly and multi-neural network processing method”, and further in view of Mrozek et al. (Mrozek), US Patent Application Publication No. US 2022/0291955 A1 (Mrozek is from IDS filed on 05/28/2025).
As to independent claim 1, Zhao discloses a data processing system, the data processing system comprising a processor that is configured to perform neural network processing (Abstract: a neural network processing assembly and a multi-neural network processing method, the assembly comprises a plurality of processors), the processor comprising: at least one execution unit configured to perform processing operations for neural network processing (Abstract: an execution unit); and a control circuit configured to distribute processing tasks to the at least one execution unit to cause the at least one execution unit to perform processing operations for neural network processing in response to a set of indications of neural network processing to be performed provided to the control circuit (Abstract: a controller is used for invoking the processor to read task data and execute the task, wherein the processor is used for executing task according to the task data); wherein the processing tasks are asynchronous (page 2, last paragraph: the neural network processing component through the controller controls a plurality of execution units to execute the same or different task at the same time, or controlling one execution unit to execute different tasks at the same or different time (asynchronous); page 3, 1st paragraph: the execution unit further comprises a data collator, for finishing the task data read by the processor, obtaining the finishing data).
Zhao, however, does not disclose the processing tasks comprise a dependency on at least one other processing task, the set of indications of neural network processing to be performed comprising an indication flag to indicate whether the execution unit can be caused to operate with a dependency on at least one other asynchronous processing task being unresolved.
In the same field of endeavor, Mrozek discloses a graphics processor configured to perform asynchronous input dependency resolution among a group of interdependent workloads. The graphics processor can dynamically resolve input dependencies among the workloads according to a dependency relationship defined for the workloads. Dependency resolution be performed via a deferred submission mode which resolves input dependencies prior to thread dispatch to the processing resources or via immediate submission mode which resolves input dependencies at the processing resources (Abstract). Mrozek further discloses a list of dependencies to be managed during thread dispatch is provided and the graphics processing hardware automatically orders thread distribution or thread execution according to the specified dependencies. In one embodiment, flag or indicator bits are also added to thread dispatch instructions that indicate that the kernel to be dispatched by the instruction has a dependency that will need to be resolved. For example, in one embodiment the thread dispatch instruction can include a flag or bit (e.g., PreSync) that indicates that there are dependencies associated with the kernel to be dispatched. The thread dispatch instruction can also include or reference a set of one or more dependencies to be resolved before execution of the command (paragraph [0214]).
Since both Zhao and Mrozek teach processing tasks in a network processing, it would have been obvious to one of ordinary skills in the art, before the effective filing date of the claimed invention, to combine the teaching of Mrozek with Zhao to include disclose the processing tasks comprise a dependency on at least one other processing task, the set of indications of neural network processing to be performed comprising an indication flag to indicate whether the execution unit can be caused to operate with a dependency on at least one other asynchronous processing task being unresolved, as taught by Mrozek, for the purpose of avoiding unrelated commands stalled.
As to dependent claim 2, Zhao and Mrozek disclose wherein the indication flag is comprised in a set of indications sent by the control circuit to multiple execution units, wherein the execution units are input readers and each input reader receives the indication flag in its set of indications (Mrozek, paragraph [0214]).
As to dependent claim 3, Zhao and Mrozek disclose wherein an input reader is permitted to fetch second data where no overlap with first data associated with a said unresolved dependency is detected (Mrozek, paragraph [0228]).
As to dependent claim 4, Zhao and Mrozek disclose wherein the execution unit caused to operate with a said unresolved dependency is provided with a signal after execution begins to indicate that the dependency has been resolved (Mrozek, paragraph [0214]).
As to dependent claim 5, Zhao and Mrozek disclose wherein when data is fetched from storage to be processed by the neural network, the data is operable upon in accordance with a sequence of operations according to at least a portion of a graph representation of the neural network (Mrozek, paragraphs [0162], [0216]).
As to dependent claim 6, Zhao and Mrozek disclose wherein the execution unit caused to operate with a said unresolved dependency is further caused to wait when the graph reaches an output stage until said unresolved dependency is resolved (Mrozek, paragraph [2016]).
As to dependent claim 7, Zhao and Mrozek disclose wherein the portion is represented by a sub-graph of the graph representation of the neural network (Mrozek, paragraph [0229]).
As to dependent claim 8, Zhao and Mrozek disclose wherein connections between sections in the graph representing the neural network are pipes and are mapped to storage elements in the processor (Mrozek, paragraph [0204]).
As to dependent claim 9, Zhao and Mrozek disclose wherein the control unit is configured to control and dispatch work representing an operation of the graph on at least a portion of the data provided by a pipe when the required data for the operation is stored in the pipe (Mrozek, paragraph [0204]).
As to dependent claim 10, Zhao and Mrozek disclose wherein an execution unit is operable to perform a memory load access to initiate a sequence of operations according to at least a portion of a graph representation of the neural network (Mrozek, paragraph [0209]).
As to independent claim 11, Zhao discloses a method of operating an execution unit of a processor that is configured to perform neural network processing (Abstract: a neural network processing assembly and a multi-neural network processing method, the assembly comprises a plurality of processors; a controller is used for invoking the processor to read task data and execute the task, wherein the processor is used for executing task according to the task data), the method comprising:
receiving a task and a set of indications of neural network processing to be
performed (page 2, last paragraph: the neural network processing component through the controller controls a plurality of execution units to execute the same or different task at the same time, or controlling one execution unit to execute different tasks at the same or different time (asynchronous); page 3, 1st paragraph: the execution unit further comprises a data collator, for finishing the task data read by the processor, obtaining the finishing data);
performing the execution unit processing operations for neural network processing (Abstract: an execution unit for multi-neural network parallel processing and interaction);
Zhao, however, does not disclose detecting from at least a first indication flag in the set of indications whether the neural network processing for the task can be started with at least one unresolved dependency at the execution unit; detecting from at least a second flag which neural network processing work items of the task can be performed at the execution unit with at least one unresolved dependency; detecting when the at least one unresolved dependency becomes resolved; and responsive to detecting when the at least one unresolved dependency becomes resolved, completing the neural network processing for the task.
In the same field of endeavor, Mrozek discloses a graphics processor configured to perform asynchronous input dependency resolution among a group of interdependent workloads. The graphics processor can dynamically resolve input dependencies among the workloads according to a dependency relationship defined for the workloads. Dependency resolution be performed via a deferred submission mode which resolves input dependencies prior to thread dispatch to the processing resources or via immediate submission mode which resolves input dependencies at the processing resources (Abstract). Mrozek further discloses a list of dependencies to be managed during thread dispatch is provided and the graphics processing hardware automatically orders thread distribution or thread execution according to the specified dependencies. In one embodiment, flag or indicator bits are also added to thread dispatch instructions that indicate that the kernel to be dispatched by the instruction has a dependency that will need to be resolved. For example, in one embodiment the thread dispatch instruction can include a flag or bit (e.g., PreSync) that indicates that there are dependencies associated with the kernel to be dispatched. The thread dispatch instruction can also include or reference a set of one or more dependencies to be resolved before execution of the command (paragraph [0214]).
Since both Zhao and Mrozek teach processing tasks in a network processing, it would have been obvious to one of ordinary skills in the art, before the effective filing date of the claimed invention, to combine the teaching of Mrozek with Zhao to include detecting from at least a first indication flag in the set of indications whether the neural network processing for the task can be started with at least one unresolved dependency at the execution unit; detecting from at least a second flag which neural network processing work items of the task can be performed at the execution unit with at least one unresolved dependency; detecting when the at least one unresolved dependency becomes resolved; and responsive to detecting when the at least one unresolved dependency becomes resolved, completing the neural network processing for the task, as taught by Mrozek, for the purpose of avoiding unrelated commands stalled.
As to dependent claim 12, Zhao and Mrozek disclose further comprising receiving the set of indications including the indication flag at an input reader (Mrozek, paragraph [0030]).
As to dependent claim 13, Zhao and Mrozek disclose wherein receiving a set of indications comprises receiving at least a single bit indication flag (Mrozek, paragraph [0030]).
As to dependent claim 14, Zhao and Mrozek disclose further comprising permitting an input reader to fetch second data where no overlap with first data associated with a said at least one unresolved dependency is detected (Mrozek, paragraphs [0162], [0216]).
As to dependent claim 15, Zhao and Mrozek disclose wherein completing the neural network processing for the task further comprises causing the execution unit to wait at an output write stage until the at least one unresolved dependency becomes resolved (Mrozek, paragraph [0162]).
Claims 16-20 are method claims that contain similar limitations of claims 1-5, respectively. Therefore, claims 16-20 are rejected under the same rationale.
Conclusion
Any inquiry concerning this communication should be directed to CHAU T NGUYEN at telephone number (571)272-4092. The examiner can normally be reached on M-F from 8am to 5pm (PT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cesar Paula, can be reached at telephone number 5712724128. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAU T NGUYEN/Primary Examiner, Art Unit 2145
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