DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks/Arguments
With respect to the rejection of claim 1 under 35 USC 112(a), Examiner withdraws said rejection due to proper amendments.
The indicated allowability of claim 1 is withdrawn in view of new grounds of rejection set forth herein as necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singh (US 2020/0119689 A1).
Regarding claim 1, Singh teaches a circuit comprising:
a current mirror (Fig. 3, 302, 303, [0027] a current mirror transistor 303 coupled to 302) having first and second outputs (Fig. 3, collectors of 302 and 303);
oscillator circuitry ([0027] oscillator 310) including:
a first transistor (Fig. 3, 331) having a first terminal (source of 331) coupled to the first output (collector of 303) of the current mirror, having a second terminal (drain of 331), and having a control terminal (gate of 331); and
a second transistor (332) having a first terminal (source of 332) coupled to the first output (collector of 303) of the current mirror, having a second terminal (drain of 332) coupled to the control terminal (gate of 331), and having a control terminal (gate of 332) coupled to the second terminal of the first transistor (drain of 331); and
current shunt circuitry (301) having a terminal (emitter of 331) coupled to the second output (collector-base of 302) of the current mirror.
Regarding claim 21, all the limitations of claim 1 are taught by Singh.
Singh further teaches the circuit,
Allowable Subject Matter
Claims 2-7, 22-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior arts fail to teach or reasonably suggest a circuit, wherein the current shunt circuitry includes: a third transistor having a second terminal, and a control terminal coupled to a third output of the current mirror; a fourth transistor having a first terminal coupled to the third output of the current mirror and the control terminal of the third transistor, a second terminal coupled to ground, and a control terminal coupled to the control terminal of the third transistor; a resistor coupled between the second terminal of the third transistor and ground; and a fifth transistor having a first terminal coupled to an input to the circuit, a second terminal coupled to ground, and a third terminal coupled to the first terminal of the third transistor, in combination with the other limitations of the claim.
Regarding claim 3, the prior arts fail to teach or reasonably suggest a circuit, further including clamp circuitry coupled to a third output of the current mirror and an input to the circuit, the clamp circuitry having: a third transistor having a first terminal coupled to the third output of the current mirror, a second terminal coupled to ground, and a control terminal coupled to ground; and a fourth transistor having a first terminal coupled to the input to the circuit, a second terminal coupled to ground, and a control terminal coupled to the first terminal of the third transistor, in combination with the other limitations of the claim.
Regarding claim 4, the prior arts fail to teach or reasonably suggest a circuit, further including oscillator disable circuitry coupled to a third output and a fourth output of the current mirror, the oscillator disable circuitry having: a third transistor having a first terminal coupled to the third output of the current mirror, a second terminal coupled to ground, and a control terminal coupled to the fourth output of the current mirror; a fourth transistor having a first terminal coupled to the control terminal of the third transistor, a second terminal, and a control terminal coupled to the control terminal of the third transistor; a first resistor coupled between the second terminal of the fourth transistor and ground; a second resistor coupled between the first terminal of the fourth transistor and ground; and a fifth transistor having a first terminal coupled to the oscillator circuitry, a second terminal coupled to ground, and a control terminal coupled to the third output of the current mirror, in combination with the other limitations of the claim.
Regarding claim 5, the prior arts fail to teach or reasonably suggest a circuit, further comprising isolation circuitry coupled to the second terminal of the first transistor and the second terminal of the second transistor, the isolation circuitry having a center tapped to a ground terminal, in combination with the other limitations of the claim.
Regarding claim 6, the prior arts fail to teach or reasonably suggest a circuit, further comprising oscillator startup circuitry having a terminal coupled to a third output of the current mirror, in combination with the other limitations of the claim.
Regarding claim 7, the prior arts fail to teach or reasonably suggest a circuit, wherein the current mirror includes a third transistor having first terminal coupled to the first terminals of the first and second transistors, a control terminal coupled to the control terminals of the first and second transistors, and a second terminal coupled to the current shunt circuitry, the circuit further including: a switch coupled between the first terminal of the third transistor and the control terminal of third transistor, and a control terminal; and a discharge circuit having a first terminal coupled to an input to the circuit, a second terminal coupled to ground, a first output coupled to the control terminal of the switch and a second output coupled to an input of the current shunt circuitry, in combination with the other limitations of the claim.
Regarding claim 22, the prior arts fail to teach or reasonably suggest a circuit, further comprising a fuse having an input and an output, the output coupled to the input of the reverse blocking switch circuitry, in combination with the other limitations of the claim.
Regarding claim 23, claim 23 is objected to due to its dependency to claim 5 above.
Regarding claim 24, claim 24 is objected to due to its dependency to claim 6 above.
Regarding claim 25, claim 25 is objected to due to its dependency to claim 6 above.
Claims 26-34 are allowed. Specifically, the independent claim 26 is allowed over the prior arts. The dependent claims 27-34 are allowed due to their dependencies to the said independent claim 26
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 26, the prior arts fail to teach or reasonably suggest a system comprising: an isolation circuit having: a first winding coupled to the second terminal of the first transistor and the second terminal of the second transistor; a second winding separated from the first winding by an isolation barrier; a receiver; the isolation circuit being center-tapped to a ground terminal; and a receiver circuit having: an input coupled to the second winding of the isolation circuit; and an output; and a processor coupled to the output of the receiver circuit, in combination with the other limitations of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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