DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR 10-2023-0015775, filed on 02/26/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Par. 23: “DB modulation” should instead read “BD modulation”
Appropriate correction is required.
Claim Objections
Claims 11 and 18 are objected to because of the following informalities:
Claim 11, line 4: “each of the second and fourth switches is a -type …” should instead read “each of the second and fourth switches is a p-type …”
Claim 18, line 2: “DB modulation should instead read “BD modulation”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques", 2018 IEEE International Solid - State Circuits Conference - (ISSCC) by Wang et al.
Regarding claim 1, Wang teaches an audio amplifier (Fig. 3.5.2 and 3.5.3), comprising:
a loop filter (OP1, OP2, “loop filter”) configured to receive a differential input signal pair (Vin, Vip);
a pulse-width modulation (PWM) signal generator configured to generate PWM signals, corresponding to the differential input signal pair, based on signals received from the loop filter (PWM & Pre-Driver);
a driver configured to generate an output signal pair based on the PWM signals (Output drivers);
a feedback circuit configured to feed back the output signal pair to the loop filter (Rfb); and
a common mode compensation circuit (Negative Output Common Mode Injection (NOCMI)) configured to compensate for a fluctuation in a common mode voltage of the fed-back output signal pair,
wherein the common mode compensation circuit generates a compensation voltage for each of a plurality of levels of the common mode voltage, and provides the generated compensation voltage to the loop filter (Column 2 Paragraph 2).
Regarding claim 18, Wang teaches the audio amplifier of claim 1, wherein the audio amplifier is a class D amplifier with DB modulation (Col. 1 par. 3, Col. 2 Par. 2).
Regarding claim 19, Wang teaches a method of operating an audio amplifier (Fig. 3.5.2 and 3.5.3), the method comprising:
receiving an audio signal through an input terminal (Vin, Vip) of a loop filter of the audio amplifier (OP1, OP2, “loop filter”);
generating a pulse-width modulation (PWM) signal corresponding to the audio signal (PWM and Pre-Driver);
generating an output signal (Vop, Von)to be output to a speaker, based on the PWM signal;
feeding back (Rfb) the output signal to the loop filter; and
compensating for a fluctuation in a common mode voltage of the fed-back output signal (NOCMI),
wherein compensating for the fluctuation comprises:
generating a compensation voltage for each of a plurality of levels of the common mode voltage (Col. 2, Par. 2); and
providing the generated compensation voltage to the loop filter (Col. 2, Par. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques", 2018 IEEE International Solid - State Circuits Conference - (ISSCC) by Wang et al.
Regarding claim 20, Wang teaches a class D audio amplifier with BD modulation (Col. 1 par. 3, Col. 2 Par. 2), the class D audio amplifier comprising:
a loop filter (Fig. 3.5.2 and 3.5.3OP1, OP2, “loop filter”);
a pulse-width modulation (PWM) signal generator (PWM and Pre-Driver);
a gate driver (Output drivers; while not specified in Wang, gate drivers are well known in the art of class-D audio amplifiers, as shown in fig. 2 of US 2020255516 by Lin et al.);
a power driver (Output drivers; while not specified in Wang, gate drivers are well known in the art of class-D audio amplifiers, as shown in fig. 2 of US 2020255516 by Lin et al.);
a feedback circuit (Rfb); and
a common mode compensation circuit (NOCMI), wherein
the common mode compensation circuit comprises a control node (see annotated figure) connected to a first input terminal and a second input terminal of the loop filter, and
the common mode compensation circuit is configured to:
apply a ground voltage to the control node when both a first output signal and a second output signal of the class D audio amplifier are at a high level (Col. 2 Par. 2);
apply a driving voltage to the control node when both the first output signal and the second output signal are at a low level (Col. 2 Par. 2); and
apply a mean voltage of the driving voltage and the ground voltage to the control node when one of the first and second output signals is at a high level and the other one of the first and second output signals is at a low level (Col. 2 Par. 2).
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Claim(s) 1 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220255516 by Lin et al.
Regarding claim 1, Lin teaches an audio amplifier (Par. 6 class-D amplifier, while Lin doesn’t specify that this is an audio amplifier, class-D amplifiers are well known for being audio amplifiers, as taught in "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques" by Wang et al.), comprising:
a loop filter (Fig. 2 #202) configured to receive a differential input signal pair (Vi1, Vi2);
a pulse-width modulation (PWM) signal generator configured to generate PWM signals, corresponding to the differential input signal pair, based on signals received from the loop filter (#204);
a driver configured to generate an output signal pair (VOP, VON) based on the PWM signals (#206, #208);
a feedback circuit (#208) configured to feed back the output signal pair (VOP, VON) to the loop filter (#202); and
a common mode compensation circuit (#212) configured to compensate for a fluctuation in a common mode voltage of the fed-back output signal pair (Par. 22),
wherein the common mode compensation circuit generates a compensation voltage for each of a plurality of levels of the common mode voltage, and provides the generated compensation voltage to the loop filter (Par. 22).
Regarding claim 18, Lin teaches the audio amplifier of claim 1, wherein the audio amplifier is a class D amplifier with DB modulation (Par. 3-4).
Regarding claim 19, Lin teaches a method of operating an audio amplifier (Par. 6 class-D amplifier, while Lin doesn’t specify that this is an audio amplifier, class-D amplifiers are well known for being audio amplifiers, as taught in "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques" by Wang et al.), the method comprising:
receiving an audio signal through an input terminal (Fig. 2 In1, In2) of a loop filter (#202) of the audio amplifier;
generating a pulse-width modulation (PWM) signal (#204) corresponding to the audio signal;
generating an output signal to be output to a speaker (While it’s not specified what load #214 is, class-D amplifiers are well known for being audio amplifiers with a speaker as a load, as taught in "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques" by Wang et al.), based on the PWM signal;
feeding back the output signal to the loop filter (#210); and
compensating for a fluctuation in a common mode voltage of the fed-back output signal (#212),
wherein compensating for the fluctuation comprises:
generating a compensation voltage for each of a plurality of levels of the common mode voltage (Par. 22); and
providing the generated compensation voltage to the loop filter (Par. 22).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220255516 by Lin et al. in view of US 20110169569 by Liu.
Regarding claim 20, Lin teaches a class D audio amplifier (Par. 6 class-D amplifier, while Lin doesn’t specify that this is an audio amplifier, class-D amplifiers are well known for being audio amplifiers, as taught in "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3. 15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques" by Wang et al.) with BD modulation (Par. 3-4), the class D audio amplifier comprising:
a loop filter (Fig. 2 #202);
a pulse-width modulation (PWM) signal generator (#204);
a gate driver (#206);
a power driver (#208);
a feedback circuit (#208); and
a common mode compensation circuit (#212) comprises a control node (ncs) connected to a first input terminal (IN1) and a second input terminal (IN2) of the loop filter (#202), and
the common mode compensation circuit is configured to:
apply a ground voltage to the control node when both a first output signal and a second output signal of the class D audio amplifier are at a high level (Par. 22);
apply a driving voltage to the control node when both the first output signal and the second output signal are at a low level (Par. 22).
Lin doesn’t teach to apply a mean voltage of the driving voltage and the ground voltage to the control node when one of the first and second output signals is at a high level and the other one of the first and second output signals is at a low level.
However, Liu teaches a class-D amplifier circuit with common mode feedback where the common mode feedback is configured to apply a mean voltage of the driving voltage and the ground voltage to the control node when one of the first and second output signals is at a high level and the other one of the first and second output signals is at a low level (Par. 37; VFCM=(OUTP+OUTN)/2).
It would be obvious to a person of ordinary skill in the art before the effective filing date to combine Liu with Lin since both are used in are analogous art and are used in a similar context for common-mode compensation. Liu’s common mode compensation greatly improves the performance of the amplifier circuit (Liu Abstract).
Allowable Subject Matter
Claims 2-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art fails to teach that the common mode compensation circuit generates the compensation voltage based on the PWM signals.
Conclusion
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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