The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/29/2026 has been entered.
Notice to Applicant
In response to the communication received on 01/29/2026, the following is a Non-Final Office Action for Application No. 18525580.
Status of Claims
Claims 1-20 are pending.
Response to Amendments
Applicant’s amendments have been fully considered.
Response to Arguments
Applicant’s arguments with respect to the claims have been fully considered but are moot in light of the new grounds of rejection, as necessitated by amendment.
As per the 101 rejection, Applicant argues that the claims are in favor of eligibility per Prong One of Step 2A, however Examiner respectfully disagrees. Per Prong One of Step 2A, the identified recitation of an abstract idea falls within at least one of the Abstract Idea Groupings consisting of: Mathematical Concepts, Mental Processes, or Certain Methods of Organizing Human Activity. Particularly, the identified recitation falls within the Mental Processes including concepts performed in the human mind (including an observation, evaluation judgment, opinion) and/or Certain Methods of Organizing Human Activity including managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules of instructions). Since the recitation of the claims falls into at least one of the above Groupings, there is a basis for providing further analysis with regard to Prong Two of Step 2A to determine whether the recitation of an abstract idea is deduced to being directed to an abstract idea. Thus, the rejection is maintained.
Applicant argues that the claims are in favor of eligibility per Prong Two of Step 2A, however Examiner respectfully disagrees. Per Prong Two of Step 2A, this judicial exception is not integrated into a practical application because the claim as a whole does not integrate the identified abstract idea into a practical application. The processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing/transmitting data. This generic processor server computing device limitation is no more than mere instructions to apply the exception using a generic computer component. Further, processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices to inter alia perform the function of outputting the server network design is mere instruction to apply an exception using a generic computer component which cannot integrate a judicial exception into a practical application. Accordingly, this/these additional element(s) does/do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. In other words, the present claims use a generic processing device and memory medium to inter alia perform the function of outputting the server network design which is a concept that can be performed in the human mind. The processor is merely used to perform the function(s), and the processor does not integrate the abstract idea into a practical application since there are no meaningful limits on practicing the abstract idea. Thus, since the claims are directed to the determined judicial exception in view of the two prongs of Step 2A, the 2019 PEG flowchart is directed to Step 2B. Thus, the rejection is maintained.
Applicant argues that the claims are in favor of eligibility per Step 2B, however Examiner respectfully disagrees. Therein, the additional elements and combinations therewith are examined in the claims to determine whether the claims as a whole amounts to significantly more than the judicial exception. It is noted here that the additional elements are to be considered both individually and as an ordered combination. In this case, the claims each at most comprise additional elements of: processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices. Taken individually, the additional limitations each are generically recited and thus does not add significantly more to the respective limitations. Further, processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices to inter alia perform the function of outputting the server network design is mere instruction to apply an exception using a generic computer component which cannot provide an inventive concept in Step 2B (or, looking back to Step 2A, cannot integrate a judicial exception into a practical application). For further support, the Applicant’s specification supports the claims being directed to use of a generic computer/memory type structure. Taken as an ordered combination, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitations are directed to limitations referenced in Alice Corp. that are not enough to qualify as significantly more when recited in a claim with an abstract idea include the non-limiting or non-exclusive examples of MPEP § 2106.05. Thus, the rejection is maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. The claims fall within statutory class of process or machine; hence, the claims fall under statutory category of Step 1.
Step 2 is the two-part analysis from Alice Corp. (also called the Mayo test). The 2019 PEG makes two changes in Step 2A: It sets forth new procedure for Step 2A (called “revised Step 2A”) under which a claim is not “directed to” a judicial exception unless the claim satisfies a two-prong inquiry. The two-prong inquiry is as follows: Prong One: evaluate whether the claim recites a judicial exception (an abstract idea enumerated in the 2019 PEG, a law of nature, or a natural phenomenon). If claim recites an exception, then Prong Two: evaluate whether the claim recites additional elements that integrate the exception into a practical application of the exception. The claim(s) recite(s) the following abstract idea indicated by non-boldface font and additional limitations indicated by boldface font:
processing circuitry and memory storing instructions which are executed by the processing circuitry to: receive a user input of parameters including a memory ratio of local memory to heterogeneous memory in each server computing device, a first relative throughput when an entire dataset is in local memory on a server computing device, and a second relative throughput when the entire dataset is in heterogeneous memory on the server computing device; based on the parameters, determine a server ratio of a number of server computing devices, each server computing device executing data-processing workloads in an enhanced cluster with heterogeneous memory to a number of server computing devices in a baseline cluster without heterogeneous memory, wherein the enhanced cluster and the baseline cluster deliver equivalent data throughput performance for the data-processing workloads; based on the parameters and the server ratio, generate a server network design; and output the server network design.
[or]
receiving a user input of parameters including a memory ratio of local memory to heterogeneous memory in each server computing device, a first relative throughput when an entire dataset is in local memory on a server computing device, and a second relative throughput when the entire dataset is in heterogeneous memory on the server computing device; based on the parameters, determining a server ratio of a number of server computing devices in an enhanced cluster with heterogeneous memory to a number of server computing devices in a baseline cluster without heterogeneous memory, wherein the enhanced cluster and the baseline cluster deliver equivalent data throughput performance; based on the parameters and the server ratio, generating a server network design; and outputting the server network design.
[or]
processing circuitry and memory storing instructions which are executed by the processing circuitry to: receive a user input of parameters including a memory ratio of local memory to heterogeneous memory in each server computing device, a first relative throughput when an entire dataset is in local memory on a server computing device, and a second relative throughput when the entire dataset is in heterogeneous memory on the server computing device; based on the parameters, determine a server ratio of a number of server computing devices in an enhanced cluster with heterogeneous memory to a number of server computing devices in a baseline cluster without heterogeneous memory, wherein the enhanced cluster and the baseline cluster deliver equivalent data throughput performance; based on the server ratio and a relative Total Cost of Ownership (TCO) comparing a TCO of an enhanced server computing device equipped with heterogeneous memory relative to a TCO of a baseline server computing device without heterogeneous memory, calculate a TCO savings value indicating a percentage reduction of TCO that is predicted by deploying heterogeneous memory in the server computing devices in accordance with the inputted parameters; and output the TCO savings value and the server ratio.
Per Prong One of Step 2A, the identified recitation of an abstract idea falls within at least one of the Abstract Idea Groupings consisting of: Mathematical Concepts, Mental Processes, or Certain Methods of Organizing Human Activity. Particularly, the identified recitation falls within the Mental Processes including concepts performed in the human mind (including an observation, evaluation judgment, opinion).
Per Prong Two of Step 2A, this judicial exception is not integrated into a practical application because the claim as a whole does not integrate the identified abstract idea into a practical application. The processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing/transmitting data. This generic processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices limitation is no more than mere instructions to apply the exception using a generic computer component. Further, outputting the server network design or output the TCO savings value and the server ratio by a processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices is mere instruction to apply an exception using a generic computer component which cannot integrate a judicial exception into a practical application. Accordingly, this/these additional element(s) does/do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Thus, since the claims are directed to the determined judicial exception in view of the two prongs of Step 2A, the 2019 PEG flowchart is directed to Step 2B.
Per Step 2B, the additional elements and combinations therewith are examined in the claims to determine whether the claims as a whole amounts to significantly more than the judicial exception. It is noted here that the additional elements are to be considered both individually and as an ordered combination. In this case, the claims each at most comprise additional elements of: processing circuitry, memory, local memory, heterogeneous memory, and server computing devices. Taken individually, the additional limitations each are generically recited and thus does not add significantly more to the respective limitations. Further, outputting the server network design or output the TCO savings value and the server ratio by a processing circuitry, memory, local memory, heterogeneous memory, and/or server computing devices is mere instruction to apply an exception using a generic computer component which cannot provide an inventive concept in Step 2B (or, looking back to Step 2A, cannot integrate a judicial exception into a practical application). For further support, the Applicant’s specification supports the claims being directed to use of a generic computer/memory type structure at ¶0063 wherein “The logic processor may include one or more physical processors configured to execute software instructions.” Taken as an ordered combination, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitations are directed to limitations referenced in Alice Corp. that are not enough to qualify as significantly more when recited in a claim with an abstract idea include, as a non-limiting or non-exclusive examples: i. Adding the words "apply it" (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a particular function such as creating and maintaining electronic records is performed by a computer, as discussed in Alice Corp., 134 S. Ct. at 2360, 110 USPQ2d at 1984 (see MPEP § 2106.05(f));
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ii. Simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, as discussed in Alice Corp., 134 S. Ct. at 2359-60, 110 USPQ2d at 1984 (see MPEP § 2106.05(d));
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iii. Adding insignificant extra-solution activity to the judicial exception, e.g., mere data gathering in conjunction with a law of nature or abstract idea such as a step of obtaining information about credit card transactions so that the information can be analyzed by an abstract mental process, as discussed in CyberSource v. Retail Decisions, Inc., 654 F.3d 1366, 1375, 99 USPQ2d 1690, 1694 (Fed. Cir. 2011) (see MPEP § 2106.05(g)); or
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v. Generally linking the use of the judicial exception to a particular technological environment or field of use, e.g., a claim describing how the abstract idea of hedging could be used in the commodities and energy markets, as discussed in Bilski v. Kappos, 561 U.S. 593, 595, 95 USPQ2d 1001, 1010 (2010) or a claim limiting the use of a mathematical formula to the petrochemical and oil-refining fields, as discussed in Parker v. Flook. The courts have recognized the following computer functions inter alia to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner: performing repetitive calculations; receiving, processing, and storing data (e.g., the present claims); electronically scanning or extracting data; electronic recordkeeping; automating mental tasks (e.g., process/machine/manufacture for performing the present claims); and receiving or transmitting data (e.g., the present claims).
The dependent claims do not cure the above stated deficiencies, and in particular, the dependent claims further narrow the abstract idea without reciting additional elements that integrate the exception into a practical application of the exception or providing significantly more than the abstract idea. Since there are no elements or ordered combination of elements that amount to significantly more than the judicial exception, the claims are not eligible subject matter under 35 USC §101.
Thus, viewed as a whole, these additional claim element(s) do not provide meaningful limitation(s) to transform the abstract idea into a patent eligible application of the abstract idea such that the claim(s) amounts to significantly more than the abstract idea itself. Therefore, the claim(s) are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hulton et al. (US 20220076726 A1) hereinafter referred to as Hulton in view of Stabrawa et al. (US 20250138883 A1) hereinafter referred to as Stabrawa in further view of Ni et al. (WO 2018219183 A1) hereinafter referred to as Ni.
Hulton teaches:
Claim 1. A computing system for modeling a deployment of heterogeneous memory on a server network, the system comprising:
processing circuitry and memory storing instructions which are executed by the processing circuitry to (¶0083 Returning to FIG. 1, the illustrated embodiment of the configurable system 100 may include a processor 130 (e.g., a microprocessor, digital processor, etc.) that is coupled with a memory device 140 via, for example, a communications interface 110. The communications interface 110 may include any number of suitable computing bus architectures such as, for example, system bus architectures or even any number of input/output (I/O) bus architectures which are commonly used to connect various peripheral devices to one or more processors. ¶0262 In one exemplary embodiment, each of the processors and/or memories is capable of isolated operation without other processors in the processing system. In one such variant, each search processor 920B can independently throttle up or down its memory bandwidth to optimize its performance.):
receive a user input of parameters including a memory ratio of local memory to heterogeneous memory in each server computing device, a first relative throughput when an entire dataset is in local memory on a server computing device, and a second relative throughput when the entire dataset is in heterogeneous memory on the server computing device (¶0183 At operation 628, when the temporal constraint is reached, it is next determined per operation 630 whether any portions have not been read/refreshed (e.g., by an access to those portions) under the probabilistic scheme, such as where for whatever reason the probability distribution was skewed. If so, then per operation 632, such unrefreshed portions are refreshed, and per operation 634, and the temporal constraint and/or the scheme adjusted accordingly so as to obviate further “active” refreshes of the type used in operation 632 ¶0100 An application can intelligently use the memory performance characteristics to select a refresh rate that both (i) minimizes memory bandwidth for refresh while (ii) still providing acceptable reliability. For example, a first memory array may use a refresh rate (e.g., 60 ms) that results in low bit error rates (e.g., 1E-18) for the first memory array; however, a second memory array may use a refresh rate (e.g., 90 ms) that results in a slightly higher bit error rate than the first memory array (e.g., 1E-17).);
based on the parameters, determine a server ratio of a number of server computing devices in an enhanced cluster with heterogeneous memory to a number of server computing devices in a baseline cluster without heterogeneous memory, wherein the enhanced cluster and the baseline cluster deliver equivalent data throughput performance (¶0100 An application can intelligently use the memory performance characteristics to select a refresh rate that both (i) minimizes memory bandwidth for refresh while (ii) still providing acceptable reliability. For example, a first memory array may use a refresh rate (e.g., 60 ms) that results in low bit error rates (e.g., 1E-18) for the first memory array; however, a second memory array may use a refresh rate (e.g., 90 ms) that results in a slightly higher bit error rate than the first memory array (e.g., 1E-17). ¶0074 In an exemplary implementation, a memory device is provided which allows, inter alia, the memory device to be selectively optimized for a given application, such that the memory bandwidth is improved and/or that power consumption is minimized as compared with prior, largely inflexible memory architectures. For instance, embodiments are disclosed herein which enable the memory device to flexibly alter its configuration during application run-time so as to further optimize its operation, especially in instances in which the memory requirements may change over time, and/or are tolerant to such configuration changes. In one exemplary approach, memory devices are disclosed which may selectively disable or enable memory refresh operations (or aspects thereof));
based on the parameters and the server ratio, generate a server network design (¶0076 Specific operating examples are also disclosed for which the inventive memory devices described herein may be more suitable than prior memory device architectures. For example, memory device architectures that are optimized for blockchain-based cryptocurrency type applications, and in particular, for use in proof-of-work (POW) mining applications are disclosed. Advantageously, some exemplary embodiments of the methods and apparatus consume less power and increase memory bandwidth (throughput); thereby facilitating their adoption and implementation within power constrained, or otherwise power-sensitive (or power-managed), computing devices. ¶0250 In some implementations, the validation memory 910 can use a very slow memory that has good BER. In other variants, the validation memory 910 can use memory technologies that are optimized for other applications. For example, a DRAM (which is volatile) can be used to quickly and inexpensively mine for POW, whereas a flash memory (which is non-volatile) can be used as a low-power validation memory. In some implementations, the search memory 930 and the validation memory 910 can be co-located such that they both reside within the physical space.); and
output the server network design (¶0250 In some implementations, the validation memory 910 can use a very slow memory that has good BER. In other variants, the validation memory 910 can use memory technologies that are optimized for other applications. For example, a DRAM (which is volatile) can be used to quickly and inexpensively mine for POW, whereas a flash memory (which is non-volatile) can be used as a low-power validation memory. In some implementations, the search memory 930 and the validation memory 910 can be co-located such that they both reside within the physical space. ¶0262 In one exemplary embodiment, each of the processors and/or memories is capable of isolated operation without other processors in the processing system. In one such variant, each search processor 920B can independently throttle up or down its memory bandwidth to optimize its performance.).
Although not explicitly taught by Hulton, Stabrawa teaches in the analogous art of distributed memory pooling:
receive a user input of parameters including a memory ratio of local memory to heterogeneous memory in each server computing device, a first relative throughput when an entire dataset is in local memory on a server computing device, and a second relative throughput when the entire dataset is in heterogeneous memory on the server computing device (¶0438 In some examples, an amount of local primary memory mapped to the address space(s) 1602, 1650 and/or an amount of local primary memory used to cache data in external primary memory may be increased and/or decreased. For example, the amount of local primary memory mapped to the address space(s) 1602, 1650 and/or the amount of local primary memory used to cache data in the external primary memory mapped to the address space(s) 1602, 1650 may be determined based upon memory access behavior of the logic(s) operating with the virtualization instance. In one example, if a relatively large percentage of the mapped portion 1610 is frequently accessed, the amount of local primary memory 1614 used to cache data in the external primary memory mapped to the mapped portion 1610 may be increased. ¶0411 the performance indication(s) 1622, 1678 may be and/or may include ACPI System Resource Affinity Table (SRAT) information, ACPI Static Resource Affinity Table (SRAT) information, ACPI System Locality Distance Information Table (SLIT) information, ACPI Heterogeneous Memory Attribute Table (HMAT) information, ACPI Heterogeneous Memory Attributes (HMA), and/or any other data structures that may indicate one or more relative and/or absolute performance attributes of the local primary memory, the external primary memory, the mappings 1604, 1610, 1652, 1672, and/or of any other portion of memory accessible via the address space 1602, 1650 and/or by the application logic 314 and/or another logic operating with the address space 1602, 1650. ¶0189 Creating or providing the indication of the allocation strategy may be provisioning pooled memory for one or more application logics 314, for one or more of the clients 130, for one or more client groups, for one or more user accounts, for one or more user groups, and/or for predetermined purposes. In a first example, creating the indication of the allocation strategy may include associating a user account with a high priority setting.… In a second example, creating the indication of the allocation strategy may include setting a time limit for a user account, such as a time-of-day limit or a duration-of-use limit.… In a third example, creating the indication of the allocation strategy may include setting a maximum pooled memory usage limit for a user account, thus limiting the amount of pooled memory that may be allocated to the third user account. In a fourth example, creating the indication of the allocation strategy may include creating one or more policies, passed functions, steps, and/or rules that indicate the allocation logic is to prefer to allocate memory on the memory appliances having low network bandwidth when satisfying requests from the clients that have low network bandwidth. In other words, low network bandwidth clients may be provisioned with low network bandwidth pooled memory and/or lower speed pooled memory.…).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton for the following reasons:
(1) a finding that there was some teaching, suggestion, or motivation, either in the references themselves or in the knowledge generally available to one of ordinary skill in the art, to modify the reference or to combine reference teachings, e.g. Hulton ¶0010 teaches that techniques are needed to allow for reduction of refresh requirements, including in such distributed search scenarios as well as others which the volatile memory device may encounter depending on its particular chosen application;
(2) a finding that there was reasonable expectation of success since the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference, e.g. Hulton Abstract teaches error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth since refresh operations have been reduced or eliminated and in another variant an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device and with yet another embodiment error-intolerant applications operate the memory with a reduced or eliminated refresh, and Stabrawa Abstract teaches memory provisioning and particularly describes systems and methods for distributed memory pools; and
(3) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness, e.g. Hulton at least the above cited paragraphs, and Stabrawa at least the inclusively cited paragraphs.
Therefore, it would be obvious to one skilled in the art at the time of the invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and whether there would have been a reasonable expectation of success in doing so." DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1360, 80 USPQ2d 1641, 1645 (Fed. Cir. 2006). See MPEP 2143(G).
Although not explicitly taught by Hulton in view of Stabrawa, Ni teaches in the analogous art of balancing CPU utilization in a massively parallel processing heterogeneous cluster:
each server computing device executing data-processing workloads [and] wherein the enhanced cluster and the baseline cluster deliver equivalent data throughput performance for the data-processing workloads (Summary the processor may determine a performance metric ratio of a performance metric of a second type of server relative to a performance metric of a first type of server for each of a first plurality of sizes of each of a plurality of benchmark datasets to thereby determine a plurality of performance metric ratio values ¶0018 According to yet another aspect of the present disclosure, there is provided a method that includes computing a performance metric ratio of a performance metric of a second type of server relative to a performance metric of a first type of server for each of a first plurality of sizes of each of a plurality of datasets to thereby compute a plurality of performance metric ratio values. The method also may include computing an interpolation function for the plurality of performance metric ratio values usable to compute interpolation performance metric ratios of the second type of server relative to the first type of server for dataset sizes other than the first plurality of sizes. Given a second dataset and for each of the first and second types of servers, the method may include computing an amount of the second dataset to provide to each of the respective types of servers using the interpolation function. The method may also include configuring a load distribution function of a load balancer based on the amount of the second dataset determined for each type of server.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the balancing CPU utilization in a massively parallel processing heterogeneous cluster of Ni with the system for probabilistic refresh in volatile memory devices of Hulton in view of Stabrawa for the following reasons:
(1) a finding that there was some teaching, suggestion, or motivation, either in the references themselves or in the knowledge generally available to one of ordinary skill in the art, to modify the reference or to combine reference teachings, e.g. Hulton ¶0010 teaches that techniques are needed to allow for reduction of refresh requirements, including in such distributed search scenarios as well as others which the volatile memory device may encounter depending on its particular chosen application;
(2) a finding that there was reasonable expectation of success since the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference, e.g. Hulton Abstract teaches error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth since refresh operations have been reduced or eliminated and in another variant an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device and with yet another embodiment error-intolerant applications operate the memory with a reduced or eliminated refresh, and Stabrawa Abstract teaches memory provisioning and particularly describes systems and methods for distributed memory pools and Ni Abstract teaches a system that includes a processor which determines a performance metric ratio of a performance metric of a second type of server relative to a performance metric of a first server type for each of multiple sizes of multiple benchmark datasets to thereby determine a plurality of performance metric ratio values; and
(3) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness, e.g. Hulton in view of Stabrawa at least the above cited paragraphs, and Ni at least the inclusively cited paragraphs.
Therefore, it would be obvious to one skilled in the art at the time of the invention to combine the balancing CPU utilization in a massively parallel processing heterogeneous cluster of Ni with the system for probabilistic refresh in volatile memory devices of Hulton in view of Stabrawa. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and whether there would have been a reasonable expectation of success in doing so." DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1360, 80 USPQ2d 1641, 1645 (Fed. Cir. 2006). See MPEP 2143(G).
Hulton teaches:
Claim 2. The computing system of claim 1, wherein the processing circuitry is further configured to: calculate a Total Cost of Ownership (TCO) savings value indicating a percentage reduction of TCO that is predicted by deploying heterogeneous memory in the server computing devices in accordance with the inputted parameters, wherein the server network design is generated based on the TCO savings value (¶0239 In other words, using the memory device 930 for mining consistent with the present disclosure will intentionally tradeoff errors for other benefits e.g., improved performance, reduced cost, etc. For example, if 3% of results are invalid but the results are being generated 25% faster, the overall acceleration of the system is 21.25% (e.g., 125% faster times 97% accuracy). The overall boost may be even greater in “race” scenarios such as cryptocurrency mining (i.e., only the first miner to locate a solution is rewarded, the second miner loses out even if he/she eventually locates the same solution). ¶0249 In one exemplary embodiment, the search memory 930 is operated to maximize overall search speed (even at the expense of accuracy) by not using, or otherwise disabling, refresh circuitry, whereas the validation memory 910 is used to accurately verify the search (which does not need to be done quickly). A variety of techniques can be used to maximize the search speed and/or minimize costs of the search memory 930. For example, eliminating refresh on the search memory 930 improves upon the internal bandwidth for memory accesses within this search memory 930. Once a predetermined number of errors, and/or a pre-determined BER, are detected by the validation memory 910, the entire contents of the search memory 930 may subsequently be reloaded.).
Although not explicitly taught by Hulton, Stabrawa teaches in the analogous art of distributed memory pooling:
wherein the server network design is generated based on the TCO savings value (¶0065 For example, the client 130 may be a server cluster. By using memory pooling and provisioning, the server cluster need not require servers to have sufficient pre-existing local memory in order to process all anticipated loads. A typical approach to have each individual server to have full capacity memory leads to over-purchasing memory for all servers in order to satisfy exceptional cases needed by some servers, some of the time. Instead, with pooled memory, the server cluster may provision portions of pooled memory where and when needed, thereby saving money, space, and energy, by providing on-demand memory to any capacity. The server cluster may even support memory capacities impossible to physically fit into a single machine. ¶0012 In any one of the example implementations above, the one or more processors are configured to execute the scheduling logic to cause the first application logic to operate in the first computing device and the second application logic to operate in the computing device other than the first computing device based on a determination of optimal performance, power usage, or operational cost associated with the first computing device. ¶0062 The memory pool allocations may span multiple memory appliances. Thus, the memory pooling system 100 makes available memory capacity, larger than what may be possible to fit into the requesting client 130, or a single memory appliance 110, or a single server. The memory capacity made available may be unlimited since any number of memory appliances may be part of the memory pool. The memory pool may be expanded based on various conditions being met. For example, the maximally price-performant memory available may be selected to grow the memory pool in a maximally cost-efficient manner. ¶0063 Instead, with memory pooling, such as the memory pool, one no longer needs to buy expensive large servers with large memory capacity. One may instead buy smaller more energy-efficient and cost-effective servers and extend their memory capacity, on demand, by using memory pooling.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton for the following reasons:
(1) a finding that there was some teaching, suggestion, or motivation, either in the references themselves or in the knowledge generally available to one of ordinary skill in the art, to modify the reference or to combine reference teachings, e.g. Hulton ¶0010 teaches that techniques are needed to allow for reduction of refresh requirements, including in such distributed search scenarios as well as others which the volatile memory device may encounter depending on its particular chosen application;
(2) a finding that there was reasonable expectation of success since the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference, e.g. Hulton Abstract teaches error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth since refresh operations have been reduced or eliminated and in another variant an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device and with yet another embodiment error-intolerant applications operate the memory with a reduced or eliminated refresh, and Stabrawa Abstract teaches memory provisioning and particularly describes systems and methods for distributed memory pools; and
(3) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness, e.g. Hulton at least the above cited paragraphs, and Stabrawa at least the inclusively cited paragraphs.
Therefore, it would be obvious to one skilled in the art at the time of the invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and whether there would have been a reasonable expectation of success in doing so." DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1360, 80 USPQ2d 1641, 1645 (Fed. Cir. 2006). See MPEP 2143(G).
Hulton teaches:
Claim 3. The computing system of claim 2, wherein the TCO savings value is determined by subtracting a product of the server ratio and the relative TCO from one, wherein the relative TCO compares a TCO of an enhanced server computing device equipped with heterogeneous memory relative to a TCO of a baseline server computing device without heterogeneous memory (¶0239 In other words, using the memory device 930 for mining consistent with the present disclosure will intentionally tradeoff errors for other benefits e.g., improved performance, reduced cost, etc. For example, if 3% of results are invalid but the results are being generated 25% faster, the overall acceleration of the system is 21.25% (e.g., 125% faster times 97% accuracy). The overall boost may be even greater in “race” scenarios such as cryptocurrency mining (i.e., only the first miner to locate a solution is rewarded, the second miner loses out even if he/she eventually locates the same solution).).
Although not explicitly taught by Hulton, Stabrawa teaches in the analogous art of distributed memory pooling:
relative TCO compares a TCO of an enhanced server computing device equipped with heterogeneous memory relative to a TCO of a baseline server computing device without heterogeneous memory (¶0065 For example, the client 130 may be a server cluster. By using memory pooling and provisioning, the server cluster need not require servers to have sufficient pre-existing local memory in order to process all anticipated loads. A typical approach to have each individual server to have full capacity memory leads to over-purchasing memory for all servers in order to satisfy exceptional cases needed by some servers, some of the time. Instead, with pooled memory, the server cluster may provision portions of pooled memory where and when needed, thereby saving money, space, and energy, by providing on-demand memory to any capacity. The server cluster may even support memory capacities impossible to physically fit into a single machine. ¶0012 In any one of the example implementations above, the one or more processors are configured to execute the scheduling logic to cause the first application logic to operate in the first computing device and the second application logic to operate in the computing device other than the first computing device based on a determination of optimal performance, power usage, or operational cost associated with the first computing device. ¶0062 The memory pool allocations may span multiple memory appliances. Thus, the memory pooling system 100 makes available memory capacity, larger than what may be possible to fit into the requesting client 130, or a single memory appliance 110, or a single server. The memory capacity made available may be unlimited since any number of memory appliances may be part of the memory pool. The memory pool may be expanded based on various conditions being met. For example, the maximally price-performant memory available may be selected to grow the memory pool in a maximally cost-efficient manner. ¶0063 Instead, with memory pooling, such as the memory pool, one no longer needs to buy expensive large servers with large memory capacity. One may instead buy smaller more energy-efficient and cost-effective servers and extend their memory capacity, on demand, by using memory pooling. ¶0213 a request to restructure a memory pool allocation may be used to migrate data closer to or further away from the client 130, for increasing or decreasing locality and/or for increasing or decreasing performance. This migrating of data may be part of a broader approach for balancing the cost/performance of memory included in the client 130, memory included in the memory appliances, and/or other media capable of holding the data, such as the backing store or other backing stores. Determining how to structure the memory pool allocation may include determining whether to resize the existing regions referenced by the memory pool allocation, whether to create additional regions, and/or whether to replace existing regions with new regions. The allocation logic 412 may resize the existing regions referenced by the memory pool allocation, create additional regions, and/or replace existing regions with new regions using the methods described throughout this disclosure. ¶¶0517-0518).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton for the following reasons:
(1) a finding that there was some teaching, suggestion, or motivation, either in the references themselves or in the knowledge generally available to one of ordinary skill in the art, to modify the reference or to combine reference teachings, e.g. Hulton ¶0010 teaches that techniques are needed to allow for reduction of refresh requirements, including in such distributed search scenarios as well as others which the volatile memory device may encounter depending on its particular chosen application;
(2) a finding that there was reasonable expectation of success since the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference, e.g. Hulton Abstract teaches error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth since refresh operations have been reduced or eliminated and in another variant an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device and with yet another embodiment error-intolerant applications operate the memory with a reduced or eliminated refresh, and Stabrawa Abstract teaches memory provisioning and particularly describes systems and methods for distributed memory pools; and
(3) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness, e.g. Hulton at least the above cited paragraphs, and Stabrawa at least the inclusively cited paragraphs.
Therefore, it would be obvious to one skilled in the art at the time of the invention to combine the distributed memory pooling of Stabrawa with the system for probabilistic refresh in volatile memory devices of Hulton. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and whether there would have been a reasonable expectation of success in doing so." DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1360, 80 USPQ2d 1641, 1645 (Fed. Cir. 2006). See MPEP 2143(G).
Hulton teaches:
Claim 4. The computing system of claim 1, wherein the first relative throughput and the second relative throughput are generated by benchmarking application configured to measure a throughput of data processing of a target computing system (¶0180 Per operation 616, the memory device is operated according to the selected modified refresh scheme and values, and at operation 617, the parameter(s) selected as the basis for the modified scheme (e.g., temperature, time, voltage, etc.) are measured to determine whether the selected modified scheme is still applicable. If so, operation of the device continues, and the method returns to operation 616. If not, the contents of the memory device (or portions thereof subject to the modified refresh scheme based on the monitored parameter(s)) are refreshed per operation 618, and the method returns to operation 612 for selection of a modified (or unmodified) refresh scheme based on the parameter values measured at operation 617. For example, if the lower temperature of the relevant portions of the array in the scenario described above has risen above a prescribed maximum value, then a faster refresh may be dictated).
Hulton teaches:
Claim 5. The computing system of claim 1, wherein the first relative throughput and the second relative throughput are estimated by analyzing historical data of a server network (¶0081 As a brief aside, extant general compute paradigms for memory operation (including refresh) tend to ignore the underlying physical memory mechanism of DRAM storage; i.e., that reliability is a function of time between refreshes for DRAM. Certain types of applications use DRAM memory for very short storage times (sub-60 ms), and in a predictable manner. For example, standard cinematic video is shot at 24 frames/second; i.e., every video frame has a lifetime of ˜42 ms. Thus, the data in a video frame potentially has a shorter lifetime than DRAM memory cell refresh, dependent upon how that video frame information is stored on, and read from, the underlying memory device (which is typically in a highly uniform and deterministic manner)…).
Hulton teaches:
Claim 6. The computing system of claim 1, wherein the server ratio is determined by dividing a nominator value by a denominator value, wherein to calculate the nominator value, one is subtracted from the first relative throughput, and the resulting subtracted value is multiplied together with a product of the memory ratio and the second relative throughput; and to calculate the denominator value, the second relative throughput is multiplied by the first relative throughput and then by the memory ratio increased by one, then the first relative throughput and the product of the memory ratio and the second relative throughput are subtracted from the resulting multiplied value (¶0170 As one example of the foregoing, the frequency (or rate) of read operations to be performed in combination with the size of the memory device (or memory array) may indicate that every memory cell may be probabilistically refreshed (via read operations), every 60 ms. Accordingly, in such an implementation, the duration of the timer may be set for a relatively long period of time (e.g., every five (5) minutes), or until some other event occurs which would somehow alter the above characteristic, and the memory throughput for the memory device may substantially be improved (e.g., on the order of forty percent (40%)) during that period. ¶0204 taking a comparatively long series of events which includes a number of individual memory accesses), which if performed serially by e.g., a single core would result in at least several mandatory refreshes of the memory array in use because the accesses would be spread out in time and would occur in somewhat unpredictable fashion (especially where one access was interlocked to another's completion), and selectively dividing the long series of events up into a number of smaller pieces (the division based on e.g., memory accesses), and allocating the pieces to different cores/memory arrays (or portions of arrays) such that each memory access can act as a refresh event for its respective array/portion, thereby obviating refresh and its associated bandwidth loss.).
Hulton teaches:
Claim 7. The computing system of claim 1, wherein the first relative throughput and the second relative throughput are normalized to a third relative throughput, which is a relative throughput when the entire dataset is spilled onto a local disk on the server computing device (¶0170 As one example of the foregoing, the frequency (or rate) of read operations to be performed in combination with the size of the memory device (or memory array) may indicate that every memory cell may be probabilistically refreshed (via read operations), every 60 ms. Accordingly, in such an implementation, the duration of the timer may be set for a relatively long period of time (e.g., every five (5) minutes), or until some other event occurs which would somehow alter the above characteristic, and the memory throughput for the memory device may substantially be improved (e.g., on the order of forty percent (40%)) during that period.).
Hulton teaches:
Claim 8. The computing system of claim 1, wherein the server computing device network design is generated based on network constraints which are part of the user input (¶0181-0183 FIG. 6C illustrates yet another embodiment of the method for operating a memory device according to the disclosure. As shown in FIG. 6C, at operation 622 of the method 620, a desired level of performance for the memory device/array (e.g., based on application 502) is determined. Next, per operation 624, a probabilistic refresh scheme is selected and applied, including an appropriate temporal constraint for the BER of operation 622. Next, at operation 626, the memory device/array is operated with the selected scheme consistent with (i.e., within) the temporal constraint. During such period, the memory controller tracks non-refreshed cells or regions (e.g., on an individual basis, or on a per-region basis). At operation 628, when the temporal constraint is reached, it is next determined per operation 630 whether any portions have not been read/refreshed (e.g., by an access to those portions) under the probabilistic scheme, such as where for whatever reason the probability distribution was skewed. If so, then per operation 632, such unrefreshed portions are refreshed, and per operation 634, and the temporal constraint and/or the scheme adjusted accordingly so as to obviate further “active” refreshes of the type used in operation 632).
Hulton teaches:
Claim 9. The computing system of claim 1, wherein the server computing device network design is rendered to show a reduction in a total number of server computing devices as a consequence of integrating heterogeneous memory in accordance with the memory ratio, the first relative throughput, and the second relative throughput (¶0077 Yet other exemplary implementations are described, including: (i) use of a known temperature dependency by the memory controller as a basis for “intelligently” choosing not to probabilistically refresh; (ii) selective refresh by the memory controller for only what was missed in a prior probabilistic refresh; (iii) selective offload of comparatively slower refreshes to software; (iv) selective reduction of error correction for certain types or configurations of memory (e.g., 3D Xpoint™); (v) enablement of “latency amortization” or certain applications (e.g., bulk mining); (vi) mixture or combination of homogeneous or heterogeneous memory fetches within memory searches, e.g., to maximize for one or more relevant parameters (such as where each of the memory fetches can be parallelized via allocation to a separate core and/or pipelined, so as to spread out latency associated with each fetch); (vii) repurposing of extant unused mechanisms such as to provide more data bits per fetch (e.g., when ECC is unused, its bits can be used for another purpose)).
Hulton teaches:
Claim 10. The computing system of claim 1, wherein a user interface is provided to receive the user input of the parameters; and the user interface is configured to display different configuration scenarios side-by-side to allow a user to view and compare effects on the data throughput performance of varying the memory ratio, the first relative throughput, and the second relative throughput (¶0189 As a simple example, it may be that a given memory device (or portion thereof) may operate differently in terms of BER performance at a first temperature versus a second temperature (see FIG. 3A). In one variant, these characterizations may be determined at a comparatively high level of granularity, such as on a per-portion basis; e.g., a given portion of a memory device may exhibit reduced BER performance relative to other portions which operate at a lower temperature. As a simple example, consider one portion of an array which operates at temperature T=x, and a second (ostensibly identical) portion of the array which operates at T=x+y. If the BER characterization of the first region indicates a given BER of 1E-18 at refresh rate R, and a BER of 1E-17 for the second region at the same rate R, then if the over-arching application 502 using the array requires only 1E-17 BER, then the refresh can be (i) uniformly applied (i.e., all portions refreshed at rate R) across both portions, or (ii) heterogeneously applied or weighted on a per-portion basis; e.g., R for the second portion, and some lesser value (R−z) for the first portion, thereby freeing yet further bandwidth for the device by minimizing the total refresh across both portions.).
As per claims 11-17,18,19 and 20, the system and manufacture tracks the method of claims 1-7,9,10 and 1, respectively, resulting in substantially similar limitations. The same cited prior art and rationale of claims 1-7,9,10 and 1 are applied to claims 11-17,18,19 and 20, respectively. Hulton discloses that the embodiment may be found as a system and manufacture (Fig. 1 and ¶0270).
Conclusion
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/KURTIS GILLS/Primary Examiner, Art Unit 3624