DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 09/25/2025.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 5-6, 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Siva K Chintu et al. (“Siva”, US Pub 2023/0137946).
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Applicant’s Fig. 5 is from Siva K Chintu et al. (“Siva”, US Pub 2023/0137946)
Regarding independent claim 1 Siva teaches (Fig. 5; wherein some of the same components of Fig. 1-4 are used in Fig. 5; Para 17-31), a voltage regulation system (160) comprising:
a voltage regulator (LDO includes operational amplifier 104 providing a gate drive Vd at gate terminal of pass-transistor PMOS or NMOS 122 to provide Vsl for load 108; Para 4, 17) comprising a gate node having a gate voltage (Vd) and an output node having an output voltage (Vsl); and
an undershoot/overshoot regulation circuit (132, 142; Para 1, 14-16, 20, 22-24) comprising:
an inverse amplifier having an input node (i.e., 1st inverter or buffer inverter’s input end that is directly connected to load, receiving Vsl, prior to 164) directly coupled to the output node of the voltage regulator for receiving the output voltage (i.e., output node of 160 carrying output voltage Vsl that is provided to load, wherein the said inverter or buffer inverter’s input end that is directly connected to load, receiving Vsl, prior to 164), and an output node for outputting a feedback voltage (from terminal 106, Vin) in response to the output voltage (Vsl); and
a capacitor (plurality of capacitors in 132, each selected to be engaged or disengaged by 142, includes top part connected to Vd of 122 and bottom part driven by 142; wherein 142 includes 1st inverter and 2nd inverter(s) 166) having a first node (on top part or plate or end of each capacitor in 132) coupled to the gate node (Vd of 122) and a second node (bottom part or plate of end of each capacitor in 132) coupled to the output node of the inverse amplifier (i.e., said 1st inverter’s output connected to bottom part of C0 in 132, wherein C0 in 132’s top part is connected to Vd of 122).
Regarding claim 5, Siva teaches the transistor is an N-type transistor (LDO includes a gate drive Vd for pass-transistor PMOS or NMOS 122 to provide Vsl for load 108; Para 17).
Regarding independent claim 6, Siva teaches (Fig. 5; wherein some of the same components of Fig. 1-4 are used in Fig. 5; Para 17-31) a voltage regulation system (160) comprising:
a voltage regulator (LDO includes operational amplifier 104 providing a gate drive Vd at gate terminal of pass-transistor PMOS or NMOS 122 to provide Vsl for load 108) comprising a gate node having a gate voltage (Vd) and an output node having an output voltage (Vsl); and
an undershoot/overshoot regulation circuit (132, 142) comprising:
a first inverse amplifier (i.e., 1st inverter or buffer inverter’s input end that is directly connected to load, receiving Vsl, prior to 164), directly coupled to the output node of the voltage regulator, for receiving the output voltage (i.e., output node of 160 carrying output voltage Vsl that is provided to load, wherein the said inverter or buffer inverter’s input end that is directly connected to load, receiving Vsl, prior to 164);
a second inverse amplifier (2nd inverter(s) 166), coupled to an output node of the first inverse amplifier (i.e., 1st inverter or buffer inverter’s output end), having an output node for outputting a feedback voltage (from terminal 106, Vin) in response to the output voltage (Vsl); and
a capacitor (plurality of capacitors in 132, each selected to be engaged or disengaged by 142, includes top part connected to Vd of 122 and bottom part driven by 142; wherein 142 includes 1st inverter and 2nd inverter(s) 166) having a first node (on top part or plate or end of each capacitor in 132) coupled to the gate node (Vd of 122) and a second node (bottom part or plate of end of each capacitor in 132) coupled to the output node of the second inverse amplifier (i.e., said 2nd inverter 166’s output connected to bottom part of C1-n in 132, wherein C1-n in 132’s top part is connected to Vd of 122).
Regarding claim 10, Siva teaches the transistor is an P-type transistor (LDO includes a gate drive Vd for pass-transistor PMOS or NMOS 122 to provide Vsl for load 108; Para 17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2-4, 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Siva (US Pub 2023/0137946), in view of Lin (US Pub 2012/0038332).
Regarding claims 2, 7, Siva teaches the voltage regulator (LDO includes operational amplifier 104 providing a gate drive Vd at gate terminal of pass-transistor PMOS or NMOS 122 to provide Vsl for load 108; Para 4, 17) further comprises:
an operation amplifier (104), comprising:
a first input node configured to receive a reference voltage (Vref);
a second input node coupled to the output node of the voltage regulator (from terminal 106, Vin); and
an output node coupled to the gate node (Vd of 122);
a transistor (pass-transistor PMOS or NMOS 122 to provide Vsl; Para 17), comprising:
the gate node (122’s gate);
a drain node (when 122 is PMOS (drain connecting Vdd) vs. 122 is NMOS (source connecting Vdd, as shown in Fig. 5); Para 4, 17) configured to receive a supply voltage (Vdd); and
a source node (when 122 is PMOS (source connecting Vsl) vs. 122 is NMOS (drain connecting Vsl, as shown in Fig. 5); Para 4, 17) coupled to the output node of the voltage regulator; and
a first resistor (R2), comprising:
a first node coupled to the second input node of the operation amplifier (104); and
a second node coupled to a ground (gnd).
However, Siva fails to teach the first input node and the second input node being a positive node and a negative node, respectively.
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Above Fig. 5 is from Lin (US Pub 2012/0038332)
However, Lin teaches (Fig. 5; Para 27-34) the first input node and the second input node being a positive node (op-amp A1’s 1st input is + receiving Vref; Para 5-7, 27-28) and a negative node (op-amp A1’s 2nd input is - receiving feedback voltage Vf, from a voltage divider 41, wherein 41 receives regulated output Vout from source of pass transistor MNO, and MNO’s drain is also connected to Vin; Para 5-7, 27-28), respectively.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Siva’s voltage regulation system to include op-amp comprising the first input node and the second input node being a positive node and a negative node, respectively, as disclosed by Lin, as doing so would have provided an improved pole-zero tracking functionality, while maintaining steady regulated output, and preventing any overshoot/undershoot transient events, as taught by Lin (Para 3, 34 and abstract).
Regarding claims 3, 8, Siva teaches the voltage regulator (LDO includes operational amplifier 104 providing a gate drive Vd at gate terminal of pass-transistor PMOS or NMOS 122 to provide Vsl for load 108; Para 4, 17) further comprises:
an operation amplifier (104), comprising:
a first input node configured to receive a reference voltage (Vref);
a second input node (from terminal 106, Vin); and
an output node coupled to the gate node (Vd of 122);
a transistor (pass-transistor PMOS or NMOS 122 to provide Vsl; Para 17), comprising:
the gate node (122’s gate);
a drain node (when 122 is PMOS (drain connecting Vdd) vs. 122 is NMOS (source connecting Vdd, as shown in Fig. 5); Para 4, 17) configured to receive a supply voltage (Vdd); and
a source node (when 122 is PMOS (source connecting Vsl) vs. 122 is NMOS (drain connecting Vsl, as shown in Fig. 5); Para 4, 17) coupled to the output node of the voltage regulator;
a first resistor (R2), comprising:
a first node coupled to the second input node of the operation amplifier (104); and
a second node coupled to a ground (gnd); and
a second resistor (R1), comprising:
a first node coupled to the source node of the transistor (when 122 is PMOS (source connecting Vsl) vs. 122 is NMOS (drain connecting Vsl, as shown in Fig. 5); Para 4, 17); and
a second node coupled to the first node of the first resistor (R1’s 2nd end coupled to R2’s 1st end on terminal 106).
However, Siva fails to teach the first input node and the second input node being a positive node and a negative node, respectively.
However, Lin teaches (Fig. 5; Para 27-34) the first input node and the second input node being a positive node (op-amp A1’s 1st input is + receiving Vref; Para 5-7, 27-28) and a negative node (op-amp A1’s 2nd input is - receiving feedback voltage Vf, from a voltage divider 41, wherein 41 receives regulated output Vout from source of pass transistor MNO, and MNO’s drain is also connected to Vin; Para 5-7, 27-28), respectively.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Siva’s voltage regulation system to include op-amp comprising the first input node and the second input node being a positive node and a negative node, respectively, as disclosed by Lin, as doing so would have provided an improved pole-zero tracking functionality, while maintaining steady regulated output, and preventing any overshoot/undershoot transient events, as taught by Lin (Para 3, 34 and abstract).
Regarding claims 4, 9, Siva teaches a load (108), comprising: a first node coupled to the output node of the voltage regulator (Vsl); and a second node.
However, Siva fails to teach load’s second node coupled to the ground.
However, Lin teaches (Fig. 5; Para 27-34) load’s (Rl) second node coupled to the ground (Gnd).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Siva’s voltage regulation system to include op-amp comprising the first input node and the second input node being a positive node and a negative node, respectively, and also having the load’s second node coupled to the ground, as disclosed by Lin, as doing so would have provided an improved pole-zero tracking functionality, while maintaining steady regulated output, and preventing any overshoot/undershoot transient events, as taught by Lin (Para 3, 34 and abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Regarding independent claims 1-3, 5, Suzuki (US Pub 2016/0226378, which could easily be used for another 102(a)(1) for at least claims 1, 5), a voltage regulation system (Fig. 1; Para 20-27) comprising: a voltage regulator (LDO includes op-amp 11 providing a gate signal for pass-transistor PMOS or NMOS 13, to provide a regulated Vout. 11 compares Vref & Vfb to provide gate drive voltage for 13) comprising a gate node having a gate voltage (op-amp 11 providing a gate signal for pass-transistor PMOS or NMOS 13) and an output node having an output voltage (regulated Vout); and an undershoot/overshoot regulation circuit (16-19) comprising: an inverse amplifier (17-18) having an input node (17-18) directly coupled to the output node (13’s output) of the voltage regulator for receiving the output voltage (Vout), and an output node for outputting a feedback voltage (Vfb from mid-node of 14) in response to the output voltage (Vout); and a capacitor (15) having a first node coupled to the gate node (15’s 1st node coupled to gate of 13 adjust gate drive voltage) and a second node coupled to the output node of the inverse amplifier (15’s 2nd node coupled to 18’s output, using feedback loop operation).
Ferlito et al. (US Pub 2024/0036595) teaches an LDO regulator with undershoot and overshoot performance, using feedback voltage and direct output voltage of the regulator.
Gupta et al. (US Pub 2020/0125126) teaches voltage regulator circuit with high power supply rejection ratio to perform undershoot/overshoot operation.
Ueda (US Pat 5247241) teaches frequency and capacitor based constant current source to control an overshoot/undershoot operation of a regulator.
Matyscak (US Pub 2022/0011798) teaches voltage regulator having circuit responsive to load transients to perform overshoot/undershoot operation.
Onody et al. (US Pub 2022/0187862) teaches high-speed low-impedance boosting LDO regulator to perform overshoot/undershoot operation.
Sugiura et al. (US Pub 2016/0181924) teaches LDO voltage regulator configured to perform an overshoot/undershoot operation on LDO regulators includes a powering signal for op-amp, gate voltage of the pass transistors and output of the LDO voltage regulator.
Bonto (US Pat 6690147) teaches LDO voltage regulator having efficiency current frequency compensation to perform overshoot/undershoot operation on the gate voltage based on output voltage of the LDO regulator.
Tadeparthy et al. (US Pub 2011/0156670) teaches using passive bootstrapped charge pump, to perform overshoot/undershoot operation for pass transistor NMOS power device based on a LDO regulator’s output.
Sekerli et al. (US Pub 2022/0253082) teaches slew rate improvement in multistage differential amplifiers for fast transient response of a linear regulator application, using overshoot and undershoot operation.
Suzuki (US pub 2016/0226378) teaches voltage regulator configured to perform overshoot/undershoot.
Kuttner (US Pat 9312824) teaches low-noise low-dropout regulator.
Huang et al. (US Pub 2015/0123635) teaches voltage regulator apparatus with sensing modules and related operating method thereof.
Oikarinen (US Pat 9671803) teaches low dropout supply asymmetric dynamic biasing.
Simmons et al. (US Pub 2012/0086420) teaches capless regulator overshoot and undershoot regulation circuit.
Hu et al. (US Pub 2019/0041885) teaches adaptive bulk-bias technique to improve supply noise rejection, load regulation and transient performance of voltage regulators.
Edwards (US Pat 5850139) teaches load pole stabilized voltage regulator circuit.
Kase et al. (US Pub 2006/0012356) teaches voltage regulator with adaptive frequency compensation.
Tomioka et al. (US Pub 2015/0168971) teaches voltage regulator to suppress overshoot and undershoot.
Duong et al. (US Pub 2017/0126118) teaches regulator circuit with undershoot operation.
Chern et al. (US Pub 2014/0266114) teaches voltage regulator circuit has bias circuit outside amplifier, which is configured to supply bias signal to gate of transistor configured to operate in saturation mode based on bias signal supplied by bias circuit.
Ke et al. (US Pat 7109690) teaches fast-disabled voltage regulator circuit with low-noise feedback loop and operating method thereof.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/NUSRAT QUDDUS/Examiner, Art Unit 2838