Prosecution Insights
Last updated: July 17, 2026
Application No. 18/526,242

PATTERN DEFECT INSPECTION DEVICE AND PATTERN DEFECT INSPECTION METHOD

Non-Final OA §103
Filed
Dec 01, 2023
Priority
Dec 07, 2022 — RE 10-2022-0170050
Examiner
WILLIAMS, REBECCA COLETTE
Art Unit
2677
Tech Center
2600 — Communications
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Non-Final)
50%
Grant Probability
Moderate
2-3
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
4 granted / 8 resolved
-12.0% vs TC avg
Strong +57% interview lift
Without
With
+57.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
18 currently pending
Career history
35
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
94.9%
+54.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 8 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendments to claims have overcome the previously held objection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, and 7-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa (JP 2021165660 A) in view of Kuroda (JP 5277008 B2), Ogi (US 20060133660 A1 ), and Weiner (JP 5238659 B2). With respect to claim 1, Ogawa teaches a pattern defect inspection device (“The present invention relates to a multi-electron beam inspection apparatus and a multi-electron beam inspection method. For example, the present invention relates to an inspection device that inspects using a secondary electron image of a pattern emitted by irradiating a multi-beam with an electron beam.” Page 2 Technical Field) comprising: an inspection apparatus configured to inspect a pattern on a substrate (“In FIG. 1, the inspection device 100 for inspecting a pattern formed on a substrate is an example of a multi-electron beam inspection device.” Page 3 Embodiment 1, paragraph 1); a database storing a pattern layout including a plurality of defect patterns from the inspection apparatus, and a target measurement number (“There is a "die to database (die database) inspection" that generates data (reference image) and compares this with the measurement image that is the measurement data obtained by imaging the pattern. The captured image is sent to the comparison circuit as measurement data. In the comparison circuit, after the images are aligned with each other, the measurement data and the reference data are compared according to an appropriate algorithm…” page 2 Background Art paragraph 2); and a processor (“In the above description, the series of "~ circuits" includes a processing circuit, and the processing circuit includes an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor device, and the like.” Page 12 paragraph 8) configured to set a plurality of inspection regions of the inspection apparatus based on the pattern layout (“In the first embodiment, the sub-irradiation region 29 acquired by the scanning operation of one primary electron beam 10i is further divided into a plurality of mask die regions, and the mask die region is used as a unit region of the image to be inspected.” Page 12 paragraph 3), arrange the plurality of inspection regions based on the region defect pattern (“The substrate 101 is arranged on the stage 105, for example, with the pattern forming surface facing upward” page 4 paragraph 1). Ogawa does not explicitly teach the database storing an FOV size, nor the processor being configured to search for a region defect pattern existing in at least one of the plurality of inspection regions in the pattern layout using a binary search, remove at least one overlapping region from the plurality of inspection regions based on the FOV size, and select an inspection region, other than the at least one overlapping region, from among the plurality of inspection regions, as a final inspection region. Kuroda teaches the database storing an FOV size (“Then, the optimum measurement conditions for various patterns are registered in the database. At this time, as pattern information, the density of the pattern inside and outside the FOV, the ratio of the measurement target pattern to the non-measurement target pattern in the FOV, the vertical and horizontal symmetry of the conductive member and the insulating member outside the FOV, or other charge related The data indicating the information to be quantified is quantified, and the quantified value is associated with the optimal measurement condition (optical condition of the apparatus) to form a database” page 4 paragraph 9), and optimizing inspection regions (“When measuring multiple points and overlapping each other, it is necessary to optimize the conditions considering the double charging effect of the overlapped part, including the irradiation history of the previous point measurement.” Page 6 paragraph 10). Kuroda is analogous art in the same field of endeavor as the claimed invention. Kuroda is directed toward pattern matching substrate based on FOV (“In this embodiment, a database (optimized measurement condition database) in which information related to pattern density and the like obtained from design data of semiconductor devices is stored in association with information related to pattern density and measurement conditions (optical conditions of the apparatus). A method for deriving an appropriate apparatus condition will be described” page 4 paragraph 8). A person of ordinary skill before the effective filing date of the claimed invention would have found it obvious to combine the system of Ogawa with Kuroda, by utilizing Kuroda’s teachings of FOV an optimized measurement, with the expectation that doing so would lead to improvements in operation reliability (“Next, the actual pattern is verified by SEM using the optimum conditions obtained by the simulation. Finally, the simulation result is fitted based on the measurement result of the SEM to improve the reliability of the simulation and create a database of optimum conditions for pattern-dependent charging.” Page 6 paragraph 3) Ogi teaches identifying, based on the FOV size (“In other words, the defect detector 45 excludes defect candidates overlapping with the defects included in the reference image from the plurality of defect candidates on the basis of positional information of the defects included in the reference image (Step S16).” Paragraph 0041), at least one overlapping region wherein at least two of the plurality of inspection regions overlap each other (see figure 3),remove the at least one overlapping region from the plurality of inspection regions (see figure 3), and selecting an inspection region, other than the at least one overlapping region, from among the plurality of inspection regions, as a final inspection region (see figure 3). Ogi is analogous art in the same field of endeavor as the claimed invention. Ogi is directed towards detecting defects (“The present invention relates to a technique for detecting a defect existing in a pattern on an object.” Paragraph 0002). A person of ordinary skill in the art would have found it obvious to combine the teachings of Ogawa and Kuroda with Ogi, by utilizing Ogi’s defect detection strategy in combination with Ogawa’s inspection methodology, with the expectation that doing so would lead to improve accuracy of defect point detection (“According to one preferred embodiment of the present invention, since the defect detector excludes a defect candidate overlapping with the defect included in the reference image from at least one defect candidate also on the basis of feature value of the defect included in the reference image and feature value of at least one defect candidate, it is possible to detect a defect existing in another block area more accurately.” Paragraph 0009). Weiner teaches the processor being configured to search for a region defect pattern existing in at least one of the plurality of inspection regions in the pattern layout using a binary search (“In the illustrated embodiment of FIG. 3A, a binary search for defects is first performed along the x direction.” Page 4 paragraph 4). Weiner is analogous art in the same field of endeavor as the claimed invention. Weiner is directed toward semiconductor defect detection apparatus (“The present invention relates to a method and apparatus for detecting electrical defects in a semiconductor device or test structure having a plurality of features specifically designed to create a potential that changes during voltage contrast inspection. More specifically, the present invention relates to a voltage contrast technique for detecting open and short circuit type defects in circuit or test structure features.” Technical Field). A person of ordinary skill in the art before the effective filing date of the claimed invention, would have found it obvious to combine the system of Ogawa, Kuroda, and Ogi with Weiner, by incorporating Weiner’s inspection methodology into Ogawa’s inspection method with the expectation that doing so would lead to the combine system being able to detect additional types of defects commonly present in semiconductors (“Another more important disadvantage of the conventional voltage contrast test structure is that they can only detect hard opens and shorts. This is a very important problem, for example in the Cu metallization process, but a significant percentage of the defects are partial opens. This partial open at the via or at the metal line is a concern for reliability and reduces the parametric performance of the semiconductor chip.” Page 2 paragraph 4) With respect to claim 2, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Kuroda further teaches wherein the processor is configured to set a point corresponding to one defect pattern, among the plurality of defect patterns, in the pattern layout as a first point (“After creating such a database, a measurement point on the design data or an FOV for measuring the measurement point is set. Based on the setting, the FOV pattern information is calculated using the pattern information of the design data, and the optimal measurement stored in association with the calculated FOV pattern information by referring to the database. Derive conditions.” Pages 4 (bottom) - 5 (top)) Weiner teaches search for a first defect pattern within a range of a first distance in a first direction from the first point (“For example, the electron beam can be moved relative to the test structure by a predetermined incremental distance” page 4 paragraph 3). With respect to claim 3, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 2. Weiner further teaches wherein the processor is configured to search for a second defect pattern existing within a range of a second distance in a second direction from the first point in the pattern layout (See Examiner Figure 1), and the second direction perpendicular to the first direction (see figure 3A). PNG media_image1.png 1326 850 media_image1.png Greyscale Examiner Figure 1: Figure 3B from Weiner Translated With respect to claim 4, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 3. Ogawa further teaches wherein the processor is configured to set the second defect pattern as a region defect pattern of a first inspection region based on the first point (“It is preferable that the mask die regions are configured so that the margin regions overlap each other so that the image is not omitted.” Page 12 paragraph 3). With respect to claim 5, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Ogawa further teaches wherein the processor is configured to place each of the plurality of inspection regions based on the plurality of defect patterns (“As the alignment step (S120), the alignment unit 57 reads out a mask die image to be an image to be inspected and a composite reference image corresponding to the mask die image, and aligns both images in sub-pixel units smaller than pixels. .. For example, the alignment may be performed by the method of least squares.” Page 12 paragraph 5) and to search for the region defect pattern of each of the plurality of inspection regions (“As a comparison step (S122), the comparison unit 58 compares the mask die image (secondary electron image) with the composite reference image pixel by pixel.” Page 12 paragraph 6). With respect to claim 7, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Kuroda further teaches wherein the inspection apparatus is at least one of a scanning electron microscope (SEM) (“As an embodiment for achieving the above object, in a method or apparatus for measuring a pattern using a scanning probe such as a scanning electron microscope, an experiment and simulation are performed in advance on a charging state depending on a pattern inside and outside the field of view” page 4 paragraph 6). With respect to claim 8, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Ogi further teaches wherein the removing the at least one overlapping region includes determining whether the plurality of inspection regions overlap with a reference region (see figure 3) Weiner further teaches a processor configured to set the reference region based on an order in which the plurality of inspection regions are arranged (See Examiner Figure 1 and Figure 3A). With respect to claim 9, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 8. Ogi further teaches wherein the processor is configured to perform the removing the at least one overlapping region after the setting the reference region from the plurality of inspection regions (see figure 3). With respect to claim 10, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 8. Kuroda further teaches wherein the FOV size includes a first horizontal directional length that is a first FOV size in a first direction and a second vertical directional length that is a second FOV size in a second direction perpendicular to the first direction (see figures 1-3 element 104), and the processor is configured to determine that a determination target region overlaps with the reference region when at least one of a horizontal distance between a first reference point of the reference region and a second reference point of the determination target region, among the plurality of inspection regions, in the first direction is less than the first horizontal directional length or a vertical distance between the first reference point and the second reference point in the second direction is less than the second vertical directional length (“Based on the setting, the FOV pattern information is calculated using the pattern information of the design data, and the optimal measurement stored in association with the calculated FOV pattern information by referring to the database. “ page 5 paragraph 1and “Next, by setting the position and size (magnification) of the FOV on the design data, values relating to the area of the chromium pattern and the glass portion in the FOV are calculated with reference to the design data.” Page 6 paragraph 4 and figures 1-3). With respect to claim 11, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Ogi further teaches wherein the removing the at least one overlapping region includes determining whether the plurality of inspection regions overlap, and the processor is configured to stop the determining whether the plurality of inspection regions overlap when a number of inspection regions determined not to overlap reaches the target measurement number (“Only one defect may exist in a reference image, though a plurality of defects are detected in the reference image in the above-discussed preferred embodiments. In this case, at least one defect candidate which includes a defect candidate derived from the defect of the reference image is detected from a target image, and one defect candidate overlapping with the defect of the reference image is excluded from at least one defect candidate on the basis of positional infomation of the defect of the reference image (and also, a feature value(s) of the defect in the reference image and a feature value(s) of at least one defect candidate)” paragraph 0068). With respect to claim 12, Ogawa teaches a pattern defect inspection device (“The present invention relates to a multi-electron beam inspection apparatus and a multi-electron beam inspection method. For example, the present invention relates to an inspection device that inspects using a secondary electron image of a pattern emitted by irradiating a multi-beam with an electron beam.” Page 2 Technical Field) comprising: an inspection apparatus configured to inspect a pattern on a substrate (“In FIG. 1, the inspection device 100 for inspecting a pattern formed on a substrate is an example of a multi-electron beam inspection device.” Page 3 Embodiment 1, paragraph 1); a database storing a pattern layout including a plurality of defect patterns from the inspection apparatus , a target measurement number (“There is a "die to database (die database) inspection" that generates data (reference image) and compares this with the measurement image that is the measurement data obtained by imaging the pattern. The captured image is sent to the comparison circuit as measurement data. In the comparison circuit, after the images are aligned with each other, the measurement data and the reference data are compared according to an appropriate algorithm…” page 2 Background Art paragraph 2), a target inspection time (“irradiation time” page 8 paragraph 2) and a processor (“In the above description, the series of "~ circuits" includes a processing circuit, and the processing circuit includes an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor device, and the like.” Page 12 paragraph 8) configured to set a plurality of inspection regions of the inspection apparatus based on the pattern layout (“In the first embodiment, the sub-irradiation region 29 acquired by the scanning operation of one primary electron beam 10i is further divided into a plurality of mask die regions, and the mask die region is used as a unit region of the image to be inspected.” Page 12 paragraph 3) and correcting the target measurement number (“There is a "die to database (die database) inspection" that generates data (reference image) and compares this with the measurement image that is the measurement data obtained by imaging the pattern. The captured image is sent to the comparison circuit as measurement data. In the comparison circuit, after the images are aligned with each other, the measurement data and the reference data are compared according to an appropriate algorithm…” page 2 Background Art paragraph 2) Ogawa does not explicitly teach the database storing an FOV size, nor the processor being configured to search for a region defect pattern existing in at least one of the plurality of inspection regions in the pattern layout using a binary search, remove at least one overlapping region from the plurality of inspection regions based on the FOV size, and select an inspection region, other than the at least one overlapping region, from among the plurality of inspection regions, as a final inspection region. Kuroda teaches the database storing an FOV size (“Then, the optimum measurement conditions for various patterns are registered in the database. At this time, as pattern information, the density of the pattern inside and outside the FOV, the ratio of the measurement target pattern to the non-measurement target pattern in the FOV, the vertical and horizontal symmetry of the conductive member and the insulating member outside the FOV, or other charge related The data indicating the information to be quantified is quantified, and the quantified value is associated with the optimal measurement condition (optical condition of the apparatus) to form a database” page 4 paragraph 9), wherein the processor is configured to measure a number of defect patterns in each of the plurality of inspection regions based on the FOV size (see figures 1-3) Kuroda is analogous art in the same field of endeavor as the claimed invention. Kuroda is directed toward pattern matching substrate based on FOV (“In this embodiment, a database (optimized measurement condition database) in which information related to pattern density and the like obtained from design data of semiconductor devices is stored in association with information related to pattern density and measurement conditions (optical conditions of the apparatus). A method for deriving an appropriate apparatus condition will be described” page 4 paragraph 8). A person of ordinary skill before the effective filing date of the claimed invention would have found it obvious to combine the system of Ogawa with Kuroda, by utilizing Kuroda’s teachings of FOV an optimized measurement, with the expectation that doing so would lead to improvements in operation reliability (“Next, the actual pattern is verified by SEM using the optimum conditions obtained by the simulation. Finally, the simulation result is fitted based on the measurement result of the SEM to improve the reliability of the simulation and create a database of optimum conditions for pattern-dependent charging.” Page 6 paragraph 3) Ogi teaches a pattern defect inspection device comprising, based on FOV size (“In other words, the defect detector 45 excludes defect candidates overlapping with the defects included in the reference image from the plurality of defect candidates on the basis of positional information of the defects included in the reference image (Step S16).” Paragraph 0041): remove an overlapping region of at least one of the plurality of inspection regions overlapping the reference region (see figure 3), select an inspection region from among the plurality of inspection regions, other than the overlapping region which is removed, as a final inspection region (see figure 3), and correct the FOV size (“The substrate 9 is not limited to a substrate for confirmation of the process margin, and the substrate 9 may be a semiconductor substrate produced by applying a constant process parameter. Generally, in a semiconductor substrate, by positional dependence in various processes, a shape or the like of a pattern is changed depending on a position as the above-described substrate for confirmation of the process margin.” Paragraph 0073). Ogi is analogous art in the same field of endeavor as the claimed invention. Ogi is directed towards detecting defects (“The present invention relates to a technique for detecting a defect existing in a pattern on an object.” Paragraph 0002). A person of ordinary skill in the art would have found it obvious to combine the teachings of Ogawa and Kuroda with Ogi, by utilizing Ogi’s defect detection strategy in combination with Ogawa’s inspection methodology, with the expectation that doing so would lead to improve accuracy of defect point detection (“According to one preferred embodiment of the present invention, since the defect detector excludes a defect candidate overlapping with the defect included in the reference image from at least one defect candidate also on the basis of feature value of the defect included in the reference image and feature value of at least one defect candidate, it is possible to detect a defect existing in another block area more accurately.” Paragraph 0009). Weiner teaches determining whether the plurality of inspection regions overlap by setting one of the plurality of inspection regions as a reference region, the reference region set based on an order in which the number of defect patterns increases (See examiner figure 1 and figure 3A) and reselecting the plurality of inspection regions (See examiner figure 1 and figure 3A) Weiner is analogous art in the same field of endeavor as the claimed invention. Weiner is directed toward semiconductor defect detection apparatus (“The present invention relates to a method and apparatus for detecting electrical defects in a semiconductor device or test structure having a plurality of features specifically designed to create a potential that changes during voltage contrast inspection. More specifically, the present invention relates to a voltage contrast technique for detecting open and short circuit type defects in circuit or test structure features.” Technical Field). A person of ordinary skill in the art before the effective filing date of the claimed invention, would have found it obvious to combine the system of Ogawa, Kuroda, and Ogi with Weiner, by incorporating Weiner’s inspection methodology into Ogawa’s inspection method with the expectation that doing so would lead to the combine system being able to detect additional types of defects commonly present in semiconductors (“Another more important disadvantage of the conventional voltage contrast test structure is that they can only detect hard opens and shorts. This is a very important problem, for example in the Cu metallization process, but a significant percentage of the defects are partial opens. This partial open at the via or at the metal line is a concern for reliability and reduces the parametric performance of the semiconductor chip.” Page 2 paragraph 4) With respect to claim 13, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 12. Ogawa further teaches wherein, the processor is configured to transfers the final inspection region to the inspection apparatus when an inspection time for the final inspection region is determined to be equal to or less than the target inspection time (“Then, the multi-primary electron beam 20 for inspection (for image acquisition) is formed by the beam group that has passed through the limiting aperture substrate 213 formed from the time when the beam is turned on to the time when the beam is turned off” page 5 paragraph 6), and the inspection apparatus is configured to inspect the pattern on the substrate corresponding to the final inspection region (“Then, the multi-primary electron beam 20 for inspection (for image acquisition) is formed by the beam group that has passed through the limiting aperture substrate 213 formed from the time when the beam is turned on to the time when the beam is turned off” page 5 paragraph 6). With respect to claim 14, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 12. Kuroda teaches wherein the measuring the number of defect patterns in each of the plurality of inspection regions includes setting, as a first point, a point corresponding to one of the plurality of defect patterns (“After creating such a database, a measurement point on the design data or an FOV for measuring the measurement point is set. Based on the setting, the FOV pattern information is calculated using the pattern information of the design data, and the optimal measurement stored in association with the calculated FOV pattern information by referring to the database. Derive conditions.” Pages 4 (bottom) - 5 (top)) Weiner teaches searching for first defect patterns within a range of a first distance in a first direction from the first point (“For example, the electron beam can be moved relative to the test structure by a predetermined incremental distance” page 4 paragraph 3), searching for a second defect pattern, among the first defect patterns (“For example, the electron beam can be moved relative to the test structure by a predetermined incremental distance” page 4 paragraph 3), within in a range of a second distance in a second direction perpendicular to the first direction from the first point in the pattern layout in a corresponding one of the first defect pattern (See examiner figure 1 and figure 3A), and determining the number of defect patterns based on a number of the second defect patterns (see examiner figure 1). With respect to claim 15, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 14. Kuroda further teaches wherein the FOV size includes a first horizontal directional length that is an FOV size in the first direction and a second vertical directional length that is an FOV size in the second direction perpendicular to the first direction (see figures 1-3 element 104), and the first distance corresponds to the first horizontal directional length (see figures 1-3 element 104), and the second distance corresponds to the second vertical directional length (see figures 1-3 element 104). With respect to claim 16, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 12. Ogi further teaches wherein the processor is configured to stop the determining whether the plurality of inspection regions overlap when a number of non-overlapping inspection regions determined not to overlap from the plurality of inspection regions reaches the target measurement number (“Only one defect may exist in a reference image, though a plurality of defects are detected in the reference image in the above-discussed preferred embodiments. In this case, at least one defect candidate which includes a defect candidate derived from the defect of the reference image is detected from a target image, and one defect candidate overlapping with the defect of the reference image is excluded from at least one defect candidate on the basis of positional infomation of the defect of the reference image (and also, a feature value(s) of the defect in the reference image and a feature value(s) of at least one defect candidate)” paragraph 0068), and select at least one of the non-overlapping inspection region as the final inspection region (“see figure 4). Claim 6 and 17-20 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, Kuroda, Ogi, and Weiner as applied to claim 1 above, and further in view of Nojima (CN 110896038 A). With respect to claim 6, Ogawa, Kuroda, Ogi, and Weiner teach the pattern defect inspection device of claim 1. Weiner teaches wherein the processor is configured to arrange the plurality of inspection regions in descending order (See Examiner Figure 1 and Figure 3A), but does not teach doing so according to a pattern number. Nojima teaches a pattern number of a region defect pattern (“wiring pattern respectively number given in any order (pattern number) (first 1 number, second 2 number” page 9 paragraph 5). Nojima is analogous art in the same field of endeavor as the claimed invention. Nojima is directed towards defect inspection (“Embodiments of the present invention relates to a defect inspection device and defect inspecting method” page 2 Technical Field). A person of ordinary skill in the art would have found it obvious to incorporate the concept of numbered patterns into the combined system of Ogawa, Kuroda, Ogi, and Weiner, by numbering the defect patterns present in the combined system, with the expectation that doing so would result in a reduction in inspection time (“it is possible to shorten the inspection time of the defect inspection in semiconductor manufacturing” page 21 paragraph 5) With respect to claim 17, Ogawa, Kuroda, Ogi, and Weiner render obvious all of the claim limitations as in consideration of claim 1, due to claim 17 being directed to the method claim 1’s device is configured to perform. Ogi further teaches inspecting a pattern on a substrate corresponding to the final inspection region (“With this operation, a binary differential image (hereinafter, referred to as "first differential image") is acquired while acquiring the reference image, and the acquired differential image is stored in a memory of the reference image inspection circuit 42 temporarily (Step S22). At this time, each pixel value of the reference image is also inputted to the second image memory 43 for the target image inspection.” Paragraph 0035). Weiner additionally teaches wherein the processor is configured to arrange the plurality of inspection regions in descending order (See Examiner Figure 1 and Figure 3A), but does not teach doing so according to a pattern number . Nojima teaches a pattern number of a region defect pattern (“wiring pattern respectively number given in any order (pattern number) (first 1 number, second 2 number” page 9 paragraph 5). Nojima is analogous art in the same field of endeavor as the claimed invention. Nojima is directed towards defect inspection (“Embodiments of the present invention relates to a defect inspection device and defect inspecting method” page 2 Technical Field). A person of ordinary skill in the art would have found it obvious to incorporate the concept of numbered patterns into the combined system of Ogawa, Kuroda, Ogi, and Weiner, by numbering the defect patterns present in the combined system, with the expectation that doing so would result in a reduction in inspection time (“it is possible to shorten the inspection time of the defect inspection in semiconductor manufacturing” page 21 paragraph 5) With respect to claim 18, Ogawa, Kuroda, Ogi, Weiner and Nojima teach the pattern defect inspection method of claim 17. Kuroda teaches wherein the searching for the region defect patterns include: setting, as a first point, a point corresponding to one of the plurality of defect patterns (“After creating such a database, a measurement point on the design data or an FOV for measuring the measurement point is set. Based on the setting, the FOV pattern information is calculated using the pattern information of the design data, and the optimal measurement stored in association with the calculated FOV pattern information by referring to the database. Derive conditions.” Pages 4 (bottom) - 5 (top)) Weiner further teaches searching for a first defect pattern within a range of a first distance in a first direction from the first point (“For example, the electron beam can be moved relative to the test structure by a predetermined incremental distance” page 4 paragraph 3), searching for a second defect pattern, among the first defect patterns (“For example, the electron beam can be moved relative to the test structure by a predetermined incremental distance” page 4 paragraph 3), within a range of a second distance in a second direction perpendicular to the first direction from the first point in the pattern layout (see examiner figure 1 and figure 3A), and determine a number of the defect patterns based on a number of second defect patterns (see examiner figure 1), and wherein the searching for the region defect pattern is repeated for each of the plurality of inspection regions (see examiner figure 1 and figure 3A). With respect to claim 19, Ogawa, Kuroda, Ogi, Weiner and Nojima teach the pattern defect inspection method of claim 18. Kuroda further teaches wherein the first distance corresponds to a first horizontal directional length, which is an FOV size in the first direction, and the second distance corresponds to a second vertical directional length, which is an FOV size in the second direction perpendicular to the first direction (see figures 1-3 element 104). With respect to claim 20, Ogawa, Kuroda, Ogi, Weiner and Nojima teach the pattern defect inspection method of claim 19. Ogawa further teaches wherein the selecting the final inspection region includes determining whether an expected inspection time for the final inspection region is equal to a target inspection time (“Then, the multi-primary electron beam 20 for inspection (for image acquisition) is formed by the beam group that has passed through the limiting aperture substrate 213 formed from the time when the beam is turned on to the time when the beam is turned off” page 5 paragraph 6), but does not teach selecting the final inspection region changing the size of the plurality of inspection regions and the number of inspection regions when the expected inspection time is greater than the target inspection time Weiner additionally teaches selecting the final inspection region changing the size of the plurality of inspection regions and the number of inspection regions (see examiner figure 1 and figure 3A). Response to Arguments Applicant’s arguments over the previously made 103 rejections (see pages 11-12 of applicant’s remarks filed 02/23/2026), have been fully considered and are persuasive, however upon further search and consideration prior art was found that taught the limitations in contention (limitations previously taught by Meng). Accordingly, updated rejections have been provided (see above claim mapping). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to REBECCA C WILLIAMS whose telephone number is (571)272-7074. The examiner can normally be reached M-F 7:30am - 4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew W Bee can be reached at (571)270-5183. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REBECCA COLETTE WILLIAMS/Examiner, Art Unit 2677 /ANDREW W BEE/Supervisory Patent Examiner, Art Unit 2677
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Prosecution Timeline

Show 2 earlier events
Dec 26, 2025
Interview Requested
Jan 08, 2026
Applicant Interview (Telephonic)
Jan 08, 2026
Examiner Interview Summary
Feb 23, 2026
Response Filed
Jun 04, 2026
Non-Final Rejection mailed — §103
Jun 25, 2026
Interview Requested
Jul 07, 2026
Applicant Interview (Telephonic)
Jul 07, 2026
Examiner Interview Summary

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Applications granted by this same examiner with similar technology

Patent 12633080
SYSTEMS AND METHODS FOR INSPECTION OF GAS PLUME USING OBJECT DETECTION AND SEGMENTATION MODELS
1y 5m to grant Granted May 19, 2026
Patent 12626335
IMAGE PROCESSING METHOD, ELECTRONIC DEVICE, AND STORAGE MEDIUM
2y 10m to grant Granted May 12, 2026
Patent 12620212
Locked-Model Multimodal Contrastive Tuning
3y 6m to grant Granted May 05, 2026
Patent 12611157
RADIATION IMAGE PROCESSING DEVICE, RADIATION IMAGE PROCESSING METHOD, AND RADIATION IMAGE PROCESSING PROGRAM
3y 6m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 4 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
50%
Grant Probability
99%
With Interview (+57.1%)
3y 1m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 8 resolved cases by this examiner. Grant probability derived from career allowance rate.

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