Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks on 9-22-2025 w.r.t. rejection of claims under 101 have been fully considered and are persuasive in light of new amendments to claims 30-34. The rejection has been withdrawn.
Applicant's arguments filed Remarks on 9-22-2025 w.r.t. DP rejection of claims have been fully considered but they are not persuasive. The e-TD was not filed to overcome the rejection. Therefore, the rejection is maintained.
Applicant's arguments filed Remarks on 9-22-2025 w.r.t. rejection of claims under 102 and 103 have been fully considered but they are not persuasive. The attorney does not provide clear argument why and how the prior art mentioned under 103 rejection differs from the current claimed concept but only provides overall generic statements. The attorney argues that “The post-hoc statistical analysis technique of Butts is not the same as identify the bit mismatch as representing a bus fault or an active attack against the protected node as recited by claim 1. Similarly, Butts fails to teach or reasonably suggest notify the protected node that a fault has occurred as recited by claim 1. Butts, instead, relies upon general notification of problems through web pages and health indicators. See Butts at paragraphs 0173-0174, 0078”. The examiner disagrees with the argument. The prior art Butts clearly recites: in [071] pre-existing controllers on the CAN bus are utilized to provide some amount of diagnostic information. This information is typically in the form of error flags and error counts. The standard John Deere Operating System (JDOS v4.05) keeps a count of the number of times a CAN controller goes error active and bus-off... To further enhance the diagnostic capability of each controller, programming code is provided that maintains a count of the error codes and a histogram of all CAN messages seen by each of the controllers on the CAN bus (i.e., protected node). This information is then sent to a central controller for analysis and [099] In the bus-off state, the CAN controller can no longer transmit CAN frames. Most CAN controllers require some sort of reset logic to get a controller out of the bus-off state. The controllers will always attempt to reset the CAN controllers and get the unit back into error passive state. Hence, the claim rejections under 102 and 103 are maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, 6, 7, 9, 25-34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-13, 15-21, 23-45 of U.S. Patent No. 11863569. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application is/are similar in scope, form and content.
Instant App. 18526456
Patent#: 11863569
1. An apparatus comprising: processor circuitry coupled to a memory, the processor circuitry to: monitor transmission of messages from a protected node to a bus; detect a bit mismatch relating to the transmitted message on the bus; identify the bit mismatch as representing a bus fault or an active attack against the protected node; and notify the protected node that a fault has occurred.
4. The apparatus of claim 1, wherein the processor circuitry is further to: upon detecting the fault, suspend the transmission of messages; use a bypass channel to transmit altered messages channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
6. (Currently Amended) The apparatus of claim 1, wherein the bit mismatch represents the bus fault; transmit the transmitted messages from the memory device to the bus at a later time when the bit mismatch represents the active attack; delete or transmit the stored transmitted messages depending on whether the bit mismatch represents the bus fault or the active attack, respectively.
9. (Currently Amended) The apparatus of claim 1, wherein the processor a protected node to a bus; detecting a bit mismatch relating to the transmitted message on the bus; identifying the bit mismatch as representing a bus fault or an active attack against the protected node; and notifying the protected node that a fault has occurred.26. (New) The method of claim 25, further comprising: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.27. (New) The method of claim 25, further comprising: storing the transmitted messages in a memory device; monitoring transmission of sensed messages from the bus to the protected node; comparing the transmitted messages to the sensed messages to identify a multi-bit mismatch between the transmitted messages and the sensed messages; and identifying the multi-bit mismatch as the bus fault or the active attack.28. (New) The method of claim 25, further comprising: storing the transmitted messages at a memory device, wherein the memory device is configured to function as a first-in first-out queue; deleting the transmitted messages from the memory device when the bit mismatch represents the bus fault; transmitting the transmitted messages from the memory device to the bus at a later time when the bit mismatch represents the active attack; deleting or transmitting the stored transmitted messages depending on whether the bit mismatch represents the bus fault or the active attack, respectively.29. (New) The method of claim 25, further comprising: monitoring bus activity on the bus for signaling that represents six bits; identifying the bit mismatch as the bus fault when the six bits are placed in a recessive state; identifying the bit mismatch as the active attack when the six bits are not placed in the recessive state; identifying a message from an attacker node participating in the active attack; classifying the identified message from the attacker node as a corrupt message; and broadcasting the corrupt message on the bus.30. (New) At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising: monitoring transmission of messages from a protected node to a bus; detecting a bit mismatch relating to the transmitted message on the bus; identifying the bit mismatch as representing a bus fault or an active attack against the protected node; and notifying the protected node that a fault has occurred.31. (New) The computer-readable medium of claim 30, wherein the operations further comprise: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.32. (New) The computer-readable medium of claim 30, wherein the operations further comprise: storing the transmitted messages in a memory device; monitoring transmission of sensed messages from the bus to the protected node; comparing the transmitted messages to the sensed messages to identify a multi-bit mismatch between the transmitted messages and the sensed messages; and identifying the multi-bit mismatch as the bus fault or the active attack.33. (New) The computer-readable medium of claim 30, wherein the operations further comprise: storing the transmitted messages at a memory device, wherein the memory device is configured to function as a first-in first-out queue; deleting the transmitted messages from the memory device when the bit mismatch represents the bus fault; transmitting the transmitted messages from the memory device to the bus at a later time when the bit mismatch represents the active attack; deleting or transmitting the stored transmitted messages depending on whether the bit mismatch represents the bus fault or the active attack, respectively.34. (New) The computer-readable medium of claim 30, wherein the operations further comprise: monitoring bus activity on the bus for signaling that represents six bits; identifying the bit mismatch as the bus fault when the six bits are placed in a recessive state; identifying the bit mismatch as the active attack when the six bits are not placed in the recessive state; identifying a message from an attacker node participating in the active attack; classifying the identified message from the attacker node as a corrupt message; and broadcasting the corrupt message on the bus.
1. (Currently Amended) An electronic device for bus-off attack detection and prevention, the electronic device comprising:
bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry disposed between the protected node and the bus, and to flipped from the transmitted message such that further transmission from the protected node is suspended.
2. (Original) The electronic device of claim 1, wherein the bus-off prevention circuitry is incorporated into the protected node.
3. (Original) The electronic device of claim 1, wherein the bus-off prevention circuitry is separately packaged from the protected node.
5. (Original) The electronic device of claim 1, wherein to suspend further transmission from the protected node, the bus-off prevention circuitry is to: use the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
6. (Original) The electronic device of claim 1, wherein to determine whether the bit mismatch represents the bus fault or the active attack against the protected node, the bus-off prevention circuitry is to: store the transmitted message in a memory device; receive a sensed message from the bus;
compare the transmitted message to the sensed message to identify a multi-bit mismatch between the transmitted message and the sensed message; and identify the multi-bit mismatch as the bus fault or active attack.
7. (Currently Amended) The electronic device of claim 1, further comprising a memory device, wherein the bus-off prevention circuitry is to: store the transmitted message in the memory device;
delete the transmitted message from the memory device when the bit mismatch represents the bus fault; and transmit the transmitted message from the memory device to the bus later at a time when the bit mismatch represents the active attack.
8. (Original) The electronic device of claim 7, wherein the memory device is configured as a first-in first-out queue and wherein the bus-off prevention circuitry is to: store multiple transmitted messages in the memory device; and delete or transmit the stored multiple transmitted messages depending on whether the bit mismatch represents the bus fault or active attack, respectively.
9. (Original) The electronic device of claim 1, wherein to determine whether the bit mismatch represents the bus fault or the active attack against the protected node, the bus-off prevention circuitry is to: monitor bus activity on the bus for signaling that represents six bits; identify the bit mismatch as the bus fault when the six bits all represent a recessive state; and identify the bit mismatch as the active attack when the six bits are not all in the recessive state.
10. (Original) The electronic device of claim 1, wherein the bus-off prevention circuitry is to: identify a message from an attacker node participating in the active attack; corrupt the message from the attacker node to produce a corrupted message; and broadcast the corrupted message on the bus.
11. (Currently Amended) A method for bus-off attack detection and prevention, the method performed by bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry disposed between the protected node and the bus, and to
detecting a transmitted message from the protected node to the bus; detecting a bit mismatch of the transmitted message on the bus; suspending further transmissions from the protected node while the bus is analyzed by using a bypass channel to transmit the transmitted message back to the protected node; determining whether the bit mismatch represents a bus fault or an active attack against the protected node; and signaling the protected node indicating whether a fault has occurred, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message such that the further transmission from the protected node is suspended.
12. (Original) The method of claim 11, wherein the bus-off prevention circuitry is incorporated into the protected node.
13. (Original) The method of claim 11, wherein the bus-off prevention circuitry is separately packaged from the protected node.
15. (Original) The method of claim 11, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
16. (Original) The method of claim 11, wherein determining whether the bit mismatch represents the bus fault or the active attack against the protected node comprises: storing the transmitted message in a memory device; receiving a sensed message from the bus; comparing the transmitted message to the sensed message to identify a multi-bit mismatch between the transmitted message and the sensed message; and identifying the multi-bit mismatch as the bus fault or active attack.
17. (Currently Amended) The method of claim 11, further comprising: storing the transmitted message in a memory device;
deleting the transmitted message from the memory device when the bit mismatch represents the bus fault; and transmitting the transmitted message
18. (Original) The method of claim 17, wherein the memory device is configured as a first-in first-out queue and wherein the method comprises: storing multiple transmitted messages in the memory device; and deleting or transmitting the stored multiple transmitted messages depending on whether the bit mismatch represents the bus fault or active attack, respectively.
19. (Original) The method of claim 11, wherein determining whether the bit mismatch represents the bus fault or the active attack against the protected node comprises: monitoring bus activity on the bus for signaling that represents six bits;
identifying the bit mismatch as the bus fault when the six bits all represent a recessive state; and identifying the bit mismatch as the active attack when the six bits are not all in the recessive state.
20. (Original) The method of claim 11, further comprising: identifying a message from an attacker node participating in the active attack; corrupting the message from the attacker node to produce a corrupted message; and broadcasting the corrupted message on the bus.
21. (Currently Amended) At least one non-transitory machine-readable medium including instructions for bus-off attack detection and prevention, the instructions when executed by bus-off prevention circuitry coupled to a protected node on a bus, wherein the bus-off prevention circuitry is disposed between the protected node and the bus, and is to protected node indicating whether a fault has occurred, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message such that the further transmission from the protected node is suspended.
23. (Original) The at least one machine-readable medium of claim 21, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
24. (Original) The at least one machine-readable medium of claim 21, further comprising: identifying a message from an attacker node participating in the active attack; corrupting the message from the attacker node to produce a corrupted message; and broadcasting the corrupted message on the bus.
25. (New) An electronic device for bus-off attack detection and prevention, the electronic device comprising: bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry disposed between the protected node and the bus, and to serve as a dedicated proxy for the protected node, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus;
detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed by using a bypass channel to transmit the transmitted message back to the protected node; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred, wherein the bus-off prevention circuitry uses the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy such that further transmission from the protected node is suspended.
26. (New) The electronic device of claim 25, wherein the bus-off prevention circuitry is incorporated into the protected node.
27. (New) The electronic device of claim 25, wherein the bus-off prevention circuitry is separately packaged from the protected node.
28. (New) The electronic device of claim 25, wherein to suspend further transmission from the protected node, the bus-off prevention circuitry is to: use the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message.
29. (New) The electronic device of claim 25, wherein to determine whether the bit mismatch represents the bus fault or the active attack against the protected node, the bus-off prevention circuitry is to: store the transmitted message in a memory device;
receive a sensed message from the bus; compare the transmitted message to the sensed message to identify a multi-bit mismatch between the transmitted message and the sensed message; and identify the multi-bit mismatch as the bus fault or active attack.
30. (New) The electronic device of claim 25, further comprising a memory device, wherein the bus-off prevention circuitry is to: store the transmitted message in the memory device; delete the transmitted message from the memory device when the bit mismatch represents the bus fault; and
transmit the transmitted message from the memory device to the bus later at a time when the bit mismatch represents the active attack.
31. (New) The electronic device of claim 30, wherein the memory device is configured as a first-in first-out queue and wherein the bus-off prevention circuitry is to: store multiple transmitted messages in the memory device; and delete or transmit the stored multiple transmitted messages depending on whether the bit mismatch represents the bus fault or active attack, respectively.
32. (New) The electronic device of claim 25, wherein to determine whether the bit mismatch represents the bus fault or the active attack against the protected node, the bus-off prevention circuitry is to: monitor bus activity on the bus for signaling that represents six bits; identify the bit mismatch as the bus fault when the six bits all represent a recessive state; and identify the bit mismatch as the active attack when the six bits are not all in the recessive state.
33. (New) The electronic device of claim 25, wherein the bus-off prevention circuitry is to: identify a message from an attacker node participating in the active attack; corrupt the message from the attacker node to produce a corrupted message; and broadcast the corrupted message on the bus.
34. (New) A method for bus-off attack detection and prevention, the method performed by bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry disposed between the protected node and the bus, and to serve as a dedicated proxy for the protected node, the method comprising: detecting a transmitted message from the protected node to the bus; detecting a bit mismatch of the transmitted message on the bus; suspending further transmissions from the protected node while the bus is analyzed by using a bypass channel to transmit the transmitted message back to the protected node; determining whether the bit mismatch represents a bus fault or an active attack against the protected node; and signaling the protected node indicating whether a fault has occurred, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy such that the further transmission from the protected node is suspended.
35. (New) The method of claim 34, wherein the bus-off prevention circuitry is incorporated into the protected node.
36. (New) The method of claim 34, wherein the bus-off prevention circuitry is separately packaged from the protected node.
37. (New) The method of claim 34, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message.
38. (New) The method of claim 34, wherein determining whether the bit mismatch represents the bus fault or the active attack against the protected node comprises: storing the transmitted message in a memory device; receiving a sensed message from the bus; comparing the transmitted message to the sensed message to identify a multi-bit mismatch between the transmitted message and the sensed message; and identifying the multi-bit mismatch as the bus fault or active attack.
39. (New) The method of claim 34, further comprising: storing the transmitted message in a memory device; deleting the transmitted message from the memory device when the bit mismatch represents the bus fault; and transmitting the transmitted message from the memory device to the bus later at a time when the bit mismatch represents the active attack.
40. (New) The method of claim 39, wherein the memory device is configured as a first-in first-out queue and wherein the method comprises: storing multiple transmitted messages in the memory device; and deleting or transmitting the stored multiple transmitted messages depending on whether the bit mismatch represents the bus fault or active attack, respectively.
41. (New) The method of claim 34, wherein determining whether the bit mismatch represents the bus fault or the active attack against the protected node comprises: monitoring bus activity on the bus for signaling that represents six bits;
identifying the bit mismatch as the bus fault when the six bits all represent a recessive state; and identifying the bit mismatch as the active attack when the six bits are not all in the recessive state.
42. (New) The method of claim 34, further comprising: identifying a message from an attacker node participating in the active attack; corrupting the message from the attacker node to produce a corrupted message; and broadcasting the corrupted message on the bus.
43. (New) At least one non-transitory machine-readable medium including instructions for bus-off attack detection and prevention, the instructions when executed by bus-off prevention circuitry coupled to a protected node on a bus, wherein the bus-off prevention circuitry is disposed between the protected node and the bus, and is to serve as a dedicated proxy for the protected node, cause the bus-off prevention circuitry to perform operations comprising: detecting a transmitted message from the protected node to the bus; detecting a bit mismatch of the transmitted message on the bus; suspending further transmissions from the protected node while the bus is analyzed by using a bypass channel to transmit the transmitted message back to the protected node; determining whether the bit mismatch represents a bus fault or an active attack against the protected node; and signaling the protected node indicating whether a fault has occurred, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy such that the further transmission from the protected node is suspended.
44. (New) The at least one machine-readable medium of claim 43, wherein suspending further transmission from the protected node comprises using the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message.
45. (New) The at least one machine-readable medium of claim 43, further comprising: identifying a message from an attacker node participating in the active attack; corrupting the message from the attacker node to produce a corrupted message; and broadcasting the corrupted message on the bus.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6, 25, 27, 30, 32 is/are rejected under 35 U.S.C. 102 (a)(1) / (2) as being unpatentable by Butts et al (US 20080186870), hereafter Butt.
Claim 1: Butt teaches an apparatus comprising: processor circuitry coupled to a memory, the processor circuitry to [082, Fig. 1, 18]: monitor transmission of messages from a protected node to a bus; ([05-6] monitors an in-vehicle communications network messages having a plurality of controllers coupled together over the network… data is read, analyzed and presented by at least one controller that is within or separate from the network being analyzed).
detect a bit mismatch relating to the transmitted message on the bus; ([096-98] CRC error occurs when the calculated CRC of the data that was received and the CRC within the frame do not match. This is typically caused by a corrupt bit in the frame).
identify the bit mismatch as representing a bus fault or an active attack against the protected node; ([076-78] when errors are received that are greater than a CAN frame's bit...bus-off, controller area network condition monitor program (CCMON) program isolates the problem to an individual controller by determining that the isolated individual controller having the communications problem, bus-off...).
and notify the protected node that a fault has occurred. ([081, 91] receiving CAN controller will generate one or more flags in response to detected errors. These flags are... bit errors, CRC errors and bus off status, [203] the CCMON notifies the user regarding deviation).
Claim 6: Butt teaches the apparatus of claim 1, wherein the processor circuitry is further to: store the transmitted messages in a memory device; monitor transmission of sensed messages from the bus to the protected node; compare the transmitted messages to the sensed messages to identify a multi-bit mismatch between the transmitted messages and the sensed messages; and identify the multi-bit mismatch as the bus fault or the active attack. ([091, 96-98, 99] The receiving CAN controller will generate one or more flags in response to detected errors. These flags are stuff errors, form errors, ACK errors, bit 1 errors, bit 0 errors, CRC errors, error warning status, and bus off status... If the transmit count goes above 255, the unit goes bus-off. In the bus-off state, the CAN controller can no longer transmit CAN frames. Most CAN controllers require some sort of reset logic to get a controller out of the bus-off state. [106] Periodically the TDR would measure the CAN bus when the CAN bus was idle... and after some amount of idle time on the CAN bus. This new measurement would be compared against the baseline measurement).
Claim 25: Butt teaches a method comprising: monitoring transmission of messages from a protected node to a bus; detecting a bit mismatch relating to the transmitted message on the bus; identifying the bit mismatch as representing a bus fault or an active attack against the protected node; and notifying the protected node that a fault has occurred. ([05-6] monitors an in-vehicle communications network messages having a plurality of controllers coupled together over the network… data is read, analyzed and presented by at least one controller that is within or separate from the network being analyzed; [096-98] CRC error occurs when the calculated CRC of the data that was received and the CRC within the frame do not match. This is typically caused by a corrupt bit in the frame; [076-78] when errors are received that are greater than a CAN frame's bit...bus-off, controller area network condition monitor program (CCMON) program isolates the problem to an individual controller by determining that the isolated individual controller having the communications problem, bus-off...; [081, 91] receiving CAN controller will generate one or more flags in response to detected errors. These flags are... bit errors, CRC errors and bus off status, [203] the CCMON notifies the user regarding deviation).
Claim 27: Butt teaches the method of claim 25, further comprising: storing the transmitted messages in a memory device; monitoring transmission of sensed messages from the bus to the protected node; comparing the transmitted messages to the sensed messages to identify a multi-bit mismatch between the transmitted messages and the sensed messages; and identifying the multi-bit mismatch as the bus fault or the active attack. ([091, 96-98, 99] The receiving CAN controller will generate one or more flags in response to detected errors. These flags are stuff errors, form errors, ACK errors, bit 1 errors, bit 0 errors, CRC errors, error warning status, and bus off status... If the transmit count goes above 255, the unit goes bus-off. In the bus-off state, the CAN controller can no longer transmit CAN frames. Most CAN controllers require some sort of reset logic to get a controller out of the bus-off state. [106] Periodically the TDR would measure the CAN bus when the CAN bus was idle... and after some amount of idle time on the CAN bus. This new measurement would be compared against the baseline measurement).
Claim 30: Butt teaches at least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising [082, Fig. 1, 18]: monitoring transmission of messages from a protected node to a bus; detecting a bit mismatch relating to the transmitted message on the bus; identifying the bit mismatch as representing a bus fault or an active attack against the protected node; and notifying the protected node that a fault has occurred. ([05-6] monitors an in-vehicle communications network messages having a plurality of controllers coupled together over the network… data is read, analyzed and presented by at least one controller that is within or separate from the network being analyzed; [096-98] CRC error occurs when the calculated CRC of the data that was received and the CRC within the frame do not match. This is typically caused by a corrupt bit in the frame; [076-78] when errors are received that are greater than a CAN frame's bit...bus-off, controller area network condition monitor program (CCMON) program isolates the problem to an individual controller by determining that the isolated individual controller having the communications problem, bus-off...; [081, 91] receiving CAN controller will generate one or more flags in response to detected errors. These flags are... bit errors, CRC errors and bus off status, [203] the CCMON notifies the user regarding deviation).
Claim 32: Butt teaches the non-transitory computer-readable medium of claim 30, wherein the operations further comprise: storing the transmitted messages in a memory device; monitoring transmission of sensed messages from the bus to the protected node; comparing the transmitted messages to the sensed messages to identify a multi-bit mismatch between the transmitted messages and the sensed messages; and identifying the multi-bit mismatch as the bus fault or the active attack. ([091, 96-98, 99] The receiving CAN controller will generate one or more flags in response to detected errors. These flags are stuff errors, form errors, ACK errors, bit 1 errors, bit 0 errors, CRC errors, error warning status, and bus off status... If the transmit count goes above 255, the unit goes bus-off. In the bus-off state, the CAN controller can no longer transmit CAN frames. Most CAN controllers require some sort of reset logic to get a controller out of the bus-off state. [106] Periodically the TDR would measure the CAN bus when the CAN bus was idle... and after some amount of idle time on the CAN bus. This new measurement would be compared against the baseline measurement).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 26, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Butt as applied to claims above, and further in view of Likovich et al (US 20060182187), hereafter Liko.
Claim 4: Butt teaches the apparatus of claim 1, but is silent on wherein the processor circuitry is further to: upon detecting the fault, suspend the transmission of messages; use a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and use the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
But analogous art Liko teaches wherein the processor circuitry is further to: upon detecting the fault, suspend the transmission of messages; use a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and use the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy. ([013, 33] If any self-test failures (Fig. 3) are detected, the system clocks are stopped, receiver self-heal control register generates the receiver self-heal control signals that select the 2-way MUXes after the receivers in a reverse order to re-align the data from the spare data path, [051] the driver selects, with 2-way MUXes, the normal path for all bits below failed bit N and logic one states for all bits N+1, N+2, . . . M that select, with 2-way MUXes, the shifted path (i.e., bypass channel) for all bits above bit N to the spare bit M).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Butt to include the idea of using bypass channel after finding fault as taught by Liko so that the self-heal control register generates the self-heal control signals which reconfigure the bus to remove the failed bit path N and substitute spare bit M ([0057]).
Claim 26: Butt teaches the method of claim 25, but is silent on further comprising: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
But analogous art Liko teaches further comprising: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy. ([013, 33] If any self-test failures (Fig. 3) are detected, the system clocks are stopped, receiver self-heal control register generates the receiver self-heal control signals that select the 2-way MUXes after the receivers in a reverse order to re-align the data from the spare data path, [051] the driver selects, with 2-way MUXes, the normal path for all bits below failed bit N and logic one states for all bits N+1, N+2, . . . M that select, with 2-way MUXes, the shifted path (i.e., bypass channel) for all bits above bit N to the spare bit M).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Butt to include the idea of using bypass channel after finding fault as taught by Liko so that the self-heal control register generates the self-heal control signals which reconfigure the bus to remove the failed bit path N and substitute spare bit M ([0057]).
Claim 31: Butt teaches the non-transitory computer-readable medium of claim 30, but is silent on wherein the operations further comprise: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy.
But analogous art Liko teaches wherein the operations further comprise: upon detecting the fault, suspending the transmission of messages; using a bypass channel to transmit altered messages back to the protected node, wherein an altered message includes a bit flipped from a transmitted message; and using the bypass channel to transmit a high-priority message back to the protected node, the high-priority message indicating that the bus is busy. ([013, 33] If any self-test failures (Fig. 3) are detected, the system clocks are stopped, receiver self-heal control register generates the receiver self-heal control signals that select the 2-way MUXes after the receivers in a reverse order to re-align the data from the spare data path, [051] the driver selects, with 2-way MUXes, the normal path for all bits below failed bit N and logic one states for all bits N+1, N+2, . . . M that select, with 2-way MUXes, the shifted path (i.e., bypass channel) for all bits above bit N to the spare bit M).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Butt to include the idea of using bypass channel after finding fault as taught by Liko so that the self-heal control register generates the self-heal control signals which reconfigure the bus to remove the failed bit path N and substitute spare bit M ([0057]).
Allowable Subject Matter
Claims 7, 9, 28, 29, 33, 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BADRINARAYANAN /Primary Examiner, Art Unit 2494.
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