DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 8-15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Number 11,627,004 to Andrews et al. (“Andrews”), US Patent Number 2016/0370835 to Erickson et al. (“Erickson”), and US Patent Application Publication Number 2011/0026525 to He (“He”).
In reference to Claim 1, Andrews discloses a power over Ethernet (PoE) to USB-C multiport switch (See Figure 8), comprising: a PoE interface to receive and transmit PoE signals containing PoE power and Ethernet data (See Figure 8 Number 225, Column 4 Lines 59-66, and Column 7 Lines 9-12 and 20-22); a USB-C port to receive and transmit USB-C signals containing USB-C power and USB-C data (See Figure 8 Numbers 215, 220, 230, 240, 250, 260, and 270, together, and Column 4 Lines 4-6 and 26-32); and wherein each USB-C port incorporates an Ethernet to USB-C data converter (See Figure 8 Number 260 and Column 4 Lines 9-20) and has a USB-C power delivery (PD) controller (See Figure 8 Numbers 230 and 240) to control a power converter (See Figure 8 Number 270), said Ethernet to USB-C data converter being interposed (See Figure 8) between said PoE interface and a USB interface (See Figure 8 Number 250) of said USB-C port to transpose said Ethernet data from said PoE interface to said USB-C port and vice versa by controlling data transfer speed between said PoE interface and said USB-C interface and processing incoming Ethernet data signals into USB-C data formats and vice versa (See Column 4 Lines 3-25 [Ethernet data transfer speed may be either 100Mbps or 1000Mbps and USB 2.0/3.0 using a USB-C interface data transfer speed may be from 480Mbps to 5 Gbps, so a control of the speed must be made in order to transpose the data]), said power converter being coupled between said PoE interface and said USB-C port to step down PoE voltage to fit USB-C voltage (See Column 5 Lines 15-19), and said USB-C power delivery (PD) controller being connected between said power converter and said USB-C port to manage conversion of PoE power signal from a PoE source into a power charging signal for said USB-C port (See Figure 8 and Column 4 Line 26 – Column 5 Line 7 and Column 5 Lines 25-27). However, Andrews does not explicitly disclose a plurality of USB-C ports to receive and transmit USB-C signals containing USB-C power and USB-C data. Erickson discloses a power over Ethernet (PoE) to USB-C multiport switch (See Figure 5 Number 502), comprising: a PoE interface to receive and transmit PoE signals containing PoE power and Ethernet data (See Figure 5 Number 508 and Paragraphs 12 and 60); a multiport Ethernet interface coupled between the PoE interface and said plurality of USB-C ports, configured to receive said Ethernet data from said PoE interface and then distribute to said plurality of USB-C ports and vice-versa (See Figure 5 and Paragraphs 12 and 60); and a plurality of USB-C ports to receive and transmit USB-C signals containing USB-C power and USB-C data (See Figure 5 Numbers 506a and 510a, together, and 506b and 510b, together, and Paragraphs 12 and 60); and wherein each USB-C port of said plurality of USB-C ports incorporates an Ethernet to USB-C data converter (See Figure 5 Numbers 506a and 506b and Paragraphs 12 and 60) and has a USB-C power controller to control a power converter (See Figure 5 Numbers 506a and 506b and Paragraphs 12 and 60), said Ethernet to USB-C data converter being interposed (See Figure 5) between said multiport Ethernet interface and a USB interface (See Figure 5 Numbers 510a or 510b) of said USB-C port to transpose said Ethernet data from said multiport Ethernet interface to said USB-C port and vice versa by controlling data transfer speed between said PoE interface and said USB-C interface and processing incoming Ethernet data signals into USB-C data formats and vice versa (See Figure 5 and Paragraphs 12 and 60 [Ethernet data transfer speed may be either 100Mbps or 1000Mbps and USB 2.0/3.0 using a USB-C interface data transfer speed may be from 480Mbps to 5 Gbps, so a control of the speed must be made in order to transpose the data]), said power converter being coupled between said PoE interface and said USB-C port to step down PoE voltage to fit USB-C voltage (See Figure 5 and Paragraphs 40-41), and said USB-C power controller being connected between said power converter and said USB-C port to manage conversion of PoE power signal from a PoE source into a power charging signal for said USB-C port (See Paragraphs 40-45 and 60-62). However, Andrews and Erickson in combination are silent as to how the single Ethernet data input is distributed to multiple outputs, and do not explicitly disclose a multiport Ethernet switch coupled between said PoE interface and said plurality of USB-C ports, configured to receive said Ethernet data from said PoE interface and then distribute to said multiple USB-C ports and vice versa. He discloses a multiport Ethernet switch coupled between a single upstream PoE interface and a plurality of downstream Ethernet interfaces, configured to receive Ethernet data from said upstream interface and then distribute to said multiple downstream interfaces and vice versa (See Figure 1 and Paragraphs 3-8).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Andrews using the PoE power and data input distributed to multiple USB-C ports of Erickson, and using the Ethernet switch of He, resulting in the invention of Claim 1, in order to yield the predictable result of providing capability for changing multiple devices from the same PoE power source (See Paragraph 61 of Erickson); and because Andrews and Erickson in combination are silent as to how the single Ethernet data input is distributed to multiple outputs, and the simple substitution of the Ethernet switch of He to distribute the single Ethernet data input to multiple outputs would have yielded the predictable result of allowing all of the connected devices to communicate with each other while very effectively avoiding transmission collisions when multiple pairs of connected devices are sending and receiving data packets at the same time (See Paragraphs 4-5 of He).
In reference to Claim 3, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews in combination with Erickson further discloses a PoE splitter disposed between said PoE interface and said multiport Ethernet switch to act as a power and data splitter (See Column 4 Lines 63-66).
In reference to Claim 4, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews in combination with Erickson further discloses a PoE interface controller disposed between said PoE splitter and said plurality of USB-C ports, configured to negotiate with a PoE switch or a midspan to ensure a powering solution is IEEE 802.3 POE standards compliant, said IEEE 802.3 POE standards including IEEE 802.3af/at and IEEE 802.3 bt, and incorporate functions for a PoE system including detection, classification and inrush current limiting (See Column 3 Lines 47-54, Column 4 Lines 49-54, and Column 5 Line 51 – Column 6 Line 16 of Andrews and Paragraph 40 of Erickson [compliance with IEEE802.3 POE Standards, such as 802.3af, 802.3at, and 802.3bt necessarily must include detection, classification, and inrush current limiting, as these are required by these specifications]).
In reference to Claim 5, Andrews, Erickson, and He disclose the limitations as applied to Claim 4 above. Andrews further discloses that said PoE interface controller is a microcontroller unit (MCU) (See Column 4 Line 44 – Column 5 Line 7 and Column 7 Lines 42-60). Erickson further discloses that said PoE interface controller is a microcontroller unit (MCU) (See Paragraphs 38 and 114).
In reference to Claim 6, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews further discloses that said PoE interface is a RJ45 interface (See Figure 8 Number 225 and Column 4 Lines 59-61). Erickson further discloses that said PoE interface is a RJ45 interface (See Paragraph 60).
In reference to Claim 7, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews further discloses that said Ethernet to USB-C data converter is a data conversion chipset (See Column 7 Lines 42-60).
In reference to Claim 9, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews further discloses that said power converter includes flyback converter (See Column 4 Lines 28-40), half bridge converter, full bridge converter, buck converter, or boost converter (See Column 7 Lines 26-41).
In reference to Claim 10, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews further discloses that said USB-C PD controller is a USB-C PD microcontroller IC (See Column 5 Lines 8-27 and Column 7 Lines 42-60).
In reference to Claim 11, Andrews discloses a power over Ethernet (PoE) to USB-C multiport switch (See Figure 8), comprising: a PoE interface to receive and transmit PoE signals containing PoE power and Ethernet data (See Figure 8 Number 225, Column 4 Lines 59-66, and Column 7 Lines 9-12 and 20-22); a USB-C port to receive and transmit USB-C signals containing USB-C power and USB-C data (See Figure 8 Numbers 215, 220, 230, 240, 250, 260, and 270, together, and Column 4 Lines 4-6 and 26-32); a PoE splitter disposed between said PoE interface and said USB-C port configured to act as a power and data splitter (See Column 4 Lines 63-66); and wherein each USB-C port incorporates an Ethernet to USB-C data converter (See Figure 8 Number 260 and Column 4 Lines 9-20) and has a USB-C power delivery (PD) controller (See Figure 8 Numbers 230 and 240) to control a power converter (See Figure 8 Number 270), said Ethernet to USB-C data converter being interposed (See Figure 8) between said PoE interface and a USB interface (See Figure 8 Number 250) of said USB-C port to transpose said Ethernet data from said PoE interface to said USB-C port and vice versa by controlling data transfer speed between said PoE interface and said USB-C interface and processing incoming Ethernet data signals into USB-C data formats and vice versa (See Column 4 Lines 3-25 [Ethernet data transfer speed may be either 100Mbps or 1000Mbps and USB 2.0/3.0 using a USB-C interface data transfer speed may be from 480Mbps to 5 Gbps, so a control of the speed must be made in order to transpose the data]), said power converter being coupled between said PoE interface and said USB-C port to step down PoE voltage to fit USB-C voltage (See Column 5 Lines 15-19), and said USB-C power delivery (PD) controller being connected between said power converter and said USB-C port to manage conversion of PoE power signal from a PoE source into a power charging signal for said USB-C port (See Figure 8 and Column 4 Line 26 – Column 5 Line 7 and Column 5 Lines 25-27), and wherein said power converter converts incoming PoE voltage to match USB-C voltage (See Column 5 Lines 15-19) while an external USB-C powered device is sensed, via CC1 and CC2 terminals of said USB-C interface to request power transferring from a PoE power source (See Figure 1 Number 250 ‘CC1’ and ‘CC2’ and Column 4 Lines 4-6 and 26-32 [USB-PD and USB-C require an external powered device to request/negotiate voltage via the CC1 and CC2 pins]), said USB-C PD controller configured to activate a switching device disposed between said power converter and said USB-C interface to establish power path between said power converter and said external USB-C powered device (See Figure 8 switch coupled to Number 240 and ‘VBUS’ pin of Number 250). However, Andrews does not explicitly disclose a plurality of USB-C ports to receive and transmit USB-C signals containing USB-C power and USB-C data. Erickson discloses a power over Ethernet (PoE) to USB-C multiport switch (See Figure 5 Number 502), comprising: a PoE interface to receive and transmit PoE signals containing PoE power and Ethernet data (See Figure 5 Number 508 and Paragraphs 12 and 60); and a plurality of USB-C ports to receive and transmit USB-C signals containing USB-C power and USB-C data (See Figure 5 Numbers 506a and 510a, together, and 506b and 510b, together, and Paragraphs 12, 43, and 60); a multiport Ethernet interface coupled between the PoE interface and said plurality of USB-C ports, configured to receive said Ethernet data from said PoE interface and then distribute to said plurality of USB-C ports and vice-versa (See Figure 5 and Paragraphs 12 and 60); a PoE splitter disposed between said PoE interface and said multiport Ethernet interface, configured to act as a power and data splitter (See Figure 5 Number 508 and Paragraphs 11-12 and 60); and wherein each USB-C port of said plurality of USB-C ports incorporates an Ethernet to USB-C data converter (See Figure 5 Numbers 506a and 506b and Paragraphs 12 and 60) and has a USB-C power controller to control a power converter (See Figure 5 Numbers 506a and 506b and Paragraphs 12, 43, and 60), said Ethernet to USB-C data converter being interposed (See Figure 5) between said multiport Ethernet interface and said USB-C port to transpose said Ethernet data from said multiport Ethernet interface to a USB interface (See Figure 5 Numbers 510a or 510b) of said USB-C port and vice versa by determining communication protocol between said PoE interface and said USB-C interface and processing incoming Ethernet data signals into USB-C data formats and vice versa (See Figure 5 and Paragraphs 12 and 60), said power converter being coupled between said PoE interface and said USB-C port to step down PoE voltage to fit USB-C voltage (See Figure 5 and Paragraphs 40-41), and said USB-C power controller being connected between said power converter and said USB-C port to manage conversion of PoE power signal from a PoE source into a power charging signal for said USB-C port (See Paragraphs 40-45 and 60-62), and wherein said power converter converts incoming PoE voltage to match USB-C voltage (See Paragraphs 40-41) while an external USB-C powered device is sensed, via CC1 and CC2 terminals of said USB-C interface to request power transferring from a PoE power source (See Figure 5 Numbers 510a and 510b and Paragraphs 12, 43, and 60 [USB-C requires an external powered device to request/negotiate voltage via the CC1 and CC2 pins]). However, Andrews and Erickson in combination are silent as to how the single Ethernet data input is distributed to multiple outputs, and do not explicitly disclose a multiport Ethernet switch coupled between said PoE interface and said plurality of USB-C ports, configured to receive said Ethernet data from said PoE interface and then distribute to said multiple USB-C ports and vice versa. He discloses a multiport Ethernet switch coupled between a single upstream PoE interface and a plurality of downstream PoE interfaces, configured to receive Ethernet data from said upstream interface and then distribute to said multiple downstream interfaces and vice versa (See Figure 1 and Paragraphs 3-8).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Andrews using the PoE power and data input distributed to multiple USB-C ports of Erickson, and using the Ethernet switch of He, resulting in the invention of Claim 11, in order to yield the predictable result of providing capability for changing multiple devices from the same PoE power source (See Paragraph 61 of Erickson); and because Andrews and Erickson in combination are silent as to how the single Ethernet data input is distributed to multiple outputs, and the simple substitution of the Ethernet switch of He to distribute the single Ethernet data input to multiple outputs would have yielded the predictable result of allowing all of the connected devices to communicate with each other while very effectively avoiding transmission collisions when multiple pairs of connected devices are sending and receiving data packets at the same time (See Paragraphs 4-5 of He).
In reference to Claim 13, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews in combination with Erickson further discloses a PoE interface controller disposed between said PoE splitter and said plurality of USB-C ports, configured to negotiate with a PoE switch or a midspan to ensure a powering solution is IEEE 802.3 POE standards compliant, said IEEE 802.3 POE standards including IEEE 802.3af/at and IEEE 802.3 bt, and incorporate functions for a PoE system including detection, classification and inrush current limiting (See Column 3 Lines 47-54, Column 4 Lines 49-54, and Column 5 Line 51 – Column 6 Line 16 of Andrews and Paragraph 40 of Erickson [compliance with IEEE802.3 POE Standards, such as 802.3af, 802.3at, and 802.3bt necessarily must include detection, classification, and inrush current limiting, as these are required by these specifications]).
In reference to Claim 14, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said PoE interface controller is a microcontroller unit (MCU) (See Column 4 Line 44 – Column 5 Line 7 and Column 7 Lines 42-60). Erickson further discloses that said PoE interface controller is a microcontroller unit (MCU) (See Paragraphs 38 and 114).
In reference to Claim 15, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said PoE interface is a RJ45 interface (See Figure 8 Number 225 and Column 4 Lines 59-61). Erickson further discloses that said PoE interface is a RJ45 interface (See Paragraph 60).
In reference to Claim 17, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said Ethernet to USB-C data converter is a data conversion chipset (See Column 7 Lines 42-60).
In reference to Claim 18, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said power converter includes flyback converter (See Column 4 Lines 28-40), half bridge converter, full bridge converter, buck converter, or boost converter (See Column 7 Lines 26-41).
In reference to Claim 19, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said USB-C PD controller is a USB-C PD microcontroller IC (See Column 5 Lines 8-27 and Column 7 Lines 42-60).
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Andrews, Erickson, and He as applied to Claims 7 and 11 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2020/0304328 to Boemi et al. (“Boemi”) and admitted by Applicant to be prior art.
In reference to Claim 8, Andrews, Erickson, and He disclose the limitations as applied to Claim 1 above. Andrews further discloses that said Ethernet to USB-C data converter controls data transfer up to and including 100 Mb/s or 1000 Mb/s (1Gb/s), but is not so limited (See Column 4 Lines 18-20). However, Andrews, Erickson, and He do not explicitly disclose that said Ethernet to USB-C data converter controls data transfer up to and including 10 Gb/s. Official Notice is taken that the use of 10 Gb/s POE data transfers is well known in the art, as evidenced by Boemi (See Paragraphs 36, 63, and 167-168). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Andrews, Erickson, and He using the well-known 10Gb/s POE data transfer speed, resulting in the invention of Claim 8, because Andrews, Erickson, and He are not limited as to any particular POE protocol or data transfer speed, and the simple substitution of the well-known 10 Gb/s POE data transfer speed as the POE data transfer speed of Andrews, Erickson, and He would have yielded the predictable result of transferring the data over the POE connection at a high speed that is 10 times faster than 1000 Mb/s (See Paragraphs 167-168 of Boemi).
In reference to Claim 16, Andrews, Erickson, and He disclose the limitations as applied to Claim 11 above. Andrews further discloses that said Ethernet to USB-C data converter controls data transfer up to and including 100 Mb/s or 1000 Mb/s (1Gb/s), but is not so limited (See Column 4 Lines 18-20). However, Andrews, Erickson, and He do not explicitly disclose that said Ethernet to USB-C data converter controls data transfer up to and including 10 Gb/s. Official Notice is taken that the use of 10 Gb/s POE data transfers is well known in the art, as evidenced by Boemi (See Paragraphs 36, 63, and 167-168). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Andrews, Erickson, and He using the well-known 10Gb/s POE data transfer speed, resulting in the invention of Claim 8, because Andrews, Erickson, and He are not limited as to any particular POE protocol or data transfer speed, and the simple substitution of the well-known 10 Gb/s POE data transfer speed as the POE data transfer speed of Andrews, Erickson, and He would have yielded the predictable result of transferring the data over the POE connection at a high speed that is 10 times faster than 1000 Mb/s (See Paragraphs 167-168 of Boemi).
Response to Arguments
Applicant's arguments filed 11 December 2025 have been fully considered but they are not persuasive.
Applicant has separately argued that Andrews, Erickson, and He do not disclose placing a multiport Ethernet switch in the data path between the PoE interface and a plurality of USB-C ports (See Pages 10-11), and that none of the cited references disclose routing PoE data through a multiport Ethernet switch prior to USB conversion (See Page 11). In response, the Examiner notes that, as indicated above, the rejection is based on a combination of Andrews, Erickson, and He. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As indicated in the rejections, Andrews discloses a device for converting between a PoE interface and a single USB-C PD interface, and Erickson discloses a device for converting between a PoE interface and multiple USB-C interfaces. However, although Erickson discloses that there must be some sort of multiport Ethernet component to distribute the single PoE interface to outputs coupled to multiple USB-C interfaces (See Figure 5), Andrews and Erickson are silent as to exactly how this is accomplished. Thus, He was relied upon solely to disclose the use of a multiport Ethernet switch coupled between a single upstream Ethernet interface and a plurality of downstream Ethernet interfaces, configured to receive Ethernet data from said upstream interface and then distribute to said multiple downstream interfaces and vice versa (See Figure 1 and Paragraphs 3-8). The use of such a multiport switch device would be substituted in place of whatever means is used by Andrews and Erickson between Figure 5 Numbers 506a, 506b, and 508 of Erickson to split the single upstream Ethernet data of Andrews and Erickson (See Figure 5 Number 508 and Paragraph 12 of Erickson) into multiple downstream Ethernet data to be provided to the multiple conversion components of Andrews and Erickson (See Figure 5 Numbers 506a-506b and Paragraph 12 of Erickson) to perform such required data splitting/distribution would have been obvious to one of ordinary skill in the art, because the simple substitution of the Ethernet switch of He to distribute the single Ethernet data input to multiple outputs of Andrews and Erickson would have yielded the predictable result of allowing all of the connected devices to communicate with each other while very effectively avoiding transmission collisions when multiple pairs of connected devices are sending and receiving data packets at the same time (See Paragraphs 4-5 of He).
Applicant has argued that integrating an Ethernet switch into the signal path necessitates a complete re-architecture of the power domain, the printed circuit board (PCB) layout, and the thermal design, and thus appears to be arguing that such a combination would produce unexpected results (See Page 11). In response, the Examiner notes that Applicant has provided no evidence, via either affidavit or declaration, that the claimed invention produced unexpected results. “It is well settled that unexpected results must be established by factual evidence”. In re De Blauwe, 736 F.2d 699, 705, 222 USPQ 191, 196 (Fed. Cir. 1984). See also In re Lindner, 457 F.2d 506, 508, 173 USPQ 356, 358 (CCPA 1972); Ex parte George, 21 USPQ2d 1058 (Bd. Pat. App. & Inter. 1991). The evidence relied upon should establish "that the differences in results are in fact unexpected and unobvious and of both statistical and practical significance." Ex parte Gelles, 22 USPQ2d 1318, 1319 (Bd. Pat. App. & Inter. 1992). Arguments presented by the applicant cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965) and In re De Blauwe, 736 F.2d 699, 705, 222 USPQ 191, 196 (Fed. Cir. 1984). Examples of statements which are not evidence and which must be supported by an appropriate affidavit or declaration include statements regarding unexpected results, commercial success, solution of a long-felt need, inoperability of the prior art, invention before the date of the reference, and allegations that the author(s) of the prior art derived the disclosed subject matter from the inventor or at least one joint inventor. See MPEP §716.01(c)(I)-(II) and MPEP §716.02(b). Furthermore the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Notwithstanding the above, and contrary to Applicant’s bald assertions, one of ordinary skill would easily recognize that simply substituting a multiport PoE Ethernet switch in place of an element for distributing PoE data from a single upstream link to multiple downstream links is well within the ordinary skill level and would have yielded predictable results, as accounting for power distribution, physical layout, and thermal constraints are routinely done in, and are a necessary step in, circuit design. As the claims and the prior art reference combination only operate on the Ethernet data, any alleged re-architecture of any power domains is moot. Furthermore, none of the prior art references nor the claims are limited to implementation with a printed circuit board, and thus any alleged re-architecture of a PCB is moot.
Applicant’s arguments with respect to Claims 2-10 and 11-19 are substantially equivalent to and cumulative to those presented with respect to Claim 1, and incorporate the same reasoning (See Page 12). The Examiner’s response is therefore the same as provided above with respect to Claim 1.
Applicant has made multiple general and broad arguments regarding the combination of references in the rejections (See Page 12). In response, the Examiner notes that, contrary to Applicant’s allegations, all of the requirements of 35 USC §103 have been met, as indicated in both the above rejections as well as those of the prior Office Action. All of the claim limitations were considered and are disclosed or suggested by the prior art, and specific and articulated reasoning was provided regarding the motivation for combining each reference. Furthermore, any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175