DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over SALMON et al. (US 2022/0217845 A1).
Regarding claim 1, SALMON teaches,
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A semiconductor package (Fig. 17), comprising:
a solid-state drive (SSD) device comprising:
a printed circuit board (1611 including 1722a-b, 1721, para [0164]) comprising a memory region (region of 1611 on which 1612 and 1724 are disposed);
a plurality of……. packages (bare die 1612 as marked, para [0168] ) disposed on the memory region;
and at least one dummy package (comprising top 1724 as marked wherein 1724 maybe a “dummy die”, see para [0168]) disposed on the memory region,
wherein the at least one dummy package is electrically coupled with the printed circuit board (via micropumps 1728, para [0168])
and wherein the at least one dummy package comprises a first pad (micropump 1728 as marked, para [0168]) constituting a heat path through which heat of the printed circuit board is dissipated (path comprising 1722a, micropumps 1728, dummy die 1724, TIM 1615 and conductive sheet 1616), para [0172], would dissipate some heat from PCB 1611/1722a and hence a heat path).
But Salmon does not explicitly teach, bare die 1612 is a memory package.
But Salmon additionally teaches,
the bare die may include processor die and may further include memory die, communication-related die, power-related die, or any other die (para [0013]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form die 1612 as a memory die ,according to the teaching of Salmon, such that die 1612 is a memory die/package, in order to form a memory system, since it has been held that choosing from a finite number of identified, predictable solutions such as bare die as memory die as taught by Salmon above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 3, SALMON teaches the semiconductor packages of claim 1 and further teaches , wherein the at least one dummy package further comprises: a metal layer (interconnect 1722a, para [0168]) coupled with the first pad and constituting the heat path; and a polished layer (glass substrate 1721, para [0168] on the metal layer.
Regarding claim 4, SALMON teaches the semiconductor packages of claim 3 and further teaches , wherein the SSD further comprises: a first adhesive layer in contact with the plurality of memory packages (layer of TIM 1615 as marked in contact with the top memory package 1612 . TIM 1615 maybe a die attach film such as ESP7660-HK-DAF, para [0166]);
a second adhesive layer in contact with the polished layer of the at least one dummy package (layer of TIM 1615 as marked in contact with the dummy package comprising dummy die 1724. TIM 1615 maybe a die attach film such as ESP7660-HK-DAF, para [0166]) ;
and a package case (1616, para [0166]) attached to the first adhesive layer and the second adhesive layer.
Regarding claim 5, SALMON teaches the semiconductor packages of claim 4 and further teaches, wherein: at least one memory package of the plurality of memory packages (top memory package 1612) is mounted on a first surface of the printed circuit board (top surface of 1611), the at least one dummy package (top 1724) is mounted on the first surface of the printed circuit board (top surface of 1611) , and a first thickness of the first adhesive layer matches a second thickness of the second adhesive layer (Tim 1615 covering top 1612 and top 1724 respectively has a same thickness, FIG. 17).
Regarding claim 6, SALMON teaches the semiconductor packages of claim 1 and further teaches, wherein the at least one dummy package further comprises: a metal layer (conducive sheet 1616 maybe copper foil, para [0166]) coupled with the first pad (thermally coupled with the first pad via the heat path), wherein the metal layer comprises a heat sink structure (1616 functions as heat sink to dissipate heat from PCB 1611) , and wherein the metal layer constitutes the heat path (1616 is the part of the heat path as per claim 1 rejection above).
Regarding claim 7, SALMON teaches the semiconductor packages of claim 1 and further teaches , wherein: the at least one dummy package (top 1724) is mounted on the printed circuit board (1611) through a plurality of bumps (1728 as marked ), the at least one dummy package further comprises a plurality of pads (comprising the first pad and second pad as marked below) in contact ( in thermal contact) with the plurality of bumps , respectively, and the plurality of pads comprise the first pad and a second pad (as defined).
Regarding claim 14, SALMON teaches,
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A semiconductor package (FIG. 17 as annotated above), comprising:
a printed circuit board (1611 including 1722a-b, 1721, para [0164]) comprising a first surface (top surface) and a second surface (bottom surface) opposite to the first surface;
a dummy package (top 1724 as marked) mounted on the first surface;
and a ……package (bottom bare die 1612 as marked, para [0168]) aligned (vertically aligned) with the dummy package in a direction perpendicular to the first surface and the second surface and mounted on the second surface (bottom surface of 1611),
wherein the dummy package comprises:
a first pad (micropump 1728 as marked) electrically coupled with the printed circuit board;
and a metal layer (1722a) electrically coupled with the first pad.
But Salmon does not explicitly teach,
bare die 1612 is a memory package.
But Salmon additionally teaches,
the bare die may include processor die and may further include memory die, communication-related die, power-related die, or any other die (para [0013]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form die 1612 as a memory die/package according to the teaching of Salmon, in order to form a memory system, since it has been held that choosing from a finite number of identified, predictable solutions such as bare die as memory die as taught by Salmon above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 16, SALMON teaches the semiconductor packages of claim 14 but does not explicitly teach, wherein the memory package comprises a NAND flash memory device.
It is widely known in art that a memory device may be a NAND type or NOR type memory device.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form memory die 1612 as a NAND memory die according to the teaching of Salmon, in order to form a NAND flash memory, since it has been held that choosing from a finite number of identified, predictable solutions such as memory die as NAND memory die as widely known in art, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 17, SALMON teaches the semiconductor packages of claim 14 and further teaches , wherein the dummy package further comprises a polished layer (glass substrate 1721) disposed on the metal layer.
Regarding claim 18, SALMON teaches the semiconductor packages of claim 17 and further teaches, further comprising: a first adhesive layer (layer of 1615 over the bottom 1612) in contact with the memory package; a second adhesive layer (top 1615 in contact with dummy package 1724) in contact (in thermal contact) with the polished layer of the dummy package;
and a package case (including top and bottom 1616) attached to the first adhesive layer and the second adhesive layer.
Regarding claim 19, SALMON teaches the semiconductor packages of claim 14 and further teaches , wherein: the metal layer comprises a heat sink structure (1616 dissipates some heat from PCB 1722a via bump 1728, dummy die 1724 & TIM1615 and hence a heat sink ), and the metal layer is exposed to air (as seen)
Regarding claim 20, SALMON teaches the semiconductor packages of claim 14 and further teaches ,wherein: the dummy package (top 1724) is mounted on the printed circuit board (1611) through a plurality of bumps(1728 as marked), the dummy package further comprises a plurality of pads (comprising the first pad and second pad as marked above) in contact (in thermal contact) with the plurality of bumps, respectively, and the plurality of pads comprise the first pad and a second pad(as defined).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over SALMON et al. US and further in view of Jeon et al. (US 2015/0357275 A1)
Regarding claim 11, SALMON teaches the semiconductor packages of claim 1 and further teaches, wherein the printed circuit board further comprises: a wiring pattern (interconnect 1722a, para [0168]) electrically coupled with the first pad and constituting the heat path (as defined in claim 1 rejection above); and an insulating layer (filler material 1613 which may be Epoxy (EMC), para [0165])) surrounding the wiring pattern,
But SALMON does not explicitly teach,
wherein the wiring pattern is electrically separated from input/output signals of the plurality of memory packages.
Meanwhile, Jeon teaches,
PCB region 110 may include an input/output control signal generation unit providing I/O signals to semiconductor chip 1 to Chip (para [0049], Fig. 1).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to form an input/output control signal generation unit on the memory region, such that the wiring pattern 1722a is electrically separated from the input/output signals of the memory package 1612, according to teaching of jeon, in order to provide input/output control signal to the memory package 1612, as taught by Jeon.
Claims 12, 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over SALMON et al. and further in view of Frank et al. (US 20150351277 A1)
Regarding claim 12, SALMON teaches the semiconductor packages of claim 1 and further teaches, wherein the SSD further comprises: a …… package (1725, para [0168]) electrically coupled with the first pad (via 1729 and 1722a) and disposed on a region other than the memory region of the printed circuit board (considering the memory region excluding the PCB 1611 region where 1725 is disposed (i.e. region of 1611 on which the memory packages and dummy packages are disposed only), 1725 is disposed on a region other than the memory region of the PCB).
But SALMON dos not explicitly teach,
the package 1725 is a driving chip package.
Meanwhile, Frank teaches,
A printed circuit board (PCB) comprising memory, solid state storage, a storage controller configured to manage the memory ...(abstract)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify Salmon such that device 1725 is formed as a storage controller such that 1725 is a driving package (storage controller) to manage/control memory die 1612, according to teaching of Frank, in order to form a flash module, as taught by Frank (see abstract)
Regarding claim 25, SALMON teaches,
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A semiconductor package (Fig. 17), comprising:
a printed circuit board (1611 including 1722a-b, 1721) comprising a first surface (top surface) and a second surface (bottom surface) opposite to the first surface;
a dummy package (top 1724 maybe a “dummy die”, see para [0168]) mounted on the first surface;
a…. package (bottom bare die 1612) aligned (vertically aligned) with the dummy package in a direction perpendicular to the first surface and the second surface and mounted on the second surface ;
and a….package (1725) mounted on at least one of the first surface (top surface) and the second surface……,
wherein the …… package (1725) is electrically coupled with the printed circuit board (1611) through a bump (1728 as marked),
wherein the dummy package comprises a pad (1728 as marked) constituting a heat path(comprising 1722a , 1728 , 1724, 1615 and 1616) through which heat of the printed circuit board is dissipated,
but Salmon does not explicitly teach,
1612 is a memory package,
1725 is a driving package,
Wherein a driving circuit configured to drive a memory chip of the memory package is formed on the at least one of the first surface and the second surface,
wherein the memory package comprises a NAND flash memory device,
and wherein the driving circuit of the driving package comprises a storage controller configured to control the NAND flash memory device.
But Salmon additionally teaches,
the bare die may include processor die and may further include memory die, communication-related die, power-related die, or any other die (para [0013])
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form bare die 1612 as a memory die according to the teaching of Salmon, in order to form a memory system such that 1612 forms a memory package, since it has been held that choosing from a finite number of identified, predictable solutions such as bare die as memory die as taught by Salmon above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Salmon still does not explicitly teach,
1725 is a driving package,
Wherein a driving circuit configured to drive a memory chip of the memory package is formed on the at least one of the first surface and the second surface,
wherein the memory package comprises a NAND flash memory device,
and wherein the driving circuit of the driving package comprises a storage controller configured to control the NAND flash memory device.
But it is widely known in art that a memory die may be a NAND or NOR memory die.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form the memory die 1612 as a NAND memory die, according to the teaching of Salmon, in order to form a NAND flash system, since it has been held that choosing from a finite number of identified, predictable solutions such as a NAND or NOR as a memory type, as widely known in art, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Salmon still does not explicitly teach,
1725 is a driving package,
wherein a driving circuit configured to drive a memory chip of the memory package is formed on the at least one of the first surface and the second surface,
and wherein the driving circuit of the driving package comprises a storage controller configured to control the NAND flash memory device.
Meanwhile, Frank teaches,
A printed circuit board (PCB) comprising memory, solid state storage, a storage controller configured to manage the memory ...(abstract)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify Salmon such that device 1725 is formed as a storage controller such that 1725 is a driving package (storage controller) to manage memory die 1612, a driving circuit (obvious circuit of the storage controller) configured to drive a memory chip of the memory package(obvious chip of memory die 1612) is formed on the at least one of the first surface (top surface) and the second surface, and wherein the driving circuit of the driving package comprises a storage controller configured to control the NAND flash memory die 1612, according to teaching of Frank, in order to form a flash module, as taught by Frank (see abstract)
Regarding claim 26, SALMON & Frank teach the semiconductor packages of claim 25 and further teaches, wherein the dummy package further comprises: a metal layer (interconnect 1722b, para [0168]) electrically coupled with the pad and constituting the heat path; and a polished layer (glass substrate 1721, para [0168] ) disposed on the metal layer.
Regarding claim 27, SALMON & Frank teach the semiconductor packages of claim 25 and further teaches, wherein the dummy package further comprises a metal layer (conducive sheet 1616 maybe copper foil, para [0166]) electrically coupled with the pad, wherein the metal layer comprises a heat sink structure(1616 functions as heat sink to dissipate heat from PCB 1611), and wherein the metal layer constitutes the heat path(1616 is the part of the heat path as per claim 25 rejection above).
Claims 10, 23 & 28 are rejected under 35 U.S.C. 103 as being unpatentable over SALMON et al. and further in view of YOON et al. (US 2014/0301125 A1)
Regarding claim 10, SALMON teaches the semiconductor packages of claim 1 and further teaches , wherein the printed circuit board further comprises: a wiring pattern (interconnect 1722a, para [0168]) electrically coupled with the first pad and constituting the heat path (as defined in claim 1 rejection above); and an insulating layer (filler material 1613 which may be Epoxy (EMC), para [0165])) surrounding the wiring pattern but does not explicitly teach,
wherein the wiring pattern is configured to receive an applied ground voltage.
Meanwhile YOON teaches,
The printed circuit board is comprised of a plurality of layers electrically separated by a dielectric material, with the plurality of layers typically containing conductive regions such as signal lines, power planes and ground planes (para [0003]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to configure wiring pattern 1722a to receive ground voltage according to the teaching of YOON, in order to form a ground plane, as taught by YOON above, since it has been held that choosing from a finite number of identified, predictable solutions such as PCB including a ground plane, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 23, SALMON teaches the semiconductor packages of claim 14 and further teaches , wherein the printed circuit board further comprises: a wiring pattern (interconnect 1722a, para [0168]) electrically coupled with the first pad; and an insulating layer (filler material 1613 which may be Epoxy (EMC), para [0165])) surrounding the wiring pattern,
but does not explicitly teach,
wherein the wiring pattern is configured to receive an applied ground voltage
Meanwhile YOON teaches,
The printed circuit board is comprised of a plurality of layers electrically separated by a dielectric material, with the plurality of layers typically containing conductive regions such as signal lines, power planes and ground planes (para [0003]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to configure wiring pattern 1722a to receive ground voltage according to the teaching of YOON, in order to form a ground plane, as taught by YOON above, since it has been held that choosing from a finite number of identified, predictable solutions such as PCB including a ground plane, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 28, SALMON & Frank teach the semiconductor packages of claim 25 and further teaches, wherein: the printed circuit board further comprises a wiring pattern (interconnect 1722a, para [0168]) electrically coupled with the pad, wherein the wiring pattern constitutes the heat path(as defined in claim 25 rejection above);
But Salmon does not explicitly teach,
and wherein the wiring pattern is configured to receive an applied ground voltage.
Meanwhile YOON teaches,
The printed circuit board is comprised of a plurality of layers electrically separated by a dielectric material, with the plurality of layers typically containing conductive regions such as signal lines, power planes and ground planes (para [0003]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to configure wiring pattern 1722a to receive ground voltage according to the teaching of YOON, in order to form a ground plane, as taught by YOON above, since it has been held that choosing from a finite number of identified, predictable solutions such as PCB including a ground plane, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Conclusion
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813