DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 5/5/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 13-15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huo (US 2022/0308993) and Mohseni et al. (WO 2022/216506).
Regarding claim 1, Huo discloses a method, comprising: attaching, by a memory sub-system over a connection from a host interface of the memory sub-system to a host system, a memory device having a memory space configured in first memory of the memory sub-system [FIG. 1: memory sub-system attached via a host connection interface to the host system, memory device with memory space residing within the memory sub-system]; attaching, by the memory sub-system over the connection from the host interface of the memory sub-system to the host system, a storage device having a storage space configured in the first memory of the memory sub-system [¶0014, 0009: a host system coupled to a memory sub-system storing in a cache logical memory address-to-physical memory address (L2P) mapping entries on the host system (local memory of the host system), host system sends access requests to the memory sub-system to store data at the memory sub-system and to read data from the memory sub-system]; allocating, by the memory sub-system, an amount of second memory, faster than the first memory, to represent pages of the memory space in servicing memory requests in the memory space [¶0020: operations are performed by the memory sub-system while a garbage collection process is being performed on one or more units of memory (pages) associated with the select portion of the address mapping]; managing, by the memory sub-system, an address map configured to identify correlations between pages of the second memory and corresponding pages of the memory space represented by the pages of the second memory [FIG. 3: generate data request comprising select logical memory address and select physical memory address based on host-side address memory mapping entry, cause data request to be sent from host system to memory sub-system].
However, Huo does not explicitly disclose operating, by the memory sub-system, a first page of the second memory in response to a memory access request transmitted over the connection according to a cache coherent memory access protocol, the memory access request identifying a memory address in the memory space.
Mohseni et al. discloses operating, by the memory sub-system, a first page of the second memory in response to a memory access request transmitted over the connection according to a cache coherent memory access protocol, the memory access request identifying a memory address in the memory space [¶0170-0175: address space for memory, access counters that keep track of frequency access of GPUs to memory and ensure that memory pages are moved to physical memory of the processor that is accessing pages, wherein cache connected to CPUs include write back cache using a cache coherence protocol (MEI, MESI, MSI, etc.)]; wherein the connection is a computer express link (CXL) connection [¶0254: compute express link].
It would have been obvious to one of ordinary skill in the art to have operated, by the memory sub-system, a first page of the second memory in response to a memory access request transmitted over the connection according to a cache coherent memory access request protocol in order to improve efficiency for memory ranges shared between processors [¶0171).
Regarding claim 2, the combination of Huo and Mohseni et al. discloses operating, by the memory sub-system, the first memory in response to a storage access request transmitted over the connection according to a storage access protocol, the storage access request identifying a logical block address in the storage space [Huo, ¶0029: host system includes a processor chipset including one or more cores, one or more caches, a memory controller, and a storage protocol controller wherein the host system uses the memory sub-system to write data to the memory sub-system and read data from the memory sub-system].
wherein the amount of the second memory allocated is faster than the first memory [Mohseni et al., ¶0113, 0115]; and wherein the connection is a computer express link (CXL) connection [Mohseni, ¶0254: compute express link].
Regarding claim 3, Huo further discloses the method of claim 2, wherein the storage space coincides with the memory space [FIG. 1, 2: local memory, memory device].
Regarding claim 4, Huo further discloses the method of claim 3, wherein the address map includes data associating a first identification of the first page with a second identification of a second page of the memory space [¶0020: operations are performed by the memory sub-system while a garbage collection process is being performed on units of memory (pages) associated with select portion of the address mapping data].
Regarding claim 5, Huo further discloses the method of claim 4, wherein the identification of the second page is based on the logical block address in the storage space [¶0171: memory pages are moved to physical of a processor that is accessing pages].
Regarding claim 6, Huo further discloses the method of claim 5, further comprising: mapping, by a flash translation layer of the memory sub-system, the logical block address to one or more pages of memory cells in the memory sub-system [¶0041, 0052].
Regarding claim 13, the rationale in the rejection of claims 1-6 is herein incorporated.
Regarding claim 14, Mohseni et al. further discloses the memory sub-system of claim 13, wherein the controller is further configured to: allocate a namespace of the non-volatile storage capacity [¶0010 and 0038]; and map the memory space to the namespace [¶0010 and 0038],
Regarding claim 15, the rationale in the rejection of claims 1-6 is herein incorporated.
Regarding claim 17, the rationale in the rejection of claims 1-6 is herein incorporated.
Regarding claim 18, the rationale in the rejection of claims 1-6 is herein incorporated.
Regarding claim 19, Mosheni et al. further discloses the non-transitory computer storage medium of claim 18, wherein further comprising: manage caching of pages of the memory space in a volatile memory of the memory sub-system [¶0170-0175: address space for memory, access counters that keep track of frequency access of GPUs to memory and ensure that memory pages are moved to physical memory of the processor that is accessing pages, wherein cache connected to CPUs include write back cache using a cache coherence protocol (MEI, MESI, MSI, etc.)].
Claim(s) 7-12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Huo (US 2022/0308993) and Mohseni et al. (WO 2022/216506), and further in view of Subbarao et al. (2020/0356307).
Regarding claim 7, Huo further discloses the method of claim 6, but does not explicitly disclose wherein the first page of the second memory is configured to represent a memory cell page having memory cells configured to be programmed together to store data in one atomic programming operating.
Subbarao et al., however, discloses the first page of the second memory is configured to represent a memory cell page having memory cells configured to be programmed together to store data in one atomic programming operating [¶0074, 0076: when a memory cell in a page of memory cells is programmed in an atomic write operation, the atomic write operation programs the memory cells in the page].
It would have been obvious to one of ordinary skill in the art to have a first page of the second memory being configured to represent a memory cell page having memory cells configured to be programmed together to store data in one atomic programming operating in order to store data at the memory devices and retrieve data from the memory devices (¶0003).
Regarding claim 8, Subbarao et al. further discloses the method of claim 7, further comprising, in response to the memory access request identifying the memory address: determining that the second page of the memory space is not yet represented by any page in the second memory [¶0056, 0069, ]; allocating the first page of the second memory; retrieving page data from the memory cell page; and storing the page data into the first page of the second memory [FIG. 4, Claim 11, 20].
Regarding claim 9, Subbarao et al. further discloses the method of claim 7, further comprising, in response to the memory access request identifying the memory address to store first data: storing the first data into the first page of the second memory [FIG. 4]; and updating the address map to indicate that the first page has content to be stored into the second memory [FIG. 5].
Regarding claim 10, Subbarao et al. further discloses the method of claim 9, further comprising, in response to the memory access request identifying the memory address to store the first data: storing data identifying the memory cell page being no longer in use [FIG. 4, 5].
Regarding claim 11, Subbarao et al. further discloses the method of claim 10, further comprising, in response to a determination that the host system is not actively using the second page of the memory space: storing the content of the first page into the second memory [FIG. 4, 5]; and updating the address map to indicate that the content in the first page is same as in a corresponding page in the second memory [FIG. 4, 5].
Regarding claim 12, Subbarao et al. further discloses the method of claim 11, wherein the storing the content includes: allocating the memory cell page; and performing an atomic programming operating to store the content in the memory cell page [¶0074, 0076: when a memory cell in a page of memory cells is programmed in an atomic write operation, the atomic write operation programs the memory cells in the page].
Regarding claim 20, Huo and Mohseni discloses the non-transitory computer storage medium of claim 19; however they does not explicitly disclose wherein each page cached in the volatile memory of the memory sub-system has a size of a memory cell page allocated to host a portion of the memory space; and wherein memory cells in the memory cell page are configured to be programmed together in an atomic programming operation to store data.
Subbarao et al., however, discloses wherein each page cached in the volatile memory of the memory sub-system has a size of a memory cell page allocated to host a portion of the memory space; and wherein memory cells in the memory cell page are configured to be programmed together in an atomic programming operation to store data [¶0074, 0076: when a memory cell in a page of memory cells is programmed in an atomic write operation, the atomic write operation programs the memory cells in the page].
It would have been obvious to one of ordinary skill in the art to have wherein each page cached in the volatile memory of the memory sub-system has a size of a memory cell page allocated to host a portion of the memory space; and wherein memory cells in the memory cell page are configured to be programmed together in an atomic programming operation to store data in order to store data at the memory devices and retrieve data from the memory devices (¶0003).
2. ALLOWABLE SUBJECT MATTER
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 16 recites the limitation of “wherein the controller is configured to swap a content of the second page from the first memory into the first page in response to the host system accessing memory addresses in the second page according to the cache coherent memory access protocol and to save a content of the first page into the first memory in response to the host system not actively accessing the second page before the host system accessing a third page in the memory space to cause the controller to use the first page to represent the third page.”
However, the closest prior art of record (see above applied prior art) does not explicitly teach or render obvious the limitations above, particularly in combination with the other limitations within the claims. The dependent claims are allowable for at least the same reasons as its respective independent claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see page 1 of the remarks) and amendments with respect to claims 1 and 13 have been considered, and are not persuasive. Specifically, the applicant argues “the claims have been amended to the state of when the examiner had issued a notice of allowance on September 3rd, 2025”. After review of the current set of claims and the claims in the notice of allowance, there appears that multiple limitations are missing from the current set in some of the claims. Also, the Examiner notes the Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references; and Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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