DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is a response to an application filed 12/01/2023, in which claims 1-10 are pending and ready for examination.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The Examiner has considered the references listed on the Information Disclosure Statement submitted on 12/01/2023.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the claim recites the limitation “wherein the threshold value is calculated by adjusting, based on a ratio between the length of a predetermined judgment period and the length of restoration time corresponding to the occurred failure, a value of throughput before occurrence of a failure.” There has been no prior mention of “a length of a predetermined judgment period” and “a length of restoration time,” and it is not clear these refer to. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, these limitations are being broadly interpreted to mean any length of a predetermined judgment period and any length of restoration time.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Japanese Patent Publication No. JP5620680B2 to Koizumi et al., (hereinafter Koizumi. English translation of JP5620680B2 is included and cited in this office action).
Regarding claim 1, Koizumi discloses a method for controlling operation of a semiconductor manufacturing apparatus, which comprises one or plural processing modules which respectively comprise plural submodules (Control of a substrate processing apparatus comprising a plurality of processing units, see p1, Fig. 1, p9, Koizumi), comprising steps for:
judging whether a failure has occurred in at least one of the plural submodules (Failure occurrence in a unit prompts change in processing, meaning there is a judgment whether a failure has occurred, see p25, 39, Koizumi);
judging, in the case that a failure has occurred in at least one of the plural submodules, whether at least one submodule which is not in a failed state exists in a processing module to which the failed submodule belongs (Failure occurrence in a unit prompts change in processing to another unit that is usable, meaning there is a judgment whether there is a unit not in a failed state in the processing, see p18, p25, p8, 56, Koizumi)
obtaining, in the case that at least one submodule which is not in a failed state exists in the processing module to which the failed submodule belongs, throughput in a state that the one or plural processing modules are controlled to perform operation while the failed submodule is controlled to stop its operation (Change in processing to another unit is performed while maintaining a high production amount/target throughput when a failure occurs with the failed unit stopped, meaning a throughput is obtained during this circumstance, see p8, Clm 1, p13-p18, p25, 41, 39-40, Koizumi);
judging whether the throughput is larger than a predetermined threshold (A throughput target condition or higher is determined and verified, meaning a judgement is made on whether throughput is larger than an amount to meet a target threshold, see p40, p8, Clm 1, p12-p18, p119-120, 123, p25, 39-41, Koizumi);
and
continuing operation of the one or plural processing modules while controlling the failed submodule to stop its operation, in the case that the throughput is larger than the predetermined threshold (Change in processing to another unit is performed while maintaining a high production amount/target throughput when a failure occurs with the failed unit stopped, meaning processing operation is continued in the case a throughput is larger than an amount to meet a target threshold, see p8, Clm 1, p13-p18, p25, 41, 39-40, Koizumi).
Regarding claim 3, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses wherein the threshold value is calculated based on restoration time that is defined in advance with respect to each of failure modes (A throughput, which constitutes a target condition threshold, is determined and based on a recovery time (i.e. restoration time) in simulation, meaning defined in advanced, see p41, 40, p8, Clm 1, p13-p18, p119-120, p25, 39-41, Koizumi)
Regarding claim 4, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses wherein the threshold value is calculated by adjusting, based on a ratio between the length of a predetermined judgment period and the length of restoration time corresponding to the occurred failure, a value of throughput before occurrence of a failure (A throughput based on a ratio with lengths of times, see p123, p12, p40, p8, Clm 2, Clm 1, p12-p18, p119-120, 123, p25, 39-41, Koizumi).
Regarding claim 5, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses wherein the predetermined judgment period is a period relating to maintenance that is periodically performed with respect to the semiconductor manufacturing apparatus (A throughput uses predetermined scheduled times based on previous performed operations, see p12, p124, p123, clm 2, p40, p8, Clm 1, p13-p18, p119-120, 123, p25, 39-41, Koizumi).
Regarding claim 6, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses wherein the step for obtaining throughput in a state that the one or plural processing modules are controlled to perform operation while the failed submodule is controlled to stop its operation comprises steps for: creating a schedule for processing of plural objects by the semiconductor manufacturing apparatus, on the supposition that the one or plural processing modules are controlled to perform operation while the failed submodule is controlled to its stop operation (Schedule simulated considering interruption, see p12, p123, clm 2, p40, p8, Clm 1, p13-p18, p119-120, 123, p25, 39-41, Koizumi); and calculating the throughput based on the created schedule, wherein the throughput represents the number of the objects with respect to which processing applied thereto in the semiconductor manufacturing apparatus is to be completed within unit time (A target throughput is determined for a schedule in case of failure interruption, wherein throughput signifies an amount (number) of processing within a time, see p9, p12, p123, clm 2, p41, p8, Clm 1, p13-p18, p119-120, 123, p25, 39-41, Koizumi).
Regarding claim 8, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses further comprising a step for selecting, based on a predetermined condition, whether the step for continuing is to be performed (Change in processing to another unit is performed while maintaining process conditions and a high production amount/target throughput when a failure occurs with the failed unit stopped, meaning processing operation is continued in the case a throughput is larger than an amount to meet a target threshold, see p25, p8-9, Clm 1, p13-p18, p25, 41, 39-40, Koizumi).
Regarding claim 9, Koizumi discloses all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further discloses wherein the processing module is a plating module comprising plural plating tanks; and the submodules are the plating tanks (A substrate manufacturing with plating and plurality of plurality of plating tanks, see Fig. 1, 28, Koizumi ).
Claim 10 is rejected on the same grounds as claim 1, with controller (see p1, p9, 46, Koizumi).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Koizumi, in view of Kozumi .
Regarding claim 2, Koizumi teaches all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
While the embodiment of Koizumi teaches a semiconductor manufacturing for restoration from a failure that considers a threshold throughput in the form of a target throughput that should be maintained (A throughput target condition or higher is determined and verified, meaning a judgement is made on whether throughput is smaller or larger than an amount to meet a target threshold, see p40, p8, Clm 1, p12-p18, p119-120, 123, p25, 39-41, Koizumi), the embodiment of Koizumi does not explicitly teach a step for stopping operation of a whole semiconductor manufacturing apparatus for restoration from a failure, in a case that a throughput is smaller than a predetermined threshold.
However, Koizumi teaches, in what is background knowledge of the art, a step for stopping operation of a whole semiconductor manufacturing apparatus from a failure, in a case that a throughput is smaller than a predetermined threshold (A system that cannot continuously process requires halting, see p7, p40, p8, Clm 1, p12-p18, p119-120, 123, p25, 39-41, Koizumi).
It would have been obvious to a person of ordinary skill in the art before the filing date of the claimed invention to modify the semiconductor processing and control as described by Koizumi and incorporating stopping when below a throughput amount, as taught by Koizumi.
One of ordinary skill in the art would have been motivated to do this modification in order to better address a system failure that impacts the amount of continuous process capability so as to maintain a continuous throughput once an issue is resolved to meet a needed throughput criteria (see p7, p40, p8, Clm 1, p12-p18, p119-120, 123, p25, 39-41, Koizumi).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Koizumi, in view of US Patent Publication No. 2021/0124341 to Nakasato et al., (hereinafter Nakasato) .
Regarding claim 7, Koizumi teaches all the limitations of the base claim as outlined above, and are analyzed as previously discussed with regard to that claim.
Koizumi further teaches further comprising a step for an operation of one or plural processing modules is continued while a failed submodule is controlled to stop its operation (Processing is continued to another unit while failed unit stopped, see p8, Clm 1, p13-p18, p25, 41, 39-40, Koizumi).
Koizumi does not explicitly teach communicating an alarm that represents a state.
However, Nakasato from the same or similar field of substrate processing, teaches communicating an alarm that represents a state (An alarm notification communicated in relation to behavior taken after an abnormal state, see Fig. 6 S19-S20, 68-69, Nakasato).
It would have been obvious to a person of ordinary skill in the art before the filing date of the claimed invention to modify the semiconductor processing and control as described by Koizumi and incorporating an alarm, as taught by Nakasato.
One of ordinary skill in the art would have been motivated to do this modification in order to better maintain a system and operators informed of a state of the system that may require monitoring or attention (see Fig. 6 S19-S20, 68-69, Nakasato).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seo , US. Patent Publication No. 2022/0206467 teaches controlling of a substrate processing apparatus that includes a second controller providing control when a first controller stops operating.
Hongkham et al., US. Patent Publication No. 2008/0051929 teaches scheduling in a semiconductor processing apparatus.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO J SAAVEDRA whose telephone number is (571)270-5617. The examiner can normally be reached M-F: 9:30am-5:30pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Robert E Fennema can be reached at (571) 272-2748. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILIO J SAAVEDRA/Primary Patent Examiner, Art Unit 2117