DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 January 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended to recite that “at least a first portion of the first data is loaded into the memory for a compile operation of the system of chip”. This feature is not supported by the specification as originally filed. While the specification teaches that utilization data (i.e., the claimed “first data”; see also claim 2 which explicitly recites that the first data is utilization data) is loaded into memory, it fails to teach that the utilization data is loaded into memory for a compile operation. The specification teaches that the utilization data is generated by a compiler and is loaded into memory during application runtime.
[0027] In some aspects, the techniques described herein relate to a device, further including: a compiler to generate the utilization data of the power domain, and an application runtime to load the utilization data of the power domain into a memory of the device. In some aspects, the techniques described herein relate to a device, wherein the thermal data is obtained during a boot time of the device.
[0098] In one or more examples, the utilization data 455 is generated during a compile time associated with the SOC 400 (e.g., a compile time the SOC 400). In variations, the utilization data 455 is loaded into the memory 440 during a runtime associated with the SOC 400 (e.g., during a runtime of the SOC 400, during runtime of an application, runtime of an operating system, runtime of a firmware configuration, after a boot time of SOC 400, etc.).
[0103] In one or more implementations, the utilization data 455 of a given power domain is based on a capacitance associated with the power domain (e.g., in relation to the execution of one or more applications). Additionally, or alternatively, the utilization data 455 is based on an activity factor of a power domain (e.g., in relation to the execution of one or more applications). In some cases, the activity factor indicates an activity level of the power domain (e.g., based on execution of one or more applications). In some examples, a SLIP compiler (e.g., stored in memory 440 and/or executed by or in conjunction with the SLIP core 435 and/or an application runtime of the SLIP core 435) generates the utilization data 455 of the power domain. Additionally, or alternatively, an application runtime of the SOC 400 loads the utilization data 455 of the power domain into the memory 440. In some cases, the thermal data 460 is obtained during a boot time of the SLIP circuit 405 and stored in the configuration space 450.
[0104] In some examples, the SLIP circuit 405 may set P-states without actively monitoring thermal sensor data of the SOC 400 or without actively monitoring instructions in an execution pipeline of the SOC 400. The SLIP circuit 405 provides predictive power steering instead of the reactive power throttling of conventional systems. The SLIP circuit 405 provides predictive setting of idle states (e.g., power gating, clock gating) and active states for individual power domains of the SOC 400. Thus, the SLIP circuit 405 provides the ability to steer power to various areas of the SOC 400 where and when the power is most needed while remaining under thermal density limits of the SOC 400 (e.g., of each power domain of the SOC 400). In some cases, the SLIP compiler creates power domain utilization data (e.g., utilization data 455). In some cases, the SLIP compiler creates at least one iteration of the utilization data 455 for at least one time step (e.g., a next time step). The utilization data 455 may include information on what power domains of the SOC 400 would be utilized (e.g., in a given time step). In some cases, the utilization data 455 includes an activity factor for one or more power domains of the SOC 400 (e.g., for each power domain being utilized). In some examples, an application runtime loads the utilization data 455 onto the memory 440. In some cases, the application runtime includes hardware, firmware, and/or software (e.g., hardware configuration, firmware configuration, software configuration) that enables an application to run (e.g., in relation to the SOC 400, on the SOC 400).
As demonstrated by these citations, the specification consistently teaches that the claimed “compile operation” is used to generate the utilization data, and fails to associate a loading step with this operation. Furthermore, the specification consistently teaches that the loading step is performed during an application runtime and therefore, presumably, after the compile operation. Based on this reasoning, the specification fails to support the claim language added by amendment. Claims 13 and 18 have been amended to include the same language and are therefore rejected on the same basis as claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 has been amended to recite that “at least a first portion of the first data is loaded into the memory for a compile operation of the system of chip”. This language is indefinite because it is unclear whether it further limits the claim or is merely a statement of intended use, and therefore possibly non-limiting [MPEP 2103(I)(C): “Language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation. The following types of claim language may raise a question as to its limiting effect… statements of intended use or field of use…”]. The claims fail to explicitly recite that a compile operation is executed by the invention. It is therefore unclear how the new language further limits the claim when it is used in a function that is not explicitly part of the invention. Nor does the intended use of the first data by the compile operation place a functional or structural limitation on the invention in any self-evident or meaningful way. The new language is therefore indefinite. Claims 13 and 18 have been amended to include the same language and are therefore rejected on the same basis as claim 1.
Because the new claim language is indefinite and lacks support in the specification as originally filed, it will be treated as non-limiting for the purposes of prior art search and consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, U.S. Patent Application Publication No. 2013/0046999, in view of Guniguntala et al., U.S. Patent Application Publication No. 2019/0042406, in view of Patel et al., U.S. Patent Application Publication No. 2005/0114056.
Regarding claim 1, Jung discloses a method comprising:
obtaining a first data of a power domain of a system on chip and a second data of the power domain [Fig. 3, step 303, 304: identify operating parameters and measure counter values; para. 0024: “The SOC solution 200 includes… a power domain 210… a power domain 220… and a power domain 230… The different power domains use, for example, different supply voltages and are used to support different operating frequencies.”];
predicting an expected power for the power domain based on the first data and the second data [Fig. 3, step 306: predicting a future temperature; para. 0025: “The baselining is based on Applicant's recognition that increase in temperature leads to increase in leakage power.”]; and
applying to the power domain a power level that is selected based on the expected power, wherein applying the power level comprises setting a voltage level and a frequency level of the power domain [para. 0027: “The controlling the operation of the processor includes the power manager 201 dynamically scaling the operating voltage and/or the operating frequency of the processor. In particular, the power manager 201 may scale the operating voltage and/or the operating frequency based on the baseline values stored in the lookup tables 206, thereby enabling the processor to operate within a desired mode.”].
Jung discloses obtaining first and second data, and also teaches that the first data is utilization data [para. 0032: “In step 303, operating parameters… include processor utilization…”], and the second data is thermal data [para. 0032: “In step 304, counter values from each ring-oscillator temperature monitor associated with each of the processors 212, 214, 234 and the components 222, 232 are measured.], but does not specifically teach that the first data is loaded into a memory of the SoC, and the second data is loaded into a hardware register of a configuration space.
Guniguntala discloses a step of loading utilization data into memory [para. 0056: “…collect run-time performance information including, but not limited to, CPU usage, memory usage, and heap usage. The collected run-time performance information is stored and updated in the non-volatile memory 304, such as in the parameters memory 312.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Jung and Guniguntala by modifying Jung to load utilization data in memory, as taught by Guniguntala. Jung discloses a process that monitors operating parameters, including utilization, of a processor. Guniguntala discloses a process that also monitors processor utilization, and further teaches that the monitoring process can also store the processor utilization data into memory. It would therefore have been obvious to one of ordinary skill in the art to modifying Jung based on Guniguntala’s teaching that processor utilization data may be stored in memory as part of a monitoring process.
Patel discloses loading thermal data [para. 0032: “Once the two ring oscillator frequencies have been determined, various methods disclosed herein may be implemented to calculate the operating temperature and process speed of the chip.”] into a hardware register of a configuration space1 [para. 0030: “A first counter 106 may be used to count clock output 108. The chip may also include a second counter 110 that counts an independent clock output… In either case, processor 114 receives outputs from ring oscillator counter 106 and second counter 110, which comprise readable registers on the chip 116 that includes the dual ring oscillator configuration.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Jung and Patel by modifying Jung to load thermal data into at least one hardware register of a configuration space, as taught by Patel. Jung and Patel both disclose the use of ring oscillator based temperature monitors. Jung does not detail the structure of ring oscillator temperature monitors, but Patel teaches that ring oscillator temperature monitors include registers that act as counters. It would therefore have been obvious to one of ordinary skill in the art to modify Jung based on Patel’s teaching that ring oscillator temperature monitors employ registers that act as counters for clock signals.
Regarding claim 2, Jung teaches that:
the first data is utilization data [para. 0032: “In step 303, operating parameters… include processor utilization…”]and the second data is thermal data [para. 0032: “In step 304, counter values from each ring-oscillator temperature monitor associated with each of the processors 212, 214, 234 and the components 222, 232 are measured.], and
the thermal data comprises at least one of a spatial thermal limit of the power domain or a positional thermal limit of the power domain [para. 0025: “The ring-oscillator temperature monitors are placed near recognized hot spots of respective devices, such as processors 212, 214, 222 and 224.”].
Regarding claim 3, Jung teaches that the spatial thermal limit of the power domain is based on an area of the power domain [para. 0025: hot spots] and a power level of the component at a time when the expected power is calculated [para. 0030: “…as the temperature increases, a dynamic current associated with the processor (or a switching current associated with the switching component) decreases. This is because the counter value has a direct proportional relationship with the dynamic current and an inverse proportion relationship with the temperature.”].
Regarding claim 4, Jung teaches the positional thermal limit of the power domain is based on a location of the power domain on the system on chip [para. 0025: hot spots].
Regarding claim 5, Jung teaches that at least one of the spatial thermal limit or the positional thermal limit of the power domain is based on thermal modeling data obtained from a simulation of the power domain operating at one or more power levels [para. 0025: baseline counter values].
Regarding claim 6, Jung teaches that the expected power is calculated before a first time period, and the power level is applied during the first time period [Fig. 3, steps 307, 308, para. 0032: “future” is the claimed first time period, therefore the expected power determinations are predictions occurring before the first time period].
Regarding claims 7 and 8, Jung teaches that the operations are performed periodically and/or repeatedly [para. 0026; Fig. 3, steps 303-307 loop], and therefore teaches performing the same operations with an updated expected power, a second time period, an updated utilization data and/or an updated thermal data, and a second power level.
Regarding claim 11, Jung teaches generating the utilization data of the power domain [para. 0026: operating parameters are monitored, indicating they are generated by system operation].
Regarding claim 12, Jung teaches that the thermal data is obtained during a boot time of the SoC [para. 0026: “Upon booting up, the silicon performance manager 207…”].
Claims 13-20 are rejected on the same basis as claims 1-5.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jung, Guniguntala, and Patel as applied to claim 1, and further in view of Boaz Costa Leite et al., U.S. Patent Application Publication No. 2020/0118012 (BCL).
Regarding claim 10, Jung discloses the method of claim 1, but does not disclose the use of a machine learning model.
BCL discloses that prediction of the expected power is based on implementing a machine learning model that is trained on power utilization training data from at least one of a system of the power domain [para. 0022: “Using machine learning 110, a model may be trained to predict the temperature of an electronic device based on CPU usage, fan speed, and battery usage.”].
It would have been obvious to one of ordinary skill, before the effective filing date of the claimed invention, to combine the teachings of Jung and BCL by modifying Jung’s prediction to be based on implementing a machine learning model that is trained on power utilization training data from at least one of a system of the power domain. Jung and BCL are both directed to predicting future processor behavior related to power. Jung discloses a step of predicting temperature/power based on operating parameters, but does not specifically disclose how such prediction is carried out. BCL discloses a step of predicting power using a machine learning model that is trained on processor operating parameters. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of BCL to Jung based on BCL’s teaching that a machine learning model may be used to provide the prediction that Jung requires.
Allowable Subject Matter
Claim 9 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(a) and 112(b) as set forth in this Office action.
Conclusion
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
1 The counter is a register that updates its value with each clock cycle. Because a new value is written to the register, it loads the data within the broadest reasonable interpretation (BRI). The counter value represents a frequency of the clock, which is within the BRI of a configuration of the clock, thereby being a hardware register of a configuration space.