Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
The acronyms GB and GK in claims 7 and 8 must be spelled out for clarity.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 10-16, 18-19, and 21 are rejected under 35 U.S.C. 102(a1) as being anticipated by "Machine learning-based prefetch optimization for data center applications," Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, Portland, OR, USA, November 2009.
With respect to claims 1 and 15, A system, comprising: a processor to: receive machine learning training data including label scores based on measurements of device performance during execution of benchmark applications for different prefetcher engine configurations, and corresponding device hardware states [(Table 2: measuring hardware events) Framework and Methodology to automatically identify and select energy-efficient configurations in re-configurable systems based on applying machine learning over system-level events like hardware event counters and kernel statistics, i.e., reliance on different machine-learning techniques to produce a training dataset that achieves energy efficiency improvement) [See Parameter Space Exploration via Machine Learning, Create a training dataset for machine learning algorithms in Section 2.1 & EXPERIMENTAL RESULTS Section 4]; and train configuration specific machine learning regression models based on the received machine learning training data to provide corresponding configuration specific device performance predictions based on given device hardware states; and a memory to store data used by the processor ((Table 2: measuring hardware events) relying on different machine-learning techniques, logistic regression models or training data using hardware profiles and hardware events to achieve energy efficiency improvements by automatically adapting the system configuration for predicting and selecting configuration, i.e., analyze application knowledge or training data required for selecting predicted configuration and make a proposal) [See Data Collection (Section 3.4) Application of Machine Learning, (Section 5.2)].
With respect to claims 10 and 21, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests system, comprising: prefetcher engines to: predict next memory access addresses of a memory from which to load data to a cache during execution of a software application; and load the data from the predicted next memory access addresses to the cache during execution of the software application (data center applications constructing with hardware prefetcher configurations having processors, each processor core has one data cache unit (DCU) prefetcher and one instruction pointer-based (IP) prefetcher and also one data prefetch logic (DPL) prefetcher and one adjacent cache line (ACL) prefetcher, the prefetcher running application to bring data into cache earlier and reduce the cache miss penalty (Tunables: Hardware Prefetchers & Observables: Hardware Events & Data Collection, section 3.2 & 3.3)]; and a processor to: execute the software application; execute a machine learning agent to select from different prefetcher engine configurations to control the prefetcher engines ([(Table 2: measuring hardware events) machine learning algorithm to instantiate machine learning, including selecting the training dataset and problem formulation that predicts optimal prefetch configurations (Observables: Hardware Events & Data Collection, section 3.3 & 3.4]; and control the prefetcher engines according to the different prefetcher engine configurations selected by the machine learning agent during execution of the software application, wherein the machine learning agent is to: receive a device hardware state (Hardware Prefetcher to select energy-efficient configurations in re-configurable systems based on applying machine learning over system-level events like hardware event counters and kernel statistics) [See Application to Hardware Prefetcher featuring Parameter Space Exploration via Machine Learning, Create a training dataset for machine learning algorithms in Section 2.1 & 2.2 & EXPERIMENTAL RESULTS Section 4]; apply configuration specific machine learning regression models to provide corresponding configuration specific performance predictions based on the received device hardware state [using or relying on different machine-learning techniques, logistic regression models or training data using hardware profiles and hardware events to generate the prediction model (Machine Learning Algorithms, Section 2.2)]; and select one of the prefetcher configurations based on a best prediction of the corresponding configuration specific performance predictions [evaluate relationship between these observable models and performance, i.e. evaluate prefetcher performance over our training set to predict optimal prefetch configurations and selecting the best configuration (Tunables: Hardware Prefetcher & Data Collection, Section 3.2 & 3.3)].
With respect to claims 2, 12, and 16, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system, wherein the corresponding hardware states and the given device hardware states are at least partially indicated by counter values [application of machine learning to predict the best configuration using data from hardware performance counters (Introduction 2nd Column)].
With respect to claims 4 and 18, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system, wherein: the machine learning training data includes the label scores, the corresponding device hardware states, and corresponding previous prefetcher engine configurations; and the processor is to train the configuration specific machine learning regression models based on the received machine learning training data to provide the corresponding configuration specific device performance predictions based on the given device hardware states and given previous prefetcher engine configurations (build or create a training dataset for machine learning algorithms and use of regression modeling for trained neural networks predicting configuration, i.e. machine learning algorithms to construct prediction models where each algorithm being a set of observables and tunables to generate a prediction model and capture relationship given the input features and trained predictions (Framework and Methodology Sec. 2.1 (3) Create a training dataset for machine learning algorithms; (4 )Build the prediction models and (5.)Use the models for prediction) Machine Learning Algorithms Sec. 2.2)].
With respect to claims 5 and 19, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system, wherein each of the configuration specific machine learning regression models includes different sub-models for respective ones of the given previous prefetcher engine configurations so that for a given previous prefetcher engine configuration a respective one of the sub-models of each of the configuration specific machine learning regression models is selected to provide a prediction based on one of the given device hardware states and the given previous prefetcher engine configuration [collect observable data and monitor monitoring observable data during a period to predict the best tunable configuration and apply the collected observable data to the prediction model ((4 )Build the prediction models and (5.)Use the models for prediction) Machine Learning Algorithms Sec. 2.2)].
With respect to claim 11, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system wherein each of the prefetcher engines is to selectively provide different levels of aggressiveness, the different configurations of the prefetcher engines providing different aggressiveness configurations of the prefetcher engines [machine learning with indicator for each prefetcher performance each prefetcher may have different performance models with all prefetchers (Observables: Hardware Events Sec. 3.3); designing or tuning prefetchers for aggressive prefetching that produces superior performance for applications that produce pathological behavior for applications that have finely tuned memory behavior (Introduction Col. 2)].
With respect to claim 13, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system wherein the machine learning agent is to apply the configuration specific machine learning regression models to provide the corresponding configuration specific performance predictions based on the received device hardware state and a previous prefetcher engine configuration of the prefetcher engines (build or create a training dataset for machine learning algorithms and use of regression modeling for trained neural networks predicting configuration, i.e. machine learning algorithms to construct prediction models where each algorithm being a set of observables and tunables to generate a prediction model and capture relationship given the input features and trained predictions (Framework and Methodology Sec. 2.1 (3) Create a training dataset for machine learning algorithms; (4 )Build the prediction models and (5.)Use the models for prediction) Machine Learning Algorithms Sec. 2.2)].
With respect to claim 14, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system wherein each of the configuration specific machine learning regression models includes different sub-models for respective ones of the given previous prefetcher engine configurations; and the machine learning agent is to select and apply, for the previous prefetcher engine configuration, a respective one of the sub-models of each of the configuration specific machine learning regression models to provide a prediction based on the received device hardware state and the given previous prefetcher engine configuration [collect observable data and monitor monitoring observable data during a period to predict the best tunable configuration and apply the collected observable data to the prediction model ((4 )Build the prediction models and (5.)Use the models for prediction) Machine Learning Algorithms Sec. 2.2)].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 6, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over "Machine learning-based prefetch optimization for data center applications," (Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis) in view of Y. Chou, "Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications," (40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), Chicago, IL, USA, 2007).
With respect to claims 3 and 17, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system, machine learning with indicator for each prefetcher performance each prefetcher may have different performance models with all prefetchers, wherein a high cache miss rate may be a good indicator indicative of poor spatial locality of the application and where to reduce the cache miss penalty, some of the prefetchers may be turned off to alter aggressive prefetcher setting (Observables: Hardware Events Sec. 3.3). “Machine Learning-based Prefetch Optimization for Data Center Applications” fails to specifically teach wherein the processor is to compute each of the label scores based on any one or more of the following: executed instructions per cycle; memory transactions per cycle; power cost per memory transaction; average core frequency; average core power; power budget; and measured temperature.
However, "Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications," (40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)) teaches benchmark applications measuring the performance characterized by irregular control flow and complex data access patterns that render cost-related prefetching schemes determined by measuring overall cycles per instruction (CPI) using a cycle-accurate timing simulator (Performance Metrics Sec. 4.1), such as stream-based and stride-based prefetching, featuring collection of statistics such as cost-effective parameters stored in correlation table of main memory to exploit the concept of latency of its correlation table access, and an attempt to eliminate entire epochs instead of individual instruction and data misses (Abstract; Timely Access of Main Memory Predictor Tables, Sec. 3.2; Performance Metrics Sec. 4.1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the instant application to combine the Observables Hardware Events with the “Low-Cost Epoch-Based Correlation Prefetching” in order to reduce the number of cache misses as taught (Introduction).
With respect to claims 6 and 20, “Machine Learning-based Prefetch Optimization for Data Center Applications” suggests the system, machine learning with indicator for each prefetcher performance each prefetcher may have different performance models with all prefetchers, wherein a high cache miss rate may be a good indicator indicative of poor spatial locality of the application and where to reduce the cache miss penalty, some of the prefetchers may be turned off to alter aggressive prefetcher setting (Observables: Hardware Events Sec. 3.3). “Machine Learning-based Prefetch Optimization for Data Center Applications” fails to specifically teach wherein the processor is configured to train the configuration specific machine learning regression models using configuration specific cost functions based on data indicative of different scenarios while running the benchmark applications, the data of the different scenarios being weighted in the cost functions. However, Y. Chou, "Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications” teaches benchmark applications measuring the performance characterized by irregular control flow and complex data access patterns that render cost-related prefetching schemes determined by measuring overall cycles per instruction (CPI) using a cycle-accurate timing simulator (Performance Metrics Sec. 4.1), such as stream-based and stride-based prefetching, featuring collection of statistics such as cost-effective parameters stored in correlation table of main memory to exploit the concept of latency of its correlation table access, and an attempt to eliminate entire epochs instead of individual instruction and data misses (Abstract; Timely Access of Main Memory Predictor Tables, Sec. 3.2; Performance Metrics Sec. 4.1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the instant application to combine the Observables Hardware Events with the “Low-Cost Epoch-Based Correlation Prefetching” in order to reduce the number of cache misses as taught (Introduction).
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
B. Herzog, S. Reif, F. Hügel, W. Schröder-Preikschat and T. Hönig, "BEARS: Building Energy-Aware Reconfigurable Systems," 2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC), Fortaleza/CE, Brazil, 2022, pp. 1-8.
US 20230391374 A1 (CHEN et al) teaching apparatuses, systems, and techniques to generate trajectory predictions based on one or more neural networks.
US 20220318017 A1 (GARG et al) teaching techniques for a hardware processor to dynamically configure a component that improves a processor function with a configuration setting based on invariant statistics, the invariant statistics generated dependent of the performance metrics and configuration setting for the component using a machine learning model.
US 20220197856 A1 (KHASAWNEH et al) teaching configuration register to store configuration information for a hardware resource including a control circuit to configure the hardware resource based at least in part on the configuration information; a performance monitor to maintain performance information during execution of an application on the processor; and a controller coupled to the at least one configuration register to dynamically provide the configuration information to the at least one configuration register based at least in part on the performance information, and the control circuit is to adjust a performance tuning of the hardware resource according to the configuration information.
US 20220004897 A1 (JADON et al) teaching techniques, using an automatically trained machine learning system, to generate a prediction based on a request for the prediction: training each respective machine learning (ML) model in a plurality of ML models to generate a respective training-phase prediction in a plurality of training-phase predictions; automatically determining a selected ML model in the plurality of ML models based on evaluation metrics for the plurality of ML; and applying the selected ML model to generate the prediction based on data collected from a network that includes a plurality of network devices.
US 10402733 B1 (LI et al) teaching two or more prediction models trained using the obtained past workload data, a weight assigned to each of the two or more trained prediction models, the two or more weighted prediction models combined to form an ensemble prediction model configured to predict, in real-time, workload associated with future execution of the application by the computing system.
Contact Information
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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