DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Figueiredo et al., "A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency," IEEE Transactions on Circuits and Systems , Vol. 58, No. 7, July 2011 (henceforth referred to as “Figueiredo”) in view of Li (2020/0358414 A1). Regarding claim 1 , Figueiredo proposes in Fig. 1, a fully differential operational amplifier (inverter-based self-biased amplifier) comprising: Fig. 1 of Figueiredo reproduce d by the examiner for ease of reference. (a) a first stage (comprising CMOS transistor pairs M12a-M13a and M12b-M13b) including a first amplifier (CMOS amplifier stage 1 ) configured to amplify a difference signal between a first differential pair of input signals (Vin and Vip) and output a first differential pair of output signals (Von1 and Vop1) , and a first CMFB circuit (CMFB1) including a first CMFB component that receives the first differential pair of output signals (Von1 and Vop1) and a first reference signal (V CMO ) and generates a first control signal ( feedback control signal V CM1N and V CM1P ) to regulate the first common-mode voltage of the first amplifier ( M12a-M13a and M12b-M13b ) to a first reference voltage (corresponding to the first reference signal V CMO ) ; and (b) a second stage ( comprising CMOS transistor pairs M 2 2a-M 2 3a and M 2 2b-M 2 3b ) connected to the first stage, including a second amplifier (CMOS amplifier stage 2) configured to amplify the difference signal between the first differential pair of output signals ( Von1 and Vop1 ) and output a second differential pair of output signals (Von and Vop) , and a second CMFB circuit (CMFB2) including a second CMFB component that receives the second differential pair of output signals ( Von and Vop ) and a second reference signal (V CMO ) and generates a second control signal (V CM2 ) to regulate the second common-mode voltage of the second amplifier to a second reference voltage ( corresponding to the second reference signal V CMO ) . The Figueiredo discloses each limitation of claim 1 except, at most, the specific arrangement whereby the first CMFB component directly receives the first differential pair of output signals (i.e., the differential output signals of the first/input stage) as the sensed feedback variable. In Figueiredo, CMFB₁ (the first CMFB circuit controlling the input stage) receives V_CM2 — the averaged common-mode signal derived from the second/output stage's differential output voltages V_op and V_on — and the reference voltage V_CMO, rather than directly sensing the differential pair of output signals of the first/input stage itself. See Figueiredo, Section II-A, Figs. 1–2. All remaining structural elements are disclosed: the first amplifier (M₁₂ ₐ , ᵦ , M₁₃ ₐ , ᵦ , input stage); the second amplifier (M₂₂ ₐ , ᵦ , M₂₃ ₐ , ᵦ , output stage); the first CMFB circuit (CMFB₁, inverter pair M₃₁–M₃₄) generating control signals V_CM1P and V_CM1N to regulate the input stage CM voltage; the second CMFB circuit (CMFB₂, switched-capacitor network) receiving V_op and V_on (second stage differential outputs) and V_CMO, and generating V_CM2 to regulate the output stage CM voltage; and the cascaded, two-stage fully differential amplifier architecture. See Figueiredo, Figs. 1–2, Section II-A. Fig. 1 of Li reproduce d by the examiner for ease of reference. Li is applied to supply any deficiency in the specific sensing arrangement of the first CMFB component. The Li discloses a common-mode feedback circuit (130) that receives the output voltage (VOUT) — which in a differential amplifier corresponds to the differential output signals — and a reference voltage ( V_Ref ), and provides a feedback signal (V_FB) to adjust the common-mode voltage of the amplification circuit. See Li , § 0005, § 0052– § 0054, Figs. 1, 8. A second summation circuit (131) receives the output voltage and generates the common-mode voltage V_CM from it. See Li , § 0054, Fig. 8. First and second level switching circuits (132, 133) process V_CM and V_Ref , respectively, and feed into an amplification circuit (134) whose output is the feedback signal V_FB. Id. It would have been obvious to a POSITA to modify the first CMFB circuit (CMFB₁) of the Figueiredo amplifier to directly receive the first differential pair of output signals of the input stage — rather than the averaged and processed V_CM2 signal from the output stage — in view of the Li 's teaching that a common-mode feedback circuit directly senses the differential output signals of the stage it controls to derive the common-mode voltage for comparison against a reference. The motivation for making this modification is clearly articulated in the art: directly sensing the output signals of the stage being regulated provides faster, more accurate common-mode feedback with reduced latency compared to using an indirectly derived signal passed through an intermediate averaging stage. This is a well-recognized principle in CMFB design. See Figueiredo, Section II-C (discussing the complexity of the CM feedback path and its impact on CM stability and bandwidth). A POSITA would have had clear motivation and a reasonable expectation of success in implementing this straightforward architectural adjustment within the fully differential two-stage framework already taught by Figueiredo. Claim 1 is unpatentable under 35 U.S.C. § 103. Claim 2 depends on claim 1 and additionally specifies that the first reference voltage is obtained by subtracting a predetermined voltage from an operation voltage. The Figueiredo reference discloses a reference voltage V_CMO for CMFB₁ that is typically provided by a bandgap circuit, setting a target CM voltage for the input stage. See Figueiredo, Section II-A ("a constant voltage, V_CMO (normally provided by a bandgap circuit)"). The Figueiredo reference does not explicitly characterize V_CMO as being derived by subtracting a predetermined voltage from an operating voltage. The Li expressly discloses that the reference voltage V_Ref may be configured to vary with the operating voltage V_DD — and in particular, that the reference voltage generation circuit (120) may be implemented as a voltage divider circuit (1211) located between the operating voltage and ground, wherein V_Ref = V_v is a voltage at a voltage divider node, which is equivalent to V_DD multiplied by a ratio R₂/(R₁+R₂), or equivalently, V_DD minus a fraction of V_DD that constitutes the predetermined voltage. See Li , § 0047, Fig. 5. The Li further discloses in § 0048 and Fig. 6 a reference voltage V_PVT generated as a summation circuit output V_PVT = § R₁ ‖ R₂R₃/R₁ × V_PT + § R₁ ‖ R₂ ‖ R₃/R₁ × V_DD, which explicitly depends on the operating voltage V_DD. See Li , § 0044– § 0049, Eq. (2). It would have been obvious to a POSITA to implement the first reference voltage of the modified Figueiredo amplifier as a voltage obtained by subtracting a predetermined voltage from the operating voltage — as taught by the Li 's voltage divider implementation — in order to track variations in the operating voltage and thereby maintain the voltage margin of the transistors in the saturation region across varying supply conditions, which is a well-understood design objective in low-voltage analog circuit design. Claim 3 depends on claim 2 and further specifies that the set value is 1/2, and the predetermined voltage is independent from the operation voltage. The specification of a set value of 1/2 for the predetermined fraction of the operating voltage is inherent in the standard design of fully differential amplifiers, in which the ideal output common-mode voltage — and thus the optimal reference voltage for the common-mode feedback circuit — is one-half of the supply voltage (V_DD/2). This design choice is universally recognized as the standard operating point that maximizes the output swing of a fully differential amplifier operating between V_DD and ground. See Figueiredo, Section II-F (describing the output swing analysis in terms of V_DD, and the V_OD terms); see also Figueiredo, Section II-A ("The input CM voltage and V_CMO were set to 550 mV" with V_DD = 1.2 V, yielding approximately V_DD/2 ≈ 0.6 V). The specification that the predetermined voltage is independent from the operation voltage is explicitly taught by the Li . As stated in § 0047 and illustrated in Fig. 5, the voltage divider implementation of the reference voltage generation circuit produces a reference voltage V_v that is a fixed fraction of V_DD. However, in the implementation of Fig. 4, the reference voltage V_PT is the drain voltage of MOS transistor M₂₃ biased by a constant current source I₁, which reflects temperature and process variations but is independent of V_DD — i.e., the predetermined offset (threshold voltage V_th minus the overdrive component) is not a function of the operating voltage. See Li , § 0040– § 0046, Eq. (1). A POSITA would have recognized the ability to select either a V_DD-dependent or V_DD-independent reference voltage depending on the design requirements, and would have had clear motivation and reasonable expectation of success in implementing a V_DD-independent reference voltage at the midpoint V_DD/2. Claim 4 depends on claim 3 and further specifies that the first CMFB circuit includes a reference signal source comprising: (a) a first transistor having a first end connected to the operation voltage, a second end, and a third end connected to the second end and the first CMFB component; and (b) a first constant current source connected between the second end and a ground end. The specific reference signal source recited in claim 4 — comprising a MOS transistor in a diode-connected configuration (gate and drain shorted together, i.e., the third end connected to the second end) with its first end (source) connected to the operating voltage and a constant current source pulling its second end (drain/gate) to ground — is expressly and directly disclosed in the Li 's reference voltage generation circuit 1201. See Li , Fig. 4, § 0007 ("the first bias circuit 1201 is configured to provide a drain current to the first MOS transistor M₂₃, a gate of the first MOS transistor M₂₃ is short-circuited to a drain, and the reference voltage is a drain voltage of the first MOS transistor"). The constant current source I₁ is explicitly shown connected between the supply node and the drain/gate of M₂₃, with M₂₃'s source connected to ground. See Li , Fig. 4. This configuration is the standard PTAT-based reference voltage generation circuit in CMOS analog design and was well within the ordinary skill in the art. It would have been obvious to a POSITA to implement the reference signal source for the first CMFB circuit of the modified Figueiredo amplifier using the diode-connected MOS transistor and constant current source topology taught by the Li , as this represents the most straightforward and compact reference generation technique for producing a voltage that tracks process and temperature variations correlated with the amplifier's own transistors, thereby achieving improved voltage margin tracking. The motivation, predictability, and expectation of success are well-established. Claim 5 depends on claim 3 and specifies that the first amplifier and the second amplifier are connected to a common power source that provides the operation voltage. The Figueiredo reference expressly and unambiguously discloses that both the input stage (first amplifier) and the output stage (second amplifier) of the two-stage fully differential amplifier are powered by the same supply voltage V_DD. See Figueiredo, Fig. 1 (V_DD connected to M₁₁, M₂₁, and all stage load transistors), Section II-A. Both amplification stages and both CMFB circuits share the common power rail V_DD and ground (V_SS). Id. This is an inherent and fundamental architectural feature of the disclosed two-stage amplifier topology and requires no modification or inventive step. The connection of both amplifier stages to a common power source providing the operation voltage is a universally standard practice in integrated circuit amplifier design and is equally confirmed by the Li . See Li , § 0033 (V_DD powering the entire operational amplifier 100 including differential amplification circuit 110). Claim 6 recites an independent claim directed to a two-stage CMFB circuit adapted for a fully differential operational amplifier that includes a first amplifier and a second amplifier connected in series, comprising: (a) a first CMFB circuit including a first CMFB component that receives a first differential pair of output signals of the first amplifier and a first reference signal, generates a first control signal to regulate a first common-mode voltage of the first amplifier to a first reference voltage; and (b) a second CMFB circuit including a second CMFB component that receives a second differential pair of output signals of the second amplifier and a second reference signal, generates a second control signal to regulate a second common-mode voltage of the second amplifier to a second reference voltage. The Figueiredo reference discloses a two-stage CMFB circuit adapted for a two-stage fully differential amplifier. The second CMFB circuit (CMFB₂) receives V_op and V_on (second stage differential output signals) and V_CMO (second reference signal ), and generates V_CM2 (second control signal) to regulate the second common-mode voltage of the output stage amplifier to the reference voltage V_CMO. See Figueiredo, Fig. 2(a), Section II-A. The first CMFB circuit (CMFB₁) receives V_CM2 and V_ CMO, and generates V_CM1P and V_CM1N (first control signals) to regulate the first common-mode voltage of the input stage amplifier. See Figueiredo, Fig. 2(b), Section II-A. As discussed in the rejection of claim 1, the only potential gap is that CMFB₁ in Figueiredo receives V_CM2 (a processed CM voltage derived from the second stage outputs) rather than the raw first differential pair of output signals of the first amplifier. The Li supplies this deficiency by teaching that a CMFB circuit directly receives the differential output signals of the stage it controls, derives the common-mode voltage therefrom via a summation circuit (131), and compares it against a reference voltage ( V_Ref ) via level switching circuits (132, 133) and an amplification circuit (134) to generate a feedback signal that regulates the CM voltage of the amplifier to the reference voltage. See Li , § 0052– § 0058, Fig. 8. A POSITA would have had clear motivation and reasonable expectation of success in modifying CMFB₁ of Figueiredo to receive the first stage output signals directly, as taught by Li . Claim 7 depends on claim 6 and specifies that the first reference voltage is obtained by subtracting a predetermined voltage from an operation voltage. As discussed in the rejection of claim 2, the Li explicitly discloses reference voltage generation circuits that derive V_Ref from the operating voltage V_DD, including voltage divider implementations (Fig. 5) and summation circuit implementations (Fig. 6) wherein V_Ref represents a portion of V_DD, which is algebraically equivalent to V_DD minus a predetermined voltage. See Li , § 0047– § 0049. The same reasoning applies with full force to claim 7 in its dependence on claim 6. A POSITA would have had clear motivation to implement the first reference voltage of the two-stage CMFB circuit as a voltage derived from the operation voltage by subtracting a predetermined amount. Claim 8 depends on claim 7 and specifies that the predetermined voltage is independent from the operation voltage. As discussed in the rejection of claim 3, the Li teaches that the predetermined offset voltage in the reference voltage generation circuit may be made independent of the operating voltage V_DD, as is the case with the PTAT-based circuit of Fig. 4 where the reference voltage V_PT is determined by the threshold voltage V_th and the drain current I₁ of transistor M₂₃, neither of which depends on V_DD. See Li , § 0040– § 0046, Fig. 4, Eq. (1). The same analysis applies to claim 8. Claim 9 depends on claim 8 and specifies that the first CMFB circuit further includes a reference signal source comprising: (a) a first transistor having a first end connected to the operation voltage, a second end, and a third end connected to the second end and the first CMFB component; and (b) a first constant current source connected between the second end and a ground end. As discussed in the rejection of claim 4, the Li expressly discloses the diode-connected MOS transistor (M₂₃, gate shorted to drain) with constant current source (I₁) reference voltage generation circuit in its reference voltage generation circuit 1201. See Li , § 0007, Fig. 4. The structural elements recited in claim 9 correspond element-by-element to those disclosed in Li Fig. 4: the first transistor (M₂₃) with its first end (source connected to ground — though connection polarity may be adapted for PMOS/NMOS), second end (drain), and third end (gate shorted to drain), and the first constant current source (I₁) connected between the supply and the drain. The identical analysis as set forth in the rejection of claim 4 applies with equal force here. Claim 10 depends on claim 9 and specifies that the first amplifier and the second amplifier are connected to a common power source that provides the operation voltage. As discussed in the rejection of claim 5, the Figueiredo reference inherently and explicitly discloses that both the input stage (first amplifier) and the output stage (second amplifier) of the two-stage amplifier share a common power supply V_DD. See Figueiredo, Fig. 1. The connection of multiple amplification stages to a single common power supply is a universally standard and mandatory practice in integrated single-chip amplifier design — no design practitioner would supply two cascaded stages within the same integrated circuit from separate, independent power supplies absent a compelling application-specific reason, and the Figueiredo architecture presents no such reason. The Li equally confirms this standard practice. See Li , § 0033, Figs. 1–3 (V_DD powering all stages of operational amplifier 100). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.