DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Hajime Tsukahara et al (US 20240103560 A1) in view of Huh Sang Gi (KR 20040069884 A).
Regarding claim 1, Tsukahara et al discloses a document processing device (¶ [26]), comprising:
a processor (Fig. 2 numeral 10) configured to receive a document output command to generate a first differential signal (¶ [27] and ¶ [35-36] data processing control device receives data and converts to differential signal via LVDS); and
a printing engine (¶ [27] data output device generating printed image data; ¶ [47] data output device 30) connected to the processor (Fig. 2 output device 30 connected to processing control device 10) and configured to receive the first differential signal (¶ [30]) and
Tsukahara et al fails to explicitly disclose a print engine which converts the first differential signal into a first interference-free information packet; wherein when the printing engine has already obtained the first interference-free information packet, the printing engine sends a buffer status checking signal to the processor.
Sang Gi, in the same field of endeavor of providing a differential signal communication system (¶ [22]), teaches a print engine which converts the first differential signal into a first interference-free information packet (¶ [10]); wherein when the printing engine has already obtained the first interference-free information packet, the printing engine sends a buffer status checking signal to the processor (¶ [33-35] notification sent to processor of lock status).
It would have been obvious to one of ordinary skill in the art before the invention was effectively filed for the document processing device as disclosed by Tsukahara et al comprising a processor configured to receive a document output command to generate a first differential signal to utilize the teachings of Sang Gi which teaches a print engine which converts the first differential signal into a first interference-free information packet; wherein when the printing engine has already obtained the first interference-free information packet, the printing engine sends a buffer status checking signal to the processor to initiate subsequent transmission or dispose of a packet when an error is determined and eliminate wasteful processing while providing an optimal output image.
Claims 2-4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Tsukahara et al in view of Sang Gi as applied to claim 1 above, and further in view of Masao Nakamura (JP 2014138344 A).
Regarding claim 2, Tsukahara et al discloses the document processing device according to claim 1 (see rejection of claim 1), wherein the printing engine comprises:
a driver (Fig. 2 numeral 102) connected to the processor (Fig. 2) to receive the first differential signal and convert the first differential signal into the first interference-free information packet (¶ [41]); and
Tsukahara et al fails to explicitly disclose a light irradiator connected to the driver and configured to generate an optical signal according to the first interference-free information packet.
Nakamura, in the same field of endeavor of improving noise resistance of a re-transmission request signal (Abstract), teaches a light irradiator connected to the driver and configured to generate an optical signal according to the first interference-free information packet (¶ [34] packets output to output image data in line units, ¶ [26] exposure unit scans photosensitive member to print image based on packets received).
It would have been obvious to one of ordinary skill in the art before the invention was effectively filed for the document processing device as disclosed by Tsukahara et al comprising a processor configured to receive a document output command to generate a first differential signal to utilize the teachings of Nakamura which teaches a light irradiator connected to the driver and configured to generate an optical signal according to the first interference-free information packet to aid in the prevention of false detection of noise and only necessary packets transmitted for image creation.
Regarding claim 3, Tsukahara et al discloses the document processing device according to claim 2 (see rejection of claim 2), wherein the driver comprises:
a clock synchronization circuit connected to the processor and configured to obtain a first clock signal from the processor (¶ [36] and [41]), and generate a synchronization clock signal according to the first clock signal and a feedback signal corresponding to the first clock signal (¶ [37]);
a buffer connected to the clock synchronization circuit (¶ [41-42] line memory temporarily holds data); and
a driving processing circuit connected to the clock synchronization circuit and the buffer, and configured to receive the synchronization clock signal and the first interference-free information packet (¶ [46]);
wherein when the driving processing circuit receives the first interference-free information packet and the synchronization clock signal, it stores the first interference-free information packet into the buffer according to the synchronization clock signal (¶ [46] and ¶ [68] memory write processing; Fig. 2).
Regarding claim 4, Tsukahara et al discloses the document processing device according to claim 3 (see rejection of claim 3), wherein when the synchronization clock signal is asserted, the driving processing circuit determines whether the buffer has stored the first interference-free information packet or determines whether the clock synchronization circuit has lost lock according to a trigger signal of the synchronization clock signal (¶ [45-46]).
Tsukahara et al fails to explicitly disclose if the clock synchronization circuit has lost lock, the driving processing circuit sets the buffer status checking signal to a first potential signal.
Sang Gi teaches if the clock synchronization circuit has lost lock, the driving processing circuit sets the buffer status checking signal to a first potential signal (¶ [35] abnormal state).
It would have been obvious to one of ordinary skill in the art before the invention was effectively filed for the document processing device as disclosed by Tsukahara et al comprising a processor configured to receive a document output command to generate a first differential signal to utilize the teachings of Sang Gi which teaches if the clock synchronization circuit has lost lock, the driving processing circuit sets the buffer status checking signal to a first potential signal to eliminate wasteful processing while providing an optimal output image.
Regarding claim 6, Tsukahara et al discloses a signal transmission method of a document processing device (see rejection of claim 1), which is executed by the document processing device (see rejection of claim 1) and comprises the following steps:
obtaining a document output command (see rejection of claim 1);
generating a first differential signal according to the document output command (see rejection of claim 1);
converting the first differential signal to generate a first interference-free information packet (see rejection of claim 1); and
sending a buffer status checking signal if the first interference-free information packet is already available (see rejection of claim 1).
Regarding claim 7, Tsukahara et al discloses the signal transmission method according to claim 6, the step of converting the first differential signal to generate the first interference-free information packet comprises the following sub-steps:
obtaining a first clock signal (¶ [41-42]);
determining whether to obtain a feedback signal corresponding to the first clock signal (¶ [43]);
if so, generating a synchronization clock signal (¶ [46] OSC generating clock signal when PLL clock signal is abnormal);
storing the first interference-free information packet according to the synchronization clock signal (¶ [47]).
Allowable Subject Matter
Claims 5 and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMARES Q WASHINGTON whose telephone number is (571) 270-1585. The examiner can normally be reached Mon-Fri 8:30am-4:30pm.
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/JAMARES Q WASHINGTON/Primary Examiner, Art Unit 2681
January 22, 2026