Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 11/04/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/06/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over HYAKUDAI et al. (USPGPUB No. 2022/0253398 A1, hereinafter referred to as Hyakudai) in view of Jacobs et al. (US Pat No. 10949365 B2, hereinafter referred to as Jacobs) and further in view of Holmes et al. (US Pat No. 12085583 B3, hereinafter referred to as Holmes) and further in view of HUANG et al. (USPGPUB No. 2022/0100421 A1, hereinafter referred to as HUANG).
Referring to claim 1, Hyakudai discloses a method for serial peripheral interface (SPI) control comprising: {“called serial peripheral interface”, see Fig. 1, [0006]}:
setting a register {“shift register 11-1 in the SPI/Master 11”, see Figs. 1 and 2, [0060], 2nd sentence} from at least one of an SPI master {“SPI/Master 11”, see Fig. 1, [0056], 1st sentence}; setting the SPI master {“ second packet includes interrupt information requesting [setting] that a master read”, see Figs. 1 and 2, [0227]; similarly recited in [0026], 1st sentence} to send a first data set of SPI serial data {send first data “transmit each serial signal included in the first serial signal group”, see Fig. 1, [0026]}; providing the first data set to an SPI slave device {“first serial signal group to the slave [device]”, see Figs. 1 and 2, [0026]}; and retrieving a second data set from the SPI slave device {“SPI data received from the SPI/Slave 12 to the packet encoder (ECP)” (see Fig. 6, [0111]) that become referred as “SPI packet 53” (see Figs. 6 and 8, [0112], 1st sentence}.
Hyakudai does not appear to explicitly disclose setting a general purpose input/output (GPIO) register to select an SPI data bus from at least one of an SPI master;
However, Jacobs discloses setting a general purpose input/output (GPIO) register {“the user can configure the device interface via software [registers]”, see Figs. 3 and 4, Col 9, lines 6-8} to select an SPI data bus {“GPIO pins 14 can be assigned to [select] connect to a sensor or device via the SPI protocol”, see Fig. 16, Col 12, lines 49-50} from at least one of an SPI master {behaving as a plurality of masters “I2C master” as well as “GPI pin 14 for MISO master in slave out”, see Fig. 16, both cited Col 12, lines 35-39, 49-60};
Hyakudai and Jacobs are analogous because they are from the same field of endeavor, peripheral bus device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Hyakudai and Jacobs before him or her, to modify Hyakudai’s “SPI/Master 11” (see Fig. 1) incorporating Jacobs’ “one or more microprocessor(s)” (see Fig. 4, [0033]).
The suggestion/motivation for doing so would have been to implement an IoT/Edge Gateways, are to connect to various non-IP based devices and sensors (Jacobs Col 2, lines 42-43) while managing a trade-off between low-cost controllers with a very limited number of interfaces vs over-engineered controllers which are very expensive and are not guaranteed to be future proof in terms of new connectors or protocols. (Col 3, lines 3-8).
Therefore, it would have been obvious to combine Jacobs with Hyakudai to obtain the invention as specified in the instant claim(s).
Neither Hyakudai or Jacobs appears to explicitly disclose retrieving a second data set directly from the SPI slave device;
However, Holmes discloses retrieving a second data set {“specific SPI devices or to read or write data via the SPI-Bridge GPIO port.”, see Fig. 41C, Col 82, lines 14-16} directly from the SPI slave device {“[second data] subsequent SPI slave data transactions commence”, see Fig. 41C, Col 82, lines 24-26};
Hyakudai/Jacobs and Holmes are analogous because they are from the same field of endeavor, peripheral bus device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Hyakudai/Jacobs and Holmes before him or her, to modify Hyakudai/Jacob’s system incorporating Holmes’ “SPI-Bridge” (see Fig. 41C).
The suggestion/motivation for doing so would have been to implement a SPI bridge component is provided between a microprocessor and a plurality of SPI I/O components which are connected in a parallel and/or series (or serial) topology, enabling parallel SPI using MISO and MOSI lines and serial (daisy chain) local chip select connection to other slaves (CSL/) including resolving any issues associated with multiple chip selects for multiple slaves (Col 80, lines 59-65, paraphrased).
Therefore, it would have been obvious to combine Holmes with Hyakudai/Jacobs to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting of Hyakudai, Jacobs, and Holmes appears to explicitly disclose the SPI slave device includes an SPI Slave multiplexer (MUX) within a complex programmable logic device (CPLD);
However, HUANG discloses wherein the SPI slave device includes an SPI Slave multiplexer (MUX) {“MUX unit 114 is a switching device” (see Fig. 2, [0026], 1st sentence) through to “one or more [slave] memories 116a-116n” ([0026], 1st), said memories “memories 116a, 116b, 116c, and 116n are SPI flash memory devices” (see Fig. 2, [0025], 4th sentence)} within a complex programmable logic device (CPLD) {“these functions are programmed into [within] a complex programmable logic device CPLD”, see Fig. 2, [0026], 2nd sentence};
Hyakudai/Jacobs/Holmes and HUANG are analogous because they are from the same field of endeavor, peripheral bus device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Hyakudai/Jacobs/Holmes and HUANG before him or her, to modify Hyakudai/Jacob/Holmes’ system incorporating HUANG’s “system 100 that efficiently simultaneous programs SPI flash memory devices” (see Fig. 2, [0025], 1st sentence).
The suggestion/motivation for doing so would have been to implement a routine that efficiently programs multiple flash memories on a computing system including a modified MUX that addresses any number or all of a plurality of flash memories for simultaneous writing of firmware images to those memories as a way to address or (HUANG [0010] paraphrased) find bugs may be in existing firmware or new functions may be added in new firmware version while reducing time required to write a new image to all SPI flash memories in a computing device is based on the program data size, clock frequency, number of flash memories, and other factors (HUANG [0005] paraphrased).
Therefore, it would have been obvious to combine HUANG with Hyakudai/Jacobs/Holmes to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Hyakudai discloses wherein the first data set is retrieved via at least one of: a chip selection signal {“slave select signal (CS signal) output”, see Figs. 3A-3D, [0062], 2nd sentence} that enables only a selected device {“[selected device] for latching data when the CS signal enters an active state”, see Figs. 3A-3D, [0062], 2nd sentence}; a serial data signal of a master output slave input line {“in the SPI/Slave 12 via a MOSI pin”, see Fig. 2, [0060], 3rd sentence}; and a serial clock signal {“clock SCK supplied from the SPI/Master”, see Fig. 2, [0060], 1st sentence} against the serial data signal of the master output slave input line {“sequentially outputs serial data from a most significant bit (MSB) side in synchronization with the SCK”, see Fig. 2, [0060], 2nd sentence}.
As per claim 3, the rejection of claim 1 is incorporated and Hyakudai discloses wherein the second data set is retrieved {“SPI data received from the SPI/Slave 12 to the packet encoder (ECP) 41-2 for transmission to the SPI/Master 11”, see Figs. 2 and 5, [0111], 1st sentence} via a serial data signal of the master input slave output line {“shift register 11-1 sequentially fetches data from the M_MISO pin by the”, see Figs. 2 and 5, [0117], 2nd sentence}.
As per claim 4, the rejection of claim 2 is incorporated and Hyakudai discloses further comprising deactivating the chip selection signal {“returns (deasserts) the S_CS to the idle state in order to terminate the SPI communication”, see Figs. 5 and 6, [0110]}.
As per claim 5, the rejection of claim 1 is incorporated and Hyakudai discloses wherein the SPI data bus includes at least two groups of directional signals {“it each serial signal included in the second serial signal group to the master” indicates at least two groups as claimed, see Figs. 2, 5, and 6 [0018]}.
As per claim 6, the rejection of claim 5 is incorporated and Hyakudai discloses wherein the at least two groups of directional signals comprise a transmit group and a receive group {“while the serial communication by the SPI is the full-duplex communication method,” full duplex that includes both transmit and receive as claimed, see Fig. 4, [0074], 2nd sentence}.
As per claim 7, the rejection of claim 6 is incorporated and Hyakudai discloses wherein the transmit group sends data from the SPI master group to the SPI slave device {“e SPI/Master 11 designates individual SPI/Slave 12 by the CSn signal in the SPI control information, so that it is possible to perform bidirectional serial communication with the plurality of SPI/Slaves 12”, see Fig. 17, [0196]}.
As per claim 8, the rejection of claim 6 is incorporated and Hyakudai discloses, wherein the receive group sends data from the SPI master group to the SPI slave device {“by daisy chaining the plurality of SPI/Slaves 12, the SPI/Master 11 can simultaneously perform serial communication with the plurality of SPI/Slaves 12”, see Fig. 17, [0196]}.
Referring to claim 9-16 are system claims reciting claim functional language corresponding to the method claim of claims 1-8, respectively, thereby rejected under the same rationale as claims 1-8 recited above, inter alia, Hyakudai discloses a system for serial peripheral interface (SPI) control {“shift register 11-1 [controlled by] in the SPI/Master 11”, see Figs. 1 and 2, [0060], 2nd sentence}; and Jacobs discloses wherein the SPI control comprising a microcontroller {“interface (virtual port), using [microcontroller] GPIO pins on a microprocessor”, see Fig. 4, Col 9, lines 4-6}.
The 103 motivation for this claim set relied upon as recited in claim 1 above.
Referring to claim 17, 18, and 19 are method claims reciting claim functional language corresponding to the method claim of claims 1, 2, and 3, respectively, thereby rejected under the same rationale as claims 1, 2, and 3 recited above, inter alia, in particular claim 18, Hyakudai discloses further comprising retrieving a second data set {“SPI data received from the SPI/Slave 12 to the packet encoder (ECP) 41-2 for transmission to the SPI/Master 11”, see Figs. 2 and 5, [0111], 1st sentence} from the SPI slave device {“shift register 11-1 sequentially fetches data from the M_MISO pin by the [SPI slave device]”, see Figs. 2 and 5, [0117], 2nd sentence}.
The 103 motivation for this claim set relied upon as recited in claim 1 above.
Neither one of the group consisting of Hyakudai, Jacobs, and Holmes appears to explicitly disclose the SPI slave device includes an SPI Slave multiplexer (MUX) within a complex programmable logic device (CPLD);
However, HUANG discloses wherein the SPI slave device includes an SPI Slave multiplexer (MUX) {“MUX unit 114 is a switching device” (see Fig. 2, [0026], 1st sentence) through to “one or more [slave] memories 116a-116n” ([0026], 1st), said memories “memories 116a, 116b, 116c, and 116n are SPI flash memory devices” (see Fig. 2, [0025], 4th sentence)} within a complex programmable logic device (CPLD) {“these functions are programmed into [within] a complex programmable logic device CPLD”, see Fig. 2, [0026], 2nd sentence};
The HUANG 103 motivation for this claim set relied upon as recited in claim 1 above.
As per claim 20, the rejection of claim 17 is incorporated and Hyakudai wherein the second data set is retrieved via a serial data signal of the master input slave output line {“shift register 11-1 sequentially fetches data from the M_MISO pin by the”, see Figs. 2 and 5, [0117], 2nd sentence}.
Response to Arguments
Applicant’s arguments, filed on 04/06/2026, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative of the current state of the art regarding claim 1’s “SPI”, “serial peripheral interface”, “GPIO” or “register”: US 11960434 B2, US 20230385216 A1, and US 10055376 B1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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