DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 5-12 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the workload scheduler" in line 17. There is insufficient antecedent basis for this limitation in the claim because there is prior instance of ‘workload scheduler’, and the subsequent instance indicates “a workload scheduler of the host machine” and therefore the correspondence between the two limitations is ambiguous. Claims 2 and 5-12 are rejected due to dependence on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5, 7-8, 11-13, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraj et al. (US Pub. No. 2022/0012396), hereinafter referred to as Jayaraj, in view of Suzuki et al. (US Pub. No. 2017/0185138), hereinafter referred to as Suzuki, further in view of Koker et al. (US Pub. No. 2018/0301119), hereinafter referred to as Koker.
As to claims 1 and 13, Jayaraj discloses a computing system comprising: a processor (fig. 3, IC 12); a voltage regulator (fig. 3, regulator 70/72) for providing a supply voltage, at a supply voltage level, to the processor; a board management controller (fig. 3, BMC) coupled to the voltage regulator by a controller- regulator communication link and operable to instruct the voltage regulator to set the supply voltage level to one of at least an idle voltage level or an active voltage level that is higher than the idle voltage level (the board management controller…may control any number of load switches, such as load switches 84A, 84B, 84C, to distribute power from the aux connector power supply rail 76 and PCIe edge connector power supply rail 78; [0025]; one peak load time, one off peak load time, [0039]); and a host machine (fig. 3, Host 18) coupled to the board management controller by a host-controller communication link, operable to schedule workloads for the processor (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]), and operable to generate a voltage setting command for directing the board management controller to instruct the voltage regulator to set the supply voltage level (Once the configuration profile 66 has been selected based on the application workload (e.g., the request), the board management controller 62 may reconfigure the power inlet connectors 76, 78, the voltage regulators 70, 72, and the load switches 84A, 84B, 84C based on the selected configuration profile 66, [0028]), wherein when the processor is idle and the host machine determines that a workload is scheduled for the processor at an active time the host machine generates the voltage setting command directing the board management controller to instruct the voltage regulator to set the supply voltage level to the active voltage level at the active time (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]; the board management controller…may control any number of load switches, such as load switches 84A, 84B, 84C, to distribute power from the aux connector power supply rail 76 and PCIe edge connector power supply rail 78; [0025]; The time of day 152 may include a peak load time 154, a first workload transition time 156…The peak load time 154 may correspond to a high power level configuration profile (e.g., the second configuration profile 66B) for the integrated circuit 12. The first workload transition time 156 may correspond to reconfiguration of the integrated circuit 12 from one configuration profile to another configuration profile, [0039]),
While Jayaraj teaches the workload scheduler sends the voltage setting command to the board management controller (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]; Once the configuration profile 66 has been selected based on the application workload (e.g., the request), the board management controller 62 may…based on the selected configuration profile 66, [0028]), Jayaraj does not appear to explicitly disclose the command is sent via an application programming interface (API) of the host machine.
Additionally, while Jayaraj suggests the systems is capable of determine wherein upon the supply voltage level reaching the voltage level of a configuration (board management controller 62 may determine no voltage is passing through the voltage regulators, [0034]) and the board management controller sends a completion signal to a workload scheduler of the host machine indicating the active configuration (the board management controller 62 may receive a confirmation signal indicating the integrated circuit 12 has been configured according to the configuration profile 66. At numeral 144, the board management controller 62 may generate and/or may transmit the confirmation signal to the host 18; [0038]), Jayaraj does not appear to explicitly disclose determining that the supply voltage level has reached the active voltage level so that the host machine does not launch workloads for the processor while the supply voltage level is too low.
However, in similar endeavor of power supply management, Suzuki discloses the command is sent via an application programming interface (API) of the host machine (an application programming interface (API) to instruct the BMC to switch a power supply, [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj and Suzuki before him or her, to substitute the anticipated power management command component of Jayaraj with the API of Suzuki because Jayaraj demonstrates a device which differed from the claimed device by the substitution of a API for the anticipated power management command component, Suzuki demonstrates that the substitute component and their functions were known in the art, and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have provided a predictable power management.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Furthermore, Koker discloses determining that the supply voltage level has reached the active voltage level so that the host machine does not launch workloads for the processor while the supply voltage level is too low (front end 208 can be configured to ensure the processing cluster array 212 is configured to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated, [0048]; issuing a command to a voltage regulator coupled to the processor to increase an output voltage of the voltage regulator to a target operating point, to enable the GPU to operate at the increased performance state; and in response to the output voltage reaching a first interim operating voltage, enabling the GPU to execute a graphics workload at an interim performance stat, [0293])
Jayaraj, Suzuki, and Koker are analogous art because they are from the same field of endeavor, power supply management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj, Suzuki, and Koker before him or her, to modify the power system of Jayaraj in view of Suzuki to include the voltage level tracking of Koker because tracking would allow operations to be launch when the appropriate voltage levels have been realized.
The suggestion/motivation for doing so would have been to ensure the configuration voltage supply level is achieved before workloads are initiated (Koker: [0048], [0144])
Therefore, it would have been obvious to combine Jayaraj, Suzuki, and Koker to obtain the invention as specified in the instant claim.
As to claims 5 and 16, Jayaraj discloses wherein the host machine generates the voltage setting command periodically (Fig. 6, peak and off peak periods).
As to claims 7 and 18, Jayaraj discloses the processor is an application- specific integrated circuit (ASIC) ([0016]).
As to claims 8 and 19, Jayaraj discloses the host machine is operable to assign machine learning workloads to the ASIC (to perform…machine learning, [0040]).
As to claim 11, Jayaraj discloses the processor, the voltage regulator, and the board management controller are part of an accelerator hardware tray (fig. 3, Add in card 10; for acceleration of a specific task and/or workload, [0023]), and wherein the host machine comprises a workload scheduler for scheduling the workloads for the processor and generating the voltage setting command (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]; the board management controller…may control any number of load switches, such as load switches 84A, 84B, 84C, to distribute power from the aux connector power supply rail 76 and PCIe edge connector power supply rail 78; [0025]), and operable to communicate with the accelerator hardware tray over the host-controller communication link (the host may communicate instructions from the host program to the integrated circuit 12 via a communications link, which may be, for example, direct memory access (DMA) communications or peripheral component interconnect express (PCIe) communications, [0017]).
Jayaraj does not appear to explicitly disclose an application programming interface (API).
However, in similar endeavor of power supply management, Suzuki discloses the (API) (an application programming interface (API) to instruct the BMC to switch a power supply, [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj and Suzuki before him or her, to substitute the anticipated power management command component of Jayaraj with the API of Suzuki because Jayaraj demonstrates a device which differed from the claimed device by the substitution of a API for the anticipated power management command component, Suzuki demonstrates that the substitute component and their functions were known in the art, and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have provided a predictable power management.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
As to claim 12, Jayaraj discloses the host-controller communication link comprises a peripheral component interconnect express (PCIe) bus (the host may communicate instructions from the host program to the integrated circuit 12 via a communications link, which may be, for example, direct memory access (DMA) communications or peripheral component interconnect express (PCIe) communications, [0017]) or a universal serial bus (USB).
As to claim 20, Jayaraj discloses the workload scheduler is executed by the host machine (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]), wherein the processor, the voltage regulator, and the board management controller are part of an accelerator hardware tray (fig. 3, Add in card 10; for acceleration of a specific task and/or workload, [0023]), and wherein the host machine provides the voltage setting command to the accelerator hardware tray, and wherein the board management controller responds to the voltage setting command by instructing the voltage regulator to set the supply voltage level to one of at least the idle voltage level or the active voltage level (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]; Once the configuration profile 66 has been selected based on the application workload (e.g., the request), the board management controller 62 may reconfigure the power inlet connectors 76, 78, the voltage regulators 70, 72, and the load switches 84A, 84B, 84C based on the selected configuration profile 66, [0028]).
Claims 2, 6, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Jayaraj, Suzuki, and Koker, as applied to claims 1, 5, 7-8, 11-13, 16, and 18-20 above, further in view of Kardach et al. (US Pub. No. 2006/0288240), hereinafter referred to as Kardach.
As to claims 2 and 14, Jayaraj discloses when the host machine determines an idle time the host machine generates the voltage setting command directing the board management controller to instruct the voltage regulator to set the supply voltage level to the idle voltage level at the idle time (a host controller 68 may request reconfiguration of a programmable logic device according to a specific workload, [0023]; the board management controller…may control any number of load switches, such as load switches 84A, 84B, 84C, to distribute power from the aux connector power supply rail 76 and PCIe edge connector power supply rail 78; [0025]; The time of day 152 may include…an off peak load time 158, and a second workload transition time 160… the off peak load time 158 may correspond to a low power level configuration profile (e.g., the first configuration profile 66A, the third configuration profile 66C). The second workload transition time 160 may correspond to reconfiguration of the integrated circuit 12, [0039]).
While Jayaraj teaches transition workload power configurations between peak and off peak load times, the combination of Jayaraj, Suzuki, and Koker is silent the range of workloads which equates to peak and off peak load times, and therefore does not appear to specifically equate the transition to when “no workload is scheduled for the processor.”
However, Kardach teaches transitioning when a scheduled workload is complete, which is an instance “no workload is scheduled for the processor” (When the workload is complete, the processor 14 can return to one of the idle states, [0019]).
Jayaraj, Koker, and Kardach are analogous art because they are from the same field of endeavor, managing power consumption.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj, Suzuki, Koker, and Kardach before him or her, to modify the power management of the combination of Jayaraj, Suzuki, and Koker to include the workload completion transition of Kardach because transition after completion of the workload would instantly reduce the power consumption when processing isn’t required.
The suggestion/motivation for doing so would have been to transition between power states on a relatively fine level of granularity (Kardach: [0019]).
Therefore, it would have been obvious to combine Jayaraj, Suzuki, Koker, and Kardach to obtain the invention as specified in the instant claim.
As to claims 6 and 17, Jayaraj discloses the board memory controller instructs the voltage regulator to set the supply voltage level to the active voltage level (the board management controller…may control any number of load switches, such as load switches 84A, 84B, 84C, to distribute power from the aux connector power supply rail 76 and PCIe edge connector power supply rail 78; [0025]).
The combination of Jayaraj, Suzuki, and Koker does not appear to explicitly disclose the action is taken “when no voltage setting command is generated for a period.”
However, Kardach teaches a timer driven interrupt, which is an instance ““when no voltage setting command is generated for a period” (When the OS schedule timer counts down, the timer can generate an interrupt to the processor 14, where the interrupt may awaken the processor 14 into an active/executing state, [0019]).
Jayaraj, Suzuki, koker, and Kardach are analogous art because they are from the same field of endeavor, managing power consumption.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj, Suzuki, Koker, and Kardach before him or her, to modify the power management of the combination of Jayaraj, Suzuki, and Koker to include the transition interrupt of Kardach in order to trigger a transition.
The suggestion/motivation for doing so would have been to transition between power states on a relatively fine level of granularity (Kardach: [0019]).
Therefore, it would have been obvious to combine Jayaraj, Suzuki, Koker, and Kardach to obtain the invention as specified in the instant claim.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraj, Suzuki, and Koker, as applied to claims 1, 5, 7-8, 11-13, 16, and 18-20 above, further in view of Thomas et al. (US Pub. No. 2018/0018189), hereinafter referred to as Thomas.
As to claim 9, while Jayaraj teaches a controller-regulator communication link, the combination of Jayaraj, Suzuki, and Koker does not appear to explicitly disclose an inter-integrated circuit (I2C) bus.
However, Thomas disclose an inter-integrated circuit (I2C) bus ([0075]).
Jayaraj, Suzuki, Koker, and Thomas are analogous art because they are from the same field of endeavor, power management architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jayaraj, Suzuki, Koker, and Thomas before him or her, to substitute the communication link anticipated by Jayaraj with the I2C bus taught by Thomas because Jayaraj demonstrates a device which differed from the claimed device by the substitution of a I2C bus for the anticipated communication link, Thomas demonstrates that the substitute component and their functions were known in the art, and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have provided a predictable communication link.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Jayaraj, Suzuki, Koker, and Thomas to obtain the invention as specified in the instant claim.
As to claim 10, the combination of Jayaraj, Koker, and Thomas discloses the I2C bus is a power management bus (PMBus) (Thomas: [0075]). The rationale to combine remains as indicated above.
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are moot in view the new grounds of rejection necessitated by the amendments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2023/0297159 of Daxer et al. is pertinent to power management and workload scheduling.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184