DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant’s amendments filed on 7/8/2026 have been entered.
Response to Arguments
Applicant’s arguments regarding Claims 1-10 have been fully considered and are persuasive. Therefore, the prior art rejections of Claims 1-10 have been withdrawn. However, a new ground of rejection, which was necessitated by Applicant’s amendments, has been found and now follows.
In the interest of compact prosecution, the examiner notes that further description of the first metal gate recess stop structure 207 of the instant application is different from the PDL structure 212 Chung et al/124 and 126 Lin et al, as shown in Fig 2B and Fig 2C of the instant application (i.e 207 is at the same height as S/D region 208 Fig 2B cross section X-X or 207 has the same width as nanosheet 204 Fig 2C cross section Y-Y, etc.), would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al (US 2022/0208982) in view of Lin et al (US 2023/0260832).
Regarding Claim 1, Chung et al discloses a field effect transistor (FET) structure (semiconductor device 200 [0016] Fig 20B), comprising:
a gate structure (metal gate stack 268 [0039] and Si layer 210B [0032] Fig 20C), extending in a first horizontal direction (x direction Fig 20B) and disposed between a first epitaxial (EPI) source/drain (S/D) structure (epitaxial S/D features 240 [0033] shown in annotated Fig 20C) and a second EPI S/D structure (epitaxial S/D features 240 [0033] shown in annotated Fig 20C)) set apart in a second horizontal direction (y direction Fig 20C),
the gate structure (268 and 210B Fig 20C) comprising a channel structure (second semiconductor layers 210B functions as a channel [0021] Fig 20C) and a vertical metal gate structure (metal gate stack 268 Fig 20C),
the channel structure (210B Fig 20C) comprising a plurality of vertically-stacked, horizontal channels (210B Fig 20C) connecting the first EPI S/D structure (240 shown in annotated Fig 20C) to the second EPI S/D structure (240 shown in annotated Fig 20C) in the second horizontal direction (y-direction Fig 20C) through the vertical metal gate structure (268 Fig 20C) that at least partially surrounds the plurality of vertically-stacked, horizontal channels (210B Fig 20C),
wherein the vertical metal gate structure (268 Fig 20C) contains a first portion (shown in annotated Fig 20B) in the first horizontal direction (x direction Fig 20B) that contains the plurality of vertically-stacked, horizontal channels (210B Fig 20B) and
a second portion (shown in annotated Fig 20B) in the first horizontal direction (x direction Fig 20B) that does not contain the plurality of vertically-stacked, horizontal channels (210B Fig 20B);
a first metal gate recess stop structure (protective dielectric layer PDL 212 [0023] Fig 20B and Fig 20C) extending in the first horizontal direction (x direction Fig 20B) and disposed above the first portion (shown in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C); and
a frontside inter-layer dielectric (ILD) layer (interlayer dielectric layer ILD 254 [0035] Fig 20C and ILD 274 Fig 20B and Fig 20C) disposed above the vertical metal gate structure (268 Fig 20C) and the first metal gate recess stop structure (212 Fig 20B and Fig 20C).
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Chung et al does not directly disclose
wherein the first metal gate recess stop structure comprises at least one of silicon carbide (SiC), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), or polysilicon.
Lin et al, in the related art of semiconductor devices that include FET devices, discloses
wherein the first metal gate recess stop structure (etch stop layer 124 and ILD 126 [0055] Fig 26B) comprises at least one of silicon carbide (SiC), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al) (etch stop layer 124 may comprise aluminum oxide [0055] which is considered to comprise aluminum), titanium (Ti), tantalum (Ta), or polysilicon.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung et al to include wherein the first metal recess stop structures comprises aluminum oxide as taught by Lin et al in order to optimize electrical function while meeting protective dielectric qualities while acting as an etch stop [0055]. Further, a person of ordinary skill in the art would have recognized that having a recess stop structure that comprises aluminum oxide would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate)).
Regarding Claim 2, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
wherein the first metal gate recess stop structure (212 Fig 20B and Fig 20C Chung et al/124 and 126 Fig 26B Lin et al) disposed above the first portion (shown above in annotated Fig 20B Chung et al) of the vertical metal gate structure (268 Fig 20C Chung et al) extends in the first horizontal direction (x direction Fig 20B Chung et al) over at least a dimension of a top-most channel (210B Fig 20B Chung et al) of the plurality of vertically- stacked, horizontal channels (210B Fig 20B Chung et al) in the first horizontal direction (x direction Fig 20B Chung et al).
Regarding Claim 3, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination Chung et al and Lin et al further discloses
wherein the first metal gate recess stop structure (212 may be silicon nitride [0024] Fig 20B and Fig 20C) comprises at least one of aluminum oxide (A1203) (124 may be aluminum oxide [0055] Fig 26B Lin et al), aluminum nitride (AIN), titanium dioxide (TiO2), silicon nitride (SiN) (212 may be silicon nitride [0024] Fig 20B and Fig 20C Chung et al), tantalum (III) oxide (Ta2O3).
Regarding Claim 4, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
wherein a portion of the vertical metal gate structure (268 Fig 20C Chung et al) that is above a top-most channel of the plurality of vertically-stacked, horizontal channels (210B Fig 20C Chung et al) and below the first metal gate recess stop structure (212 Fig 20C Chung et al/124 and 126 Fig 26B Lin et al) has a vertical dimension of 4nm to 8nm (distance H4 is about 4nm-15nm Fig 20C Chung et al).
Regarding Claim 5, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
further comprising a second metal gate recess stop structure (CESL 272 [0046] Fig 20C Chung et al/123 and 126 Fig 26B Lin et al) disposed within the second portion (shown above in annotated Fig 20B, and shown in Fig 20A Chung et al) of the vertical metal gate structure (268 Fig 20C Chung et al) lower in a vertical direction than the first metal gate recess stop structure (212 Fig 20C/124 and 126 Fig 26B Lin et al).
Regarding Claim 6, the combination of Chung et al and Lin et al discloses the limitations of claim 5 as explained above. The combination of Chung et al and Lin et al further discloses
wherein the second metal gate recess stop structure (CESL 272 Fig 20C Chung et al) is lower in the vertical direction than a bottom-most channel (shown in the combination of Fig 20A and Fig 20B Chung et al) of the plurality of vertically- stacked, horizontal channels (210B Fig 20C Chung et al).
Regarding Claim 7, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
wherein a portion (254 Fig 20C Chung et al) of the ILD layer (254 and 274 Fig 20B and Fig 20C Chung et al) extends vertically into the second portion (shown above in annotated Fig 20B Chung et al) of the vertical metal gate structure (268 Fig 20C Chung et al) to a depth lower in the vertical direction than a bottom surface of the first metal gate recess stop structure (212 Fig 20B and Fig 20C Chung et al).
Regarding Claim 8, the combination of Chung et al and Lin et al discloses the limitations of claim 7 as explained above. The combination of Chung et al and Lin et al further discloses
wherein the portion of the ILD layer (254 Fig 20C Chung et al) that extends vertically into the second portion (shown above in annotated Fig 20B Chung et al) of the vertical metal gate structure (268 Fig 20C Chung et al) extends to a depth lower (shown in the combination of Fig 14A and Fig 20A Chung et al) in the vertical direction than a top surface of a top-most channel of the plurality of vertically- stacked, horizontal channels (210B Fig 20B and Fig 20C Chung et al).
Regarding Claim 9, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
wherein the portion (254 Fig 20C Chung et al) of the ILD layer (254 and 274 Fig 20B and Fig 20C Chung et al) that extends vertically into the second portion (shown above in annotated Fig 20B Chung et al) of the vertical metal gate structure (268 Fig 20C Chung et al) comprises silicon dioxide (SiO2) (254 may be boron doped silicon glass [0035] Chung et al which is known to be boron doped SiO2).
Regarding Claim 10, the combination of Chung et al and Lin et al discloses the limitations of claim 1 as explained above. The combination of Chung et al and Lin et al further discloses
wherein the first metal gate stop structure (124 may be aluminum oxide [0055] Fig 26B Lin et al) consists of a different material than the vertical metal gate structure (gate electrodes 266 may include titanium nitride, tantalum nitride, aluminum, tungsten or combinations thereof [0042] Chung et al).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 2020/0075723) which discloses vertical transport FETs FTFETs [0002], and Ando et al (US 2022/0165850) which discloses VTFETs [0002].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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