DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election, without traverse, of Invention I, Claims 1-10, drawn to a device, has been acknowledged. Claims 1-20 remain pending. Claims 11-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al (US 2022/0208982).
Regarding Claim 1, Chung et al discloses a field effect transistor (FET) structure (semiconductor device 200 [0016] Fig 20B), comprising:
a gate structure (metal gate stack 268 [0039] and Si layer 210B [0032] Fig 20C), extending in a first horizontal direction (x direction Fig 20B) and disposed between a first epitaxial (EPI) source/drain (S/D) structure (epitaxial S/D features 240 [0033] shown in annotated Fig 20C) and a second EPI S/D structure (epitaxial S/D features 240 [0033] shown in annotated Fig 20C)) set apart in a second horizontal direction (y direction Fig 20C),
the gate structure (268 and 210B Fig 20C) comprising a channel structure (second semiconductor layers 210B functions as a channel [0021] Fig 20C) and a vertical metal gate structure (metal gate stack 268 Fig 20C),
the channel structure (210B Fig 20C) comprising a plurality of vertically-stacked, horizontal channels (210B Fig 20C) connecting the first EPI S/D structure (240 shown in annotated Fig 20C) to the second EPI S/D structure (240 shown in annotated Fig 20C) in the second horizontal direction (y-direction Fig 20C) through the vertical metal gate structure (268 Fig 20C) that at least partially surrounds the plurality of vertically-stacked, horizontal channels (210B Fig 20C),
wherein the vertical metal gate structure (268 Fig 20C) contains a first portion (shown in annotated Fig 20B) in the first horizontal direction (x direction Fig 20B) that contains the plurality of vertically-stacked, horizontal channels (210B Fig 20B) and
a second portion (shown in annotated Fig 20B) in the first horizontal direction (x direction Fig 20B) that does not contain the plurality of vertically-stacked, horizontal channels (210B Fig 20B);
a first metal gate recess stop structure (protective dielectric layer PDL [0023] Fig 20B and Fig 20C) extending in the first horizontal direction (x direction Fig 20B) and disposed above the first portion (shown in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C); and
a frontside inter-layer dielectric (ILD) layer (interlayer dielectric layer ILD 254 [0035] Fig 20C and ILD 274 Fig 20B and Fig 20C) disposed above the vertical metal gate structure (268 Fig 20C) and the first metal gate recess stop structure (212 Fig 20B and Fig 20C).
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Regarding Claim 2, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein the first metal gate recess stop structure (212 Fig 20B and Fig 0C) disposed above the first portion (shown above in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C) extends in the first horizontal direction (x direction Fig 20B) over at least a dimension of a top-most channel (210B Fig 20B) of the plurality of vertically- stacked, horizontal channels (210B Fig 20B) in the first horizontal direction (x direction Fig 20B).
Regarding Claim 3, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein the first metal gate recess stop structure (212 may be silicon nitride [0024] Fig 20B and Fig 20C) comprises at least one of aluminum oxide (A1203), aluminum nitride (AIN), titanium dioxide (TiO2), silicon carbide (SiC), silicon nitride (SiN) (212 may be silicon nitride [0024] Fig 20B and Fig 20C), tantalum (III) oxide (Ta2O3), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), or polysilicon.
Regarding Claim 4, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein a portion of the vertical metal gate structure (268 Fig 20C) that is above a top-most channel of the plurality of vertically-stacked, horizontal channels (210B Fig 20C) and below the first metal gate recess stop structure (212 Fig 20C) has a vertical dimension of 4nm to 8nm (distance H4 is about 4nm-15nm Fig 20C).
Regarding Claim 5, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
further comprising a second metal gate recess stop structure (CESL 272 [0046] Fig 20C) disposed within the second portion (shown above in annotated Fig 20B, and shown in Fig 20A) of the vertical metal gate structure (268 Fig 20C) lower in a vertical direction than the first metal gate recess stop structure (212 Fig 20C).
Regarding Claim 6, Chung et al discloses the limitations of claim 5 as explained above. Chung et al further discloses
wherein the second metal gate recess stop structure (CESL 272 Fig 20C) is lower in the vertical direction than a bottom-most channel (shown in the combination of Fig 20A and Fig 20B) of the plurality of vertically- stacked, horizontal channels (210B Fig 20C).
Regarding Claim 7, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein a portion (254 Fig 20C) of the ILD layer (254 and 274 Fig 20B and Fig 20C) extends vertically into the second portion (shown above in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C) to a depth lower in the vertical direction than a bottom surface of the first metal gate recess stop structure (212 Fig 20B and Fig 20C).
Regarding Claim 8, Chung et al discloses the limitations of claim 7 as explained above. Chung et al further discloses
wherein the portion of the ILD layer (254 Fig 20C) that extends vertically into the second portion (shown above in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C) extends to a depth lower (shown in the combination of Fig 14A and Fig 20A) in the vertical direction than a top surface of a top-most channel of the plurality of vertically- stacked, horizontal channels (210B Fig 20B and Fig 20C).
Regarding Claim 9, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein the portion (254 Fig 20C) of the ILD layer (254 and 274 Fig 20B and Fig 20C) that extends vertically into the second portion (shown above in annotated Fig 20B) of the vertical metal gate structure (268 Fig 20C) comprises silicon dioxide (SiO2) (254 may be boron doped silicon glass [0035] which is known to be boron doped SiO2).
Regarding Claim 10, Chung et al discloses the limitations of claim 1 as explained above. Chung et al further discloses
wherein the first metal gate stop structure (212 may be silicon nitride [0024] Fig 20B and Fig 20C) consists of a different material than the vertical metal gate structure (gate electrodes 266 may include titanium nitride, tantalum nitride, aluminum, tungsten or combinations thereof [0042]).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 2020/0075723) which discloses vertical transport FETs FTFETs [0002], and Ando et al (US 2022/0165850) which discloses VTFETs [0002].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812