DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant’s arguments filed 07/20/2026 with respect to claims 1-20 have been fully considered but are not persuasive.
Claim Rejections - 35 USC § 101
With respect to this rejection, a ‘lock manager’ is within control module 230 of Applicant’s specification, which can be software; for example, paragraph 0051 of Applicant’s file specification discloses “[0051] The lock control module 230 may include a synchronization manager 231, a waiting queue 232, a lock manager 233, and a scheduler 234. In an embodiment, elements constituting the lock control module 230 may be implemented in software or hardware. The lock control module 230 may correspond to the lock control module LCM of FIG. 1”.
Claim Rejections - 35 USC § 102 and 103
Applicant’s arguments with respect to claims 1-20 have been fully considered but are moot in view of new interpretation of the cited reference based on most recent amendment.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject.
As per the independent claims and their dependent claims respectively, they are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Paragraph 0070 of the filed specification and body of claims do not limit structural features to perform the steps. Rather, the body of the claims are interpreted as purely software because paragraph 0051 stated that the method is being performed by software. Software is per se not a statutory class of invention. Therefore, the claims are rejected under 35 U.S.C. 101 because they are directed to software which is not a statutory class of invention.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-10, 13-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anand et al. (US pub. 2011/0161539), hereinafter, “Anand”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 7 and 15, Anand discloses a method of controlling access to shared resources in a system comprising a processor, and a memory storing a shared resource (shared resource 112 combined with wait queue 118 of fig. 1) and a waiting queue (wait queue 118) (see paragraph 0008, which discloses “embodiments of the invention provide a method, apparatus and computer program product for enabling a thread to acquire a lock associated with a shared resource, when a locking mechanism is used therewith, wherein each embodiment reduces waiting time and enhances efficiency in using the shared resource. One embodiment is associated with a plurality of processors, which includes two or more processors that each provides a specified thread to access a shared resource”), the method comprising: executing, by the processor, a first process (a waiter thread of the wait queue 118 receiving the lock and access to shared resource 112 during time (A+B), as discloses in paragraph 0025) that acquires a lock on the shared resource (shared resource 112 combined with wait queue 118) (see paragraph 0008, which discloses “the shared resource can only be accessed by one thread at a given time, a locking mechanism enables a first one of the specified threads to access the shared resource while each of the other specified threads is retained in a waiting queue”); adding a second process (a second thread being added to wait queue 118) to the waiting queue based on the second process performing an operation (wait queue 118 receiving/storing the second thread) on the shared resource (see paragraph 0008, which discloses “a second one of the specified threads occupies a position of highest priority in the queue”); determining, by a lock manager (function of handoff lock mechanism 116, as discloses in paragraph 0030), whether to deactivate preemption for the processor based on a priority of the second process (see paragraph 0030 and fig. 2. ‘Deactivate preemption’ is being equated to giving the lock to a new thread instead of a second thread with the highest priority that’s waiting in queue 118. Note, this consideration, determination, takes place during time B, during the first process, as discloses in paragraph 0025; for example, paragraph 0025 discloses “moreover, the time B can be significantly greater than the time A. Accordingly, an embodiment of the invention is provided to enable a new thread, which seeks to access the shared resource during a time B, to be considered for selection as the next thread to receive the lock. Herein, the terms "new thread" and "additional thread" mean a thread that was not previously a waiter thread, or a thread that has not been waiting in the queue”); based on determining to deactivate preemption for the processor, maintaining execution of the first process by the processor without context switching to the second process until execution of the first process on the shared resource is completed (as stated right above, the consideration/determination of giving the lock to the highest priority queued thread or a newly received thread takes place during time B, during the first process, as discloses in paragraph 0025; for example, paragraph 0025 discloses “moreover, the time B can be significantly greater than the time A. Accordingly, an embodiment of the invention is provided to enable a new thread, which seeks to access the shared resource during a time B, to be considered for selection as the next thread to receive the lock. Herein, the terms "new thread" and "additional thread" mean a thread that was not previously a waiter thread, or a thread that has not been waiting in the queue”); retrieving the lock from the first process after execution of the first process on the shared resource is completed; and reactivating preemption for the processor (see step 214 of fig. 2).
3. As per claims 2, 8 and 19, Anand discloses “The method of claim 1” [See rejection to claim 1 above], wherein the priority of the second process is determined based on at least one of a contribution group to which the second process belongs, a latency sensitivity of the second process [see paragraph 0023, which discloses “the first position, or front end 124 of queue 118 is the location for the thread that has highest priority in the queue. Under certain conditions, the thread in this position would be woken up and given the lock, after the lock was released by the thread which had been holding it. Priority in queue 118 could be determined on a first in, first out (FIFO) or priority basis, so that the thread at position 124 would always be the thread that had been waiting longest in the queue. The newest or most recent thread sent to access the shared resource would be placed at the back of the queue. The queue may be implemented by placing the respective waiting threads on a linked list, with pointers to the highest priority and lowest priority of these threads”], and priority information set when the second process is created.
4. As per claims 3, 9 and 20, Anand discloses wherein the determining whether to deactivate preemption for the processor comprises: determining to deactivate preemption for the processor based on at least one of determining that the contribution group to which the second process belongs is a top-app group, determining that the second process is a real-time process having high latency sensitivity (see paragraph 0024, which discloses “wherein the policy can include giving the lock to the longest waiting thread in the queue”), and determining that the priority information is higher than a reference value.
5. As per claim 4, Anand discloses wherein context switching from the first process to the second process is prevented by deactivating preemption for the processor (see paragraph 0030).
6. As per claim 5, Anand discloses wherein the adding the second process to the waiting queue comprises: adding the second process to the waiting queue based on the second process performing an operation on the shared resource (see paragraph 0030).
7. As per claim 6, Anand discloses wherein, further comprising: executing, by the processor, the second process after reactivating preemption for the processor (see paragraph 0030).
8. As per claim 10, Anand discloses wherein the processor is a heterogeneous multi-core processor (processor hardware 100) comprising at least a first processing core and a second processing core, and wherein the first processing core is a little core and the second processing core is a big core (see paragraph 0018. Note, claim language doesn’t a difference between a ‘little’ core and a ‘big’ core).
9. As per claim 13, Anand discloses further comprising: setting a clock frequency of the processor to a first clock frequency based on the processor operating in the first mode; and setting a clock frequency of the processor to a second clock frequency based on the processor operating in the second mode, wherein the second clock frequency is higher than the first clock frequency (see paragraph 0025).
10. As per claim 14, Anand discloses wherein the adding the second process to the waiting queue comprises: adding the second process to the waiting queue based on the second process performing an operation on the shared resource (see paragraph 0023).
11. As per claim 16, Anand discloses wherein the lock comprises a read lock or a write lock, and further comprising: granting the read lock to at least one process to perform a read operation on the shared resource; and granting the write lock to only one process to perform a write operation on the shared resource (see paragraph 0023).
12. As per claim 17, Anand discloses wherein granting the read lock to the at least one process comprises: granting the read lock to the first process based on executing the read operation of the first process: and granting the read lock to the third process when the read operation of the third process is executed, wherein granting the write lock to only the one process comprises granting the write lock to the second process based on executing the write operation of the second process (see paragraph 0023).
Claim Rejections - 35 USC § 103
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claims 11-12 and 18 are rejected under 35 U.S.C. 103(a) as being unpatentable over Anand et al. (US pub. 2011/0161539), hereinafter, “Anand”, in view of Vaidyanathan et al. (US pub. # 2005/0080824), hereinafter, “Vaidyanathan”.
15. As per claim 11, Anand discloses “The method of claim 10” [See rejection to claim 10 above], but fails to expressly discloses wherein the executing the first process, by the processor operating in the second mode, comprises: migrating the first process from the first processing core to the second processing core.
Vaidyanathan discloses wherein the executing the first process, by the processor operating in the second mode, comprises: migrating the first process from the first processing core to the second processing core (see paragraphs 0027 and 0028, particularly paragraph 0028, which discloses “the first thread is scheduled to be processed by the second CPU”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Vaidyanathan’s teaching of a system of enhancing priority boosting such that a process that has a lock on a shared resource and whose priority has been boosted may obtain some CPU time as soon as possible, into Anand’s teaching of enabling a thread to acquire a lock associated with a shared resource, when a locking mechanism is used therewith, wherein each embodiment reduces waiting time and enhances efficiency in using the shared resource, for the ability/benefit of enhancing priority boosting of a scheduled thread.
16. As per claim 12, Anand discloses “The method of claim 10” [See rejection to claim 10 above], but fails to expressly discloses further comprising: based on controlling the processor to operate in the first mode, executing the second process through the first processing core.
Vaidyanathan discloses further comprising: based on controlling the processor to operate in the first mode, executing the second process through the first processing core (see paragraph 0027).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Vaidyanathan’s teaching of a system of enhancing priority boosting such that a process that has a lock on a shared resource and whose priority has been boosted may obtain some CPU time as soon as possible, into Anand’s teaching of enabling a thread to acquire a lock associated with a shared resource, when a locking mechanism is used therewith, wherein each embodiment reduces waiting time and enhances efficiency in using the shared resource, for the ability/benefit of enhancing priority boosting of a scheduled thread.
17. As per claim 18, Anand discloses “The method of claim 16” [See rejection to claim 16 above], but fails to expressly discloses wherein the determining whether to extend the read phase comprises determining to extend the read phase based on the priority of the second process being lower than the priority of the third process, and wherein the executing the read operation of the third process comprises executing the read operation of the third process in parallel with the read operation of the first process.
Vaidyanathan discloses wherein the determining whether to extend the read phase comprises determining to extend the read phase based on the priority of the second process being lower than the priority of the third process, and wherein the executing the read operation of the third process comprises executing the read operation of the third process in parallel with the read operation of the first process (see figures 1 and 3).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Vaidyanathan’s teaching of a system of enhancing priority boosting such that a process that has a lock on a shared resource and whose priority has been boosted may obtain some CPU time as soon as possible, into Anand’s teaching of enabling a thread to acquire a lock associated with a shared resource, when a locking mechanism is used therewith, wherein each embodiment reduces waiting time and enhances efficiency in using the shared resource, for the ability/benefit of enhancing priority boosting of a scheduled thread.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights