DETAILED ACTION
This action is responsive to the following: The amendments and arguments made in amendment filed on June 4, 2026.
Claims 1-2, 4, 7-10, 12, 15-20 are pending. Claims 1, 9, 17 are independent. Claims 3, 5-6, 11, and 13-14 are cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 4, 2026 has been entered.
Response to Amendment
The amendments filed on June 4, 2026 has been entered. Claims 1-2, 4, 7-10, 12, 15-20 remain pending. Claims 3, 5-6, 11, and 13-14 are cancelled by applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-2, 4, 7-10, 12, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190198514) in view of Lee (US 20160307633 A1) and Jung (US 20200381061).
Regarding Independent Claim 1, Kim teaches a method comprising:
receiving a request to perform a program operation (Fig. 17: WL9 PROGRAM) on a block of a memory device (Fig. 7: BLKi), wherein a block is set of vertically stacked memory cells (Fig. 7: NS11-NS33), wherein each memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells is addressable (Fig. 2: ADDR) by a respective wordline (Fig. 7: WL1-WL12);
determining whether the block is a fully functional block (para 43 “The ECC engine 42 may designate a memory block as a bad block, based on uncorrectable errors in data read from the nonvolatile memory device 50.)”;
responsive to determining that the block is not a fully functional block, determining which memory cell of the set of vertically stacked memory cells of the block is non-programmable (para 45 “The memory controller 40 may include a repair manage module 43b that uses a portion of the bad block as a partial normal region based on the error information. The repair manage module 43b may control the nonvolatile memory device 50 to perform a repair operation that uses the portion of the bad block as a partial normal region by referring to the error information stored in the bad block information register 49”);
responsive to determining that a top memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells is non-programmable (Fig. 15: BR), determining, a pass voltage adjustment value;
adjusting a default pass voltage (Fig. 17: VPPASS1); by the pass voltage adjustment value to generate an adjusted pass voltage (Fig. 17: VPPASS2); and
Kim further teaches wherein the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is a block (Fig. 7: BLKi) of the memory device (Fig. 2: 50).
Kim further teaches at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at “a top” (see Kim Fig. 15: memory cell at WL12, next to SST1) of the set of vertically stacked memory cells. It is also noted that Kim’s disclosure is applicable to marking regions of a block as “normal” and “bad,” instead of marking the entire block as bad (see Kim Fig. 15: normal region PNRG and bad region PBRG). As such, Kim’s disclosure embraces scenarios and would have been understood by those having ordinary skill in the NAND flash memory art as intended to designate bad cells, at any location in the block (including cells at the “top” of the vertical NAND string), so as to salvage useable cells in a block instead of marking a block with useable memory cells entirely bad.
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Lee teaches a method of adjusting the pass voltages based on the number of program erase cycles performed (Fig. 21: S530a).
And applying the adjusted pass voltage during a program verify operation (Fig. 21: S530a) of the memory cell of, the set of vertically stacked memory cells (Fig. 5: NS1)
It would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lee and Jung to the teachings of Kim to create a memory method of programming a memory device where the pass voltage used in the program verify operation is adjusted based on both the presence of a non-programmable cell within a vertical stack of memory cells and the number of program erase cycles the cells have undergone and their logical states.
Regarding Claim 2, Kim, Jung, and Lee teach the limitations of Claim 1. Kim further teaches wherein determining that at least one memory cell of the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is non-programmable (Fig. 15: BR) comprises:
identifying whether a wordline associated with the at least one memory cell of the set of vertically stacked memory cells is defective (para 44; “The memory controller 40 may include a bad block information register 49 that stores error information of the bad block. The memory controller 40 may store a first error information and a second error information in the bad block information register 49 as the error information. The first error information may be associated the uncorrectable errors of word-lines in the bad block”).
Regarding Claim 4, Kim, Jung, and Lee teach the limitations of Claim 1. Jung Further teaches wherein determining the pass voltage adjustment value further comprises:
for a given memory cell of the set of vertically stacked memory cells (Fig. 4: STR), identifying, from a plurality of entries in a pass voltage adjustment data structure , an entry associated with a logical state of the given memory cell (Fig. 11: Vpass_P, Vpass_E) and
Lee further teaches the number of PECs (Fig. 21: S530a), the entry comprising the pass voltage adjustment value, wherein each entry of the plurality of entries comprises a respective pass voltage adjustment value associated with a different logical state and a respective number of PECs.
Regarding Claim 7, Kim, Jung, and Lee teach the limitations of Claim 1.
Kim further teaches the method of claim 1, further comprising:
performing a read operation (Fig. 18: WL9 Read) on the set of vertically stacked memory cells (Fig. 7: NS11-NS33).
Regarding Claim 8, Kim, Jung, and Lee teach the limitations of Claim 1.
Kim further teaches the method of claim 1, further comprising:
responsive to determining that each memory cell of the set of vertically stacked memory cells is programmable, performing, using the default pass voltage (VPPASS1), the program operation on the set of vertically stacked memory cells (para 148; “The voltage generation circuit 700 may include the first voltage generator 705 and the second voltage generator 760 as described with reference to FIG. 4. The first voltage generator 705 may generate word-line voltages applied to the normal block or the partial normal region and the second voltage generator 760 may generate word-line voltages applied to the partial bad region PBRG.” Since the Normal region receives the same voltages as the partial normal region then it’s clear that a normal block with no bad cells would use the same “default” pass voltages).
Regarding Independent Claim 9, Kim teaches A system comprising:
a memory device (Fig. 2: 50); and
a processing device (Fig. 3: 41), operatively coupled (Fig. 3: 48, 47) to the memory device (Fig. 3: 50), the processing device (Fig. 3: 41) to perform operations comprising:
receiving a request to perform a program operation (Fig. 17: WL9 Program) on a block of the memory device (Fig. 2: 50), wherein the block is a set of vertically stacked memory cells (Fig. 7: NS11-NS33), wherein each memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is addressable (Fig. 2: ADDR) by a respective wordline (Fig. 7: WL1-WL12);
determining whether the block is a fully functional block (para 43 “The ECC engine 42 may designate a memory block as a bad block, based on uncorrectable errors in data read from the nonvolatile memory device 50.)”;
responsive to determining that the block is not a fully functional block, determining which memory cell of the set of vertically stacked memory cells of the block is non-programmable (para 45 “The memory controller 40 may include a repair manage module 43b that uses a portion of the bad block as a partial normal region based on the error information. The repair manage module 43b may control the nonvolatile memory device 50 to perform a repair operation that uses the portion of the bad block as a partial normal region by referring to the error information stored in the bad block information register 49”);
responsive to determining that at least one memory cell of the set of vertically stacked memory cells (Fig. 15: MC1-MC12) is non-programmable (Fig. 15: BR), determining a pass voltage adjustment value;
adjusting a default pass voltage (Fig. 17: VPPASS1) by the pass voltage adjustment value to generate an adjusted pass voltage (Fig. 17: VPPASS2); and
performing, using the adjusted pass voltage (Fig. 17: VPPASS2), the program operation (Fig. 17: WL9 PROGRAM) on the set of vertically stacked memory cells (Fig. 7: NS11-NS33).
Kim further teaches wherein the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is a block (Fig. 7: BLKi) of the memory device (Fig. 2: 50).
Kim further teaches at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at “a top” (see Kim Fig. 15: memory cell at WL12, next to SST1) of the set of vertically stacked memory cells. It is also noted that Kim’s disclosure is applicable to marking regions of a block as “normal” and “bad,” instead of marking the entire block as bad (see Kim Fig. 15: normal region PNRG and bad region PBRG). As such, Kim’s disclosure embraces scenarios and would have been understood by those having ordinary skill in the NAND flash memory art as intended to designate bad cells, at any location in the block (including cells at the “top” of the vertical NAND string), so as to salvage useable cells in a block instead of marking a block with useable memory cells entirely bad.
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Lee teaches a method of adjusting the pass voltages based on the number of program erase cycles performed (Fig. 21: S530a).
And applying the adjusted pass voltage during a program verify operation (Fig. 21: S530a) of the memory cell of, the set of vertically stacked memory cells (Fig. 5: NS1)
It would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lee and Jung to the teachings of Kim to create a memory device where the pass voltage used in the program verify operation is adjusted based on both the presence of a non-programmable cell within a vertical stack of memory cells and the number of program erase cycles the cells have undergone and their logical states.
Regarding Claim 10, Kim, Jung, and Lee teach the limitations of Claim 9. Claim 10 is rejected for the same reasons as Claim 2.
Regarding Claim 12, Kim, Jung, and Lee teach the limitations of Claim 9. Claim 12 is rejected for the same reasons as Claim 4.
Regarding Claim 15, Kim, Jung, and Lee teach the limitations of Claim 9. Claim 15 is rejected for the same reasons as Claim 7.
Regarding Claim 16, Kim, Jung, and Lee teach the limitations of Claim 9. Claim 16 is rejected for the same reasons as Claim 8.
Regarding Independent Claim 17, Kim teaches a non-transitory computer readable storage medium (Fig. 2: 50) including instructions (para 48; “The processor 41 controls an overall operation of the memory controller 40. In example embodiments, the processor 41 may execute instructions stored in, for example the buffer”) that, when executed by a processing device (Fig. 3: 41), cause the processing device to perform a method comprising:
receiving a request to perform a program operation (Fig. 17: WL9 PROGRAM) on a first block (Fig. 15: BB) of a memory device, wherein the block includes a non-programmable top deck (Fig. 15: PBRG) and a programmable bottom deck (Fig. 15: PNRG); and
performing, using an adjusted pass voltage (Fig. 17: VPPASS2), the program operation on the first block (Fig. 15: BB).
Kim further teaches wherein the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is a block (Fig. 7: BLKi) of the memory device (Fig. 2: 50).
Kim further teaches at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at “a top” (see Kim Fig. 15: memory cell at WL12, next to SST1) of the set of vertically stacked memory cells. It is also noted that Kim’s disclosure is applicable to marking regions of a block as “normal” and “bad,” instead of marking the entire block as bad (see Kim Fig. 15: normal region PNRG and bad region PBRG). As such, Kim’s disclosure embraces scenarios and would have been understood by those having ordinary skill in the NAND flash memory art as intended to designate bad cells, at any location in the block (including cells at the “top” of the vertical NAND string), so as to salvage useable cells in a block instead of marking a block with useable memory cells entirely bad.
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Lee teaches a method of adjusting the pass voltages based on the number of program erase cycles performed (Fig. 21: S530a).
And applying the adjusted pass voltage during a program verify operation (Fig. 21: S530a) of the memory cell of, the set of vertically stacked memory cells (Fig. 5: NS1)
It would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lee to the teachings of Kim to produce a memory device which adjusts pass voltages based on the presence of defective cells, the programmed state of a cell and the number of program erase cycles.
Regarding Claim 18, Kim, Lee and Jung teaches the limitations of Claim 17.
Lee further teaches a method of adjusting a pass voltage based on the number of program erase cycles (Fig. 21: S530a) and
Jung further teaches the logical state (Fig. 13: Vpass_E) of the cell from a plurality of adjustment values (Fig. 13: Vpass_E’).
Regarding Claim 19, Kim teaches the limitations of Claim 17. Kim further teaches wherein the processing device (Fig. 3: 41) to perform a method further comprising:
responsive to receiving a request to perform a read operation (Fig. 18: WL9 READ) on the first block (Fig. 15: BB), performing a read operation on the first block (Fig. 15: BB).
Regarding Claim 20, Kim, lee, and Jung teach the limitation of Claim 17. Kim further teaches wherein the processing device (Fig. 3: 41) to perform a method further comprising:
receiving a request to perform a program operation on a second block of the memory device, wherein the block includes a programmable top deck and a programmable bottom deck; and
performing, using a default pass voltage (Fig. 17: VPPASS1), the program operation on the second block (para 148; “The voltage generation circuit 700 may include the first voltage generator 705 and the second voltage generator 760 as described with reference to FIG. 4. The first voltage generator 705 may generate word-line voltages applied to the normal block or the partial normal region and the second voltage generator 760 may generate word-line voltages applied to the partial bad region PBRG.”).
Response to Arguments
Applicant’s arguments with respect to claim(s) June 4, 2026 have been considered but are moot because the new ground of rejection.
The combination of Kim, Lee and Jung represents an obvious combination of the art. Kim teaches adjusting pass values based on the presence of non-programmable cells in the block. And Lee and Jung disclose the well understood practice of adjusting pass voltages based on PEC cycles and the logic state of cells. Thus, combining them would be obvious when attempting to optimize the operation of a non-volatile memory such as the one disclosed.
Further applicant makes a distinction of Top vs Bottom in the stack, but performing these operations on cells based on non-programmable cells in the top of the stack vs the bottom represent obvious variants. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
