DETAILED ACTION
This action is responsive to the following: The amendments, arguments made after non-final rejection, and information disclosure statement filed on November 21, 2025. And the Information Disclosure statement filed on August 26, 2025.
Claims 1-20 are pending. Claims 1, 9, 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on August 26, 2025 and November 25, 2025 were filed after the mailing date of the Non-final office Action on August 26, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendments filed on November 21, 2025 has been entered. Claims 1-20 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-2, 4-10, 12-16 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190198514) in view of Dong (US 20100329010) and Jung (US 20200381061).
Regarding Independent Claim 1, Kim teaches a method comprising:
receiving a request to perform a program operation (Fig. 17: WL9 PROGRAM) on a set of vertically stacked memory cells (Fig. 7: NS11-NS33) of a memory device (Fig. 7: BLKi), wherein each memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells is addressable (Fig. 2: ADDR) by a respective wordline (Fig. 7: WL1-WL12);
responsive to determining that at least one memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells is non-programmable (Fig. 15: BR), determining, a pass voltage adjustment value;
adjusting a default pass voltage (Fig. 17: VPPASS1); by the pass voltage adjustment value to generate an adjusted pass voltage (Fig. 17: VPPASS2); and
performing, using the adjusted pass voltage (Fig. 17: VPPASS2), the program operation (Fig. 17: WL9 PROGRAM) on the set of vertically stacked memory cells (Fig. 7: NS11-NS33).
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Dong teaches a method of adjusting the pass voltages based on the number of program erase cycles performed (Fig. 18: 1804).
Dong states “FIG. 15c depicts a graph showing read pass voltages for a word line WLn+1 for different states of a storage element on WLn, based on number of program-erase cycles. By applying these different read pass voltages on WLn+1, the net VTH shift on WLn can be minimized so that read errors are reduced.” Thus, it would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages when verifying or reading data.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Dong and Jung to the teachings of Kim to create a memory method of programming a memory device where the pass voltage used in the program verify operation is adjusted based on both the presence of a non-programmable cell within a vertical stack of memory cells and the number of program erase cycles the cells have undergone and their logical states.
Regarding Claim 2, Kim, Jung, and Dong teach the limitations of Claim 1. Kim further teaches wherein determining that at least one memory cell of the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is non-programmable (Fig. 15: BR) comprises:
identifying whether a wordline associated with the at least one memory cell of the set of vertically stacked memory cells is defective (para 44; “The memory controller 40 may include a bad block information register 49 that stores error information of the bad block. The memory controller 40 may store a first error information and a second error information in the bad block information register 49 as the error information. The first error information may be associated the uncorrectable errors of word-lines in the bad block”).
Regarding Claim 4, Kim, Jung, and Dong teach the limitations of Claim 1. Dong Further teaches wherein determining the pass voltage adjustment value further comprises:
for a given memory cell of the set of vertically stacked memory cells (Fig. 1a-1b: 100-106), identifying, from a plurality of entries in a pass voltage adjustment data structure (Fig. 15c: 1520-1538), an entry associated with a logical state of the given memory cell (Fig. 15b: 1510, 1512, 1514) and the number of PECs (Fig. 15c: # Program-erase cycles), the entry comprising the pass voltage adjustment value, wherein each entry of the plurality of entries (Fig. 15c: 1520-1538) comprises a respective pass voltage adjustment value associated with a different logical state and a respective number of PECs.
Regarding Claim 5, Kim, Jung, and Dong teach the limitations of Claim 1. Kim further teaches wherein the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is a block (Fig. 7: BLKi) of the memory device (Fig. 2: 50).
Regarding Claim 6, Kim, Jung, and Dong teach the limitations of Claim 1.
Kim further teaches at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at “a top” (see Kim Fig. 15: memory cell at WL12, next to SST1) of the set of vertically stacked memory cells. It is also noted that Kim’s disclosure is applicable to marking regions of a block as “normal” and “bad,” instead of marking the entire block as bad (see Kim Fig. 15: normal region PNRG and bad region PBRG). As such, Kim’s disclosure embraces scenarios and would have been understood by those having ordinary skill in the NAND flash memory art as intended to designate bad cells, at any location in the block (including cells at the “top” of the vertical NAND string), so as to salvage useable cells in a block instead of marking a block with useable memory cells entirely bad.
Regarding Claim 7, Kim, Jung, and Dong teach the limitations of Claim 1.
Kim further teaches the method of claim 1, further comprising:
performing a read operation (Fig. 18: WL9 Read) on the set of vertically stacked memory cells (Fig. 7: NS11-NS33).
Regarding Claim 8, Kim, Jung, and Dong teach the limitations of Claim 1.
Kim further teaches the method of claim 1, further comprising:
responsive to determining that each memory cell of the set of vertically stacked memory cells is programmable, performing, using the default pass voltage (VPPASS1), the program operation on the set of vertically stacked memory cells (para 148; “The voltage generation circuit 700 may include the first voltage generator 705 and the second voltage generator 760 as described with reference to FIG. 4. The first voltage generator 705 may generate word-line voltages applied to the normal block or the partial normal region and the second voltage generator 760 may generate word-line voltages applied to the partial bad region PBRG.” Since the Normal region receives the same voltages as the partial normal region then it’s clear that a normal block with no bad cells would use the same “default” pass voltages).
Regarding Independent Claim 9, Kim teaches A system comprising:
a memory device (Fig. 2: 50); and
a processing device (Fig. 3: 41), operatively coupled (Fig. 3: 48, 47) to the memory device (Fig. 3: 50), the processing device (Fig. 3: 41) to perform operations comprising:
receiving a request to perform a program operation (Fig. 17: WL9 Program) on a set of vertically stacked memory cells (Fig. 7: NS11-NS33) of a memory device (Fig. 2: 50), wherein each memory cell (Fig. 7: MC1-MC12) of the set of vertically stacked memory cells (Fig. 7: NS11-NS33) is addressable (Fig. 2: ADDR) by a respective wordline (Fig. 7: WL1-WL12);
responsive to determining that at least one memory cell of the set of vertically stacked memory cells (Fig. 15: MC1-MC12) is non-programmable (Fig. 15: BR), determining a pass voltage adjustment value;
adjusting a default pass voltage (Fig. 17: VPPASS1) by the pass voltage adjustment value to generate an adjusted pass voltage (Fig. 17: VPPASS2); and
performing, using the adjusted pass voltage (Fig. 17: VPPASS2), the program operation (Fig. 17: WL9 PROGRAM) on the set of vertically stacked memory cells (Fig. 7: NS11-NS33).
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Dong teaches a method of adjusting the pass voltages based on the number of program erase cycles performed.
Dong states “ FIG. 15c depicts a graph showing read pass voltages for a word line WLn+1 for different states of a storage element on WLn, based on number of program-erase cycles. By applying these different read pass voltages on WLn+1, the net VTH shift on WLn can be minimized so that read errors are reduced.” Thus, it would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages when verifying or reading data.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Dong and Jung to the teachings of Kim to create a memory device where the pass voltage used in the program verify operation is adjusted based on both the presence of a non-programmable cell within a vertical stack of memory cells and the number of program erase cycles the cells have undergone and their logical states.
Regarding Claim 10, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 10 is rejected for the same reasons as Claim 2.
Regarding Claim 12, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 12 is rejected for the same reasons as Claim 4.
Regarding Claim 13, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 13 is rejected for the same reasons as Claim 5.
Regarding Claim 14, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 12 is rejected for the same reasons as Claim 6.
Regarding Claim 15, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 15 is rejected for the same reasons as Claim 7.
Regarding Claim 16, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 16 is rejected for the same reasons as Claim 8.
Regarding Independent Claim 17, Kim teaches a non-transitory computer readable storage medium (Fig. 2: 50) including instructions (para 48; “The processor 41 controls an overall operation of the memory controller 40. In example embodiments, the processor 41 may execute instructions stored in, for example the buffer”) that, when executed by a processing device (Fig. 3: 41), cause the processing device to perform a method comprising:
receiving a request to perform a program operation (Fig. 17: WL9 PROGRAM) on a first block (Fig. 15: BB) of a memory device, wherein the block includes a non-programmable top deck (Fig. 15: PBRG) and a programmable bottom deck (Fig. 15: PNRG); and
performing, using an adjusted pass voltage (Fig. 17: VPPASS2), the program operation on the first block (Fig. 15: BB).
Kim fails to teach adjusting a pass voltage based on the number of program erase cycles performed and a logical state of at least one programmable memory cell of a set of vertically stacked memory cells.
Dong teaches a method of adjusting the pass voltages based on the number of program erase cycles performed (Fig. 18: 1804).
Dong states “FIG. 15c depicts a graph showing read pass voltages for a word line WLn+1 for different states of a storage element on WLn, based on number of program-erase cycles. By applying these different read pass voltages on WLn+1, the net VTH shift on WLn can be minimized so that read errors are reduced.” Thus, it would be obvious to want to compensate for the effect of the threshold voltage shifts due to repeated program and erases within stacks of non-volatile memory devices by tracking the number of program erase cycles and adjusting pass voltages when verifying or reading data.
Jung teaches adjusting a pass voltage based a logical state (Fig. 12: VPASS_E, VPASS_P) of at least one programmable memory cell of a set of vertically stacked memory cells (Fig. 4: STR).
Jung states in paragraph 185 that there is a motivation to modify the voltage level of the memory cells when dealing with multi-level memory cells because using a single pass voltage for all cases requires a high voltage higher than the logical state with the largest threshold voltage. And thus, over biasing other cells not at that logic state can result in the threshold voltage increasing resulting in read disturbs. Its therefore advantageous to use pass voltages that are tailored to the logical state of the cells to which they’re being applied.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Dong to the teachings of Kim to produce a memory device which adjusts pass voltages based on the presence of defective cells, the programmed state of a cell and the number of program erase cycles.
Regarding Claim 18, Kim, Dong, teaches the limitations of Claim 17.
Dong further teaches a method of adjusting a pass voltage (Fig. 18: 1804) based on the number of program erase cycles (Fig. 18: 1802) and the logical state (Fig. 15b: 1510-1514) of the cell from a plurality of adjustment values (Fig. 15c: 1520-1538).
Regarding Claim 19, Kim teaches the limitations of Claim 17. Kim further teaches wherein the processing device (Fig. 3: 41) to perform a method further comprising:
responsive to receiving a request to perform a read operation (Fig. 18: WL9 READ) on the first block (Fig. 15: BB), performing a read operation on the first block (Fig. 15: BB).
Regarding Claim 20, Kim, Dong, and teaches the limitation of Claim 17. Kim further teaches wherein the processing device (Fig. 3: 41) to perform a method further comprising:
receiving a request to perform a program operation on a second block of the memory device, wherein the block includes a programmable top deck and a programmable bottom deck; and
performing, using a default pass voltage (Fig. 17: VPPASS1), the program operation on the second block (para 148; “The voltage generation circuit 700 may include the first voltage generator 705 and the second voltage generator 760 as described with reference to FIG. 4. The first voltage generator 705 may generate word-line voltages applied to the normal block or the partial normal region and the second voltage generator 760 may generate word-line voltages applied to the partial bad region PBRG.”).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190198514), Dong (US 20100329010), and Jung (US 20200381061) in view of Masuduzzaman et al (US 11139038).
Regarding Claim 3, Kim, Jung, and Dong teach the limitations of Claim 1. Kim, Jung, and Dong fail to teach applying an adjusted pass voltage during the verification step of the program verify operation.
Masuduzzaman teaches adjusting the pass voltage (Fig. 19: 1902) of cells adjacent to the selected cell for the purpose of performing verify operation after programming based on the logical state of adjacent cells.
Masuduzzaman states the purpose of adjusting the verify voltage is “predictively compensating for the deleterious effects of electrostatic coupling and electron diffusion to the programmed data.” Thus, it’s clear there is a benefit to compensating for shifts in threshold voltage that may occur within memory cells from various effects. Thus, it would be obvious to adjust the verify voltage for other effects that may impact the threshold voltage of cells such as the defective cells in a vertical stack of memory cells or number of program erase cycles the cell has undergone.
It would have therefore have been obvious to one of ordinary skill in the art to apply the teachings of Masuduzzaman to the teachings of Kim, Jung, and Dong to produce a memory device where during the verify operation the pass voltage applied to cells adjacent to the selected cell are adjusted based on the presence of a defective cell in the vertical stack of cells, the number of program erase cycles, and the logical state of the cell.
Regarding Claim 11, Kim, Jung, and Dong teach the limitations of Claim 9. Claim 11 is rejected for the same reasons as Claim 3.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection in view of amendments to the claims.
Applicants arguments are primarily directed to the rejections of independent claims 1, 9, and 17 and rely primarily on the addition of a limitation requiring that the adjustment to the pass voltage value be determined by the logical state of at least one programmable memory cell in a vertical stack of cells. And claim 17 had the limitation added that the pass voltage adjustment be based off of the number of Program erase cycles, which was already present in claims 1 and 9.
While applicant is correct that the amendment overcomes the previous 102(a)(1) rejection of Claim 17 under Kim et al (US 20190198514) it fails to overcome the obviousness rejection under the combination of references Kim, Dong et al (US 20100329010), and Jung (US 20200381061) for all three Claims.
Applicant also asserts that Kim is directed to a read operation and refers to Kim’s abstract. However, Figure 17 of Kim clearly shows an example of biasing during a program operation, which uses the adjusted pass voltages described in Kim’s disclosure. So regardless of what invention is claimed by this reference, Kim discloses adjusting the pass voltage during a program operation.
Applicant attempts to overcome the obviousness rejection under the combination of Kim and Dong but In response to applicant's arguments against the references individually, however one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Dong clearly teaches that adjusting a pass voltage based on the number of program erase cycles in figure 18. Therefore, the basis for obviousness in combining Kim and Dong is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825