DETAILED ACTION
This action is in response to the arguments and amendments filed on 11/21/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 8-10, 13-14, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saavedra et al. (US Patent 10095254) in view of Takemoto (US Patent 11552471). Regarding claims 1 and 18, Saavedra et al. discloses (see fig. 4) a computing device comprising: a voltage regulator (400) to control a current supplied to a hardware processor (400 output to loads 114), the voltage regulator comprising: a voltage regulator controller (120) to generate, based on a current supply request of the hardware processor (output from 438), a control signal to control a plurality of power stage circuits (output from 120 to power supplies 112), wherein the control signal indicates whether the voltage regulator is to operate in a single-phase mode or a multi-phase mode (operation of 120 activating or deactivating power supplies 112); the plurality of power stage circuits comprising a first power stage circuit (112-1) and a second power stage circuit (112-2/112-3-112/N), wherein a maximum output current of the first power stage circuit is lower than a maximum output current of the second power stage circuit (the maximum output current of 112-1 is less than the maximum output current of 112-2/112-3-112/N), and wherein: the first power stage circuit is to supply a first current to the hardware processor (output from 112-1 when activated) and the second power stage circuit is to not supply a second current to the hardware processor when the control signal indicates that the voltage regulator is to operate in the single-phase mode (when 112-1 is the only supply activated, 112-2/112-3-112/N does not supply an output current to the load); and the first power stage circuit is to supply the first current to the hardware processor and the second power stage circuit is to supply the second current to the hardware processor when the control signal indicates that the voltage regulator is to operate in the multi-phase mode (112-1 and 112-2/112-3-112/N being activated to output current to the loads); and the hardware processor to receive the first current, the second current, or the first current and the second current in response to the current supply request (loads receiving output current from 112-1 and 112-2/112-3-112/N individually or together). Saavedra et al. does not disclose that a power conversion efficiency of the first power stage circuit is higher than a power conversion efficiency of the second power stage circuit. Takemoto discloses (see fig. 1 and 5) that a power conversion efficiency of a first power stage circuit (16) is higher than a power conversion efficiency of a second power stage circuit (18). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to have modify the device of Saavedra et al. to include the features of Takemoto because it can provide for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 8, Saavedra et al. discloses (see fig. 4) when the current supply request indicates that a requested current of the hardware processor does not exceed a threshold current (output from 438 indicating that the required current does not require the activation of more power supplies), the voltage regulator controller (120) is to generate the control signal to indicate that the voltage regulator is to operate in the single-phase mode (output from 120 activating only 112-1). Regarding claim 9, Saavedra et al. discloses (see fig. 4) when the current supply request indicates that the requested current of the hardware processor exceeds the threshold current (output from 438 indicating that the required current does require the activation of more power supplies), the voltage regulator controller (120) is to generate the control signal to indicate that the voltage regulator is to operate in the multi-phase mode (output from 120 activating all of the power supplies). Regarding claim 10, Saavedra et al. discloses the claimed invention except for the threshold current being adjustable by the voltage regulator or a user of the computing device. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have the threshold current be adjustable by the voltage regulator or a user of the computing device, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Saavedra et al. to include the features of having the threshold current be adjustable by the voltage regulator or a user of the computing device, because it provides for a reduction in operational variances, which can increase operational efficiencies. Regarding claim 13, Saavedra et al. discloses the claimed invention except for a power conversion efficiency of the first power stage circuit being higher than a power conversion efficiency of the second power stage circuit. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have a power conversion efficiency of the first power stage circuit be higher than a power conversion efficiency of the second power stage circuit, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Saavedra et al. to include the features of having a power conversion efficiency of the first power stage circuit be higher than a power conversion efficiency of the second power stage circuit, because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies. Regarding claim 14, Saavedra et al. discloses (see fig. 4) Saavedra et al. discloses (see fig. 4) a computing device comprising: a voltage regulator (400) to control a current supplied to a hardware processor (400 output to loads 114), the voltage regulator comprising: a voltage regulator controller (120) to generate, based on a current supply request of the hardware processor (output from 438), a control signal to control a plurality of power stage circuits (output from 120 to power supplies 112), wherein the control signal indicates whether the voltage regulator is to operate in a single-phase mode or a multi-phase mode (operation of 120 activating or deactivating power supplies 112); the plurality of power stage circuits comprising a first power stage circuit (112-1) and a second power stage circuit (112-2/112-3-112/N), wherein a maximum output current of the first power stage circuit is lower than a maximum output current of the second power stage circuit (the maximum output current of 112-1 is less than the maximum output current of 112-2/112-3-112/N), and wherein: the first power stage circuit is to supply a first current to the hardware processor (output from 112-1 when activated) and the second power stage circuit is to not supply a second current to the hardware processor (when 112-1 is the only supply activated, 112-2/112-3-112/N does not supply an output current to the load) when the control signal indicates that a power consumption of the computing device is at a first level (load requirement indicates that only 112-1 is needed); and the first power stage circuit is to supply the first current to the hardware processor and the second power stage circuit is to supply the second current to the hardware processor (112-1 and 112-2/112-3-112/N being activated to output current to the loads) when the control signal indicates that the power consumption is at a second level higher than the first level (load requirement increases beyond the load requirement only needing current from 112-1). Saavedra et al. does not disclose that a power conversion efficiency of the first power stage circuit is higher than a power conversion efficiency of the second power stage circuit. Takemoto discloses (see fig. 1 and 5) that a power conversion efficiency of a first power stage circuit (16) is higher than a power conversion efficiency of a second power stage circuit (18). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to have modify the device of Saavedra et al. to include the features of Takemoto because it can provide for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 2, 11-12, 15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saavedra et al. (US Patent 10095254) in view of Takemoto (US Patent 11552471) and Chen et al. (US Patent 11381173). Regarding claims 2, 15, and 19, Saavedra et al. does not disclose that the control signal indicates that the voltage regulator is to operate in the multi-phase mode, the voltage regulator controller is to control the first current and the second current based on an amplified signal and a current sense signal. Chen et al. discloses (see fig. 4) that control signal (output from 337) indicates that a voltage regulator is to operate in a multi-phase mode (interleaving mode), the voltage regulator controller is to control a first current (output from 1st power stage) and a second current (output from 2nd and 3rd power stages) based on an amplified signal (output from 331) and a current sense signal (output from 333). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Saavedra et al. to include the features of Chen et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 11, Saavedra et al. does not disclose that the first power stage circuit includes a first inductor, a first power metal-oxide semiconductor field-effect transistor (MOSFET) and a second power MOSFET, and wherein the second power stage circuit includes a second inductor, a third power MOSFET and a fourth power MOSFET. Chen et al. discloses (see fig 10) that the first power stage circuit includes a first inductor, a first power metal-oxide semiconductor field-effect transistor (MOSFET) and a second power MOSFET, and wherein the second power stage circuit includes a second inductor, a third power MOSFET and a fourth power MOSFET (fig. 10 discloses different configuration for each power stage shown in fig. 4). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Saavedra et al. to include the features of Chen et al. because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies. Regarding claim 12, Saavedra et al. does not disclose that an inductance of the first inductor is higher than an inductance of the second inductor, and wherein a size of the first power MOSFET is smaller than a size of the third power MOSFET. Chen et al. discloses the claimed invention except for an inductance of the first inductor being higher than an inductance of the second inductor, and wherein a size of the first power MOSFET is smaller than a size of the third power MOSFET. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have an inductance of the first inductor be higher than an inductance of the second inductor, and wherein a size of the first power MOSFET is smaller than a size of the third power MOSFET, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Saavedra et al. to include the features of Chen et al. because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Allowable Subject Matter
Claims 3-7, 16-17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838