DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Objections
Claims 1, 4-7, 10-14, and 16-20 are objected to because of the following informalities:
As per claim 1, “each independent hypervisor”, ll 2 should be “each independent hypervisor from the plurality of independent hypervisors”.
As per claim 4, “independent hypervisor”, ll 2 should be “independent hypervisor from the plurality of independent hypervisors”.
As per claim 5, “at least independent hypervisor”, ll 1-2 should be “at least one independent hypervisor from the plurality of independent hypervisors”. “at least one independent hypervisor”, ll 2-3 should be “at least another one independent hypervisor from the plurality of independent hypervisors”.
As per claim 6, see objection on claim 5.
As per claim 7, “each of the plurality of independent hypervisors”, ll 1-2 should be “the each independent hypervisor”.
As per claim 10, “that”, ll 2 should be “the”.
As per claim 11, “a first independent hypervisor”, ll 2-3 should be “a first independent hypervisor from the plurality of independent hypervisors”. “a second independent hypervisor”, ll 4 should be “a second independent hypervisor from the plurality of independent hypervisors”.
As per claim 12, “a hypervisor”, ll 1 should be “the hypervisor from the plurality of independent hypervisors”. “a plurality of independent hypervisors”, ll 3-4 should be “the plurality of independent hypervisors”.
As per claim 13, “a hypervisor”, ll 1 should be “the hypervisor from the plurality of independent hypervisors”.
As per claim 14, “each independent hypervisor”, ll 2 should be “each independent hypervisor from the plurality of independent hypervisors”. “a respective independent hypervisor”, ll 4 should be “a respective independent hypervisor from the plurality of independent hypervisors”.
As per claim 16, “the plurality of independent hypervisors”, ll 3 should be “the plurality of concurrently executing independent hypervisors”. “a respective independent hypervisor”, ll 4 should be “a respective independent hypervisor from the plurality of concurrently executing independent hypervisors”.
As per claim 17, “the plurality of independent hypervisors”, ll 1-2 should be “the plurality of concurrently executing independent hypervisors.
As per claim 18, “one of the independent hypervisors”, ll 2 should be “one of the plurality of concurrently executing independent hypervisors”. “each independent hypervisor”, ll 3 should be “each independent hypervisor from the plurality of concurrently executing independent hypervisors”. “the same physical memory page”, ll 3 should be “a same physical memory page”. “the physical memory page”, ll 5 should be “the same physical memory page”.
As per claim 19, “a physical memory page”, ll 1 should be “a different physical memory page”. “that physical memory page”, ll 2 should be “the different physical memory page”.
As per claim 20, “The computer system”, ll 1 should be “The method”. “a hypervisor”, ll 1-2 should be “a hypervisor from the plurality of concurrently executing independent hypervisors”. “a first independent hypervisor”, ll 3 should be “a first independent hypervisor from the plurality of concurrently executing independent hypervisors”. “a second independent hypervisor”, ll 4 should be “a second independent hypervisor from the plurality of concurrently executing independent hypervisors”. “the same physical page”, ll 4-5 should be “a same physical page”.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 1-16 are rejected under 35 U.S.C. 101.
As per claim 1, “A computer system . . . a virtual machine configured to execute using a plurality of independent hypervisors” (under the broadest reasonable interpretation) can be SW per se. Virtual machine, and hypervisor are software constructs. Applicant is encouraged to claim a processor or memory to overcome this rejection.
As per claims 2-3, the claims do not add any hardware constructs and are therefore rejected for the reason set forth in claim 1.
As per claim 4, the claim recites a system, is therefore a machine.
The claim recites the limitation of “ . . . determine . . . “. This limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
“execute . . .” does not require any particular application of the recited “ . . . execute...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)). The claim is directed to the abstract idea.
As discussed above, “. . . execute . . . “ does not require any particular application of the recited “ . . . execute...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)). The claim is ineligible.
Furthermore, claim 4 does not add any hardware constructs and is therefore rejected for the reason set forth in claim 1.
As per claims 5-15, the claims do not add any hardware constructs and are therefore rejected for the reason set forth in claim 1.
As per claim 16, the claim recites a series of steps, therefore is a process.
The claim recites the limitation of “selecting, by the virtual machine, a respective independent hypervisor to provide different functions to the virtual machine”. This limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The limitation of “providing a plurality of concurrently executing independent hypervisors”, amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim also recites the additional element, "executing a virtual machine on the plurality of independent hypervisors", does not require any particular application of the recited “execute...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)). The claim is directed to the abstract idea.
As discussed above, “providing a plurality of concurrently executing independent hypervisors” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g)). "executing a virtual machine on the plurality of independent hypervisors", does not require any particular application of the recited “execute...” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. (see MPEP 2106.05(f)) The claim is ineligible.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 14 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 14, it is not clear where written description for “each independent hypervisor communicating using a common network interface having a common network address” exists. The spec lacks a discussion on this limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Applicant Admitted Prior Art (Background, Spec) (hereinafter AAPA).
As per claim 1, AAPA teaches:
A computer system, comprising a
virtual machine configured to execute using a plurality of independent hypervisors, each independent hypervisor providing different functions to the virtual machine (AAPA, pg 2 ll 7-8—under BRI, different functions can be an intrusion detection service, a deduplication service, and/or a real-time CPU or I/O scheduling service.).
As per claim 2, AAPA teaches:
The computer system according to claim 1 (see rejection on claim 1), wherein the plurality of independent hypervisors provide alternate implementations of functions for the virtual machine (AAPA, pg 2, ll 7-8—under BRI, alternate implementations of functions can be different implementations of specialized hypervisor-level services).
As per claim 3, AAPA teaches:
The computer system according to claim 1 (see rejection on claim 1), wherein the plurality of independent hypervisors provide different functions for the virtual machine (AAPA, pg 2 ll 7-8).
As per claim 4, AAPA teaches:
The computer system according to claim 1 (See rejection on claim 1), wherein the virtual machine is configured to determine which independent hypervisor to use (AAPA, pg 2, ll 5).
As per claim 5, AAPA teaches:
The computer system according to claim 1 (see rejection on claim 1), wherein at least independent hypervisor selectively provides an intrusion detection service, and at least one independent hypervisor does not provide an intrusion detection service (AAPA, pg 2 ll 7-8).
As per claim 16, AAPA teaches:
A method of operating a computer system, comprising:
providing a plurality of concurrently executing independent hypervisors(AAPA, pg 2, ll 7-8); executing a virtual machine on the plurality of independent hypervisors (AAPA, pg 2 ll 4);
selecting, by the virtual machine, a respective independent hypervisor to provide different functions to the virtual machine (AAPA, pg 2, ll 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of LUTAS et al (US 2015/0379265) (hereinafter LUTAS).
As per claim 6, AAPA teaches:
The computer system according to claim 1(see rejection on claim 1), at least one independent hypervisor does not provide a virtual machine introspection service (AAPA, pg 2 ll 7-8).
AAPA does not expressly teach:
wherein at least independent hypervisor selectively provides a virtual machine introspection service;
However, LUTAS discloses:
wherein at least independent hypervisor selectively provides a virtual machine introspection service (LUTAS, [0049]);
Both LUTAS and AAPA pertain to the art of virtualization technology.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use LUTAS’ method to provide a virtual machine introspection service because it is well-known in the art that introspection service offers several benefits for virtualized environments including reduced resource consumption.
Claims 7-9, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Anderson et al (US 2006/0130060) (hereinafter Anderson).
As per claim 7, AAPA teaches:
The computer system according to claim (see rejection on claim 1).
AAPA does not expressly teach:
wherein each of the plurality of independent hypervisors instantiate their respective virtual machine association by setting aside corresponding memory pages in their respective gust physical address space for the respective virtual machine.
However, Anderson discloses:
wherein each of the plurality of independent hypervisors instantiate their respective virtual machine association by setting aside corresponding memory pages in their respective gust physical address space for the respective virtual machine (Anderson, [0051])
Both Anderson and AAPA pertain to the art of virtualization technology.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Anderson’s method to assign memory pages because it is well-known in the art that virtualizing memory gives the appearance of a large, continuous block of memory to applications although the physical memory (RAM) is limited.
As per claim 8, AAPA teaches:
The computer system according to claim 1(see rejection on claim 1), wherein independent controller are hypervisors (AAPA, pg 2 ll 7-8);
AAPA does not expressly teach:
wherein one of the independent controllers is configured to coordinate memory usage, and ensures at runtime of the virtual machine that the respective guest address for each independent hypervisor is mapped to the same physical memory page.
However, Anderson discloses:
wherein one of the controllers is configured to coordinate memory usage (Anderson, [0051]), and ensures at runtime of the virtual machine that the respective guest address for each independent hypervisor is mapped to the same physical memory page (Anderson, [0051]).
Both Anderson and AAPA pertain to the art of virtualization technology.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Anderson’s method to assign memory pages because it is well-known in the art that virtualizing memory gives the appearance of a large, continuous block of memory to applications although the physical memory (RAM) is limited.
As per claim 9, AAPA/Anderson teaches:
The computer system according to claim 8 (See rejection on claim 8), wherein the mapping to the same physical memory page does not consume physical memory absent a write to the physical memory page (Anderson, [0051]—under BRI, the same physical memory page does not consume physical memory absent a write to the physical memory page can be “not accessing page when the page is not assigned [absent a write]”).
As per claim 17, see rejection on claim 7.
As per claim 18, see rejection on claims 8 and 9.
As per claim 19, AAPA/Anderson teaches:
The method according to claim 18 (See rejection claim 18), further comprising consuming a physical memory page when a first time write mapped to that physical memory page triggers a page fault (NOT REQUIRED: the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met [when, whenever, and if are synonyms]).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Yogen et al (Dalal, Yogen K., and Robert M. Metcalfe. "Reverse path forwarding of broadcast packets." Communications of the ACM 21.12 (1978): 1040-1048.) (hereinafter Yogen) further in view of Chadwell et al ( US 2015/0081893) (hereinafter Chadwell).
As per claim 14, AAPA teaches:
A computer system, comprising a virtual machine configured to execute using a plurality of independent hypervisors (AAPA, pg 2, ll 7-8—under BRI, a plurality of independent hypervisors can be L1 hypervisors), wherein a destination is a respective independent hypervisor (AAPA, pg 2, ll 7-8).
AAPA does no expressly teach:
each independent hypervisor communicating using a common network interface having a common network address, further comprising delivering a packet received through the common network interface to the destination based on a reverse learning algorithm dependent on prior outgoing packets from the destination.
However, Yogen discloses:
delivering a packet received through an interface to the destination based on a reverse learning algorithm dependent on prior outgoing packets from the destination (Yogen, pg 1043, 4. Reverse Path Forwarding Algorithm)
Both Yogen and AAPA pertain to the art of networking.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Yogen’s reverse learning algorithm because it is well-known in the art that the reverse learning algorithm in networking offers several benefits, particularly in the context of deep learning and reverse engineering.
AAPA/Yogen does not expressly teach:
each independent hypervisor communicating using a common network interface having a common network address;
wherein the interface is the common network interface;
However, Chadwell discloses:
each independent hypervisor communicating using a common network interface having a common network address (Chadwell, [0125]—under BRI, a common network interface having a common network address can be “an ethernet interface with ethernet address [common can be familiar]);
wherein the interface is the common network interface (Chadwell, [0125]);
Both Chadwell and AAPA/Yogen pertain to the art of networking.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Chadwell’s common (familiar) interface because it is well-known in the art that ethernet offers several benefits including high reliability.
As per claim 15, AAPA/Yogen/Chadwell teaches:
The computer system according to claim 14 (see rejection on claim 14) , further comprising a reverse learning gateway (Yogen, pg 1043, 4. Reverse Path Forwarding Algorithm), wherein the gateway is a hypervisor(AAPA, pg 2, ll 7-8), configured to conduct all outgoing communications packets and distribute inbound communications packets to a destination (Yogen, pg 1043, 4. Reverse Path Forwarding Algorithm ), wherein the destination respective independent hypervisors (AAPA, pg 2, ll 7-8).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2011/0270899 teaches a method of assigning memory pages by a hypervisor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198