DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Currently, claims 1,3-9 & 11-16 are pending in the application. No amendment or cancellation.
Continued Examination Under 37 CFR 1.114 1.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Response to Arguments / Amendments
Applicant’s arguments have been fully considered, but they are not persuasive, see discussion below.
Rejections under 35 U.S.C. § 103:
I. The applicant argues that Jeon fails to disclose the technical feature "to mix the intermediate image and a buffered image according to the reference data to generate a pre-mixed image." & “wherein the buffered image includes a second frame corresponding to the second bitstream”
As to the above argument Jeon discloses generate & store intermediate image based on at least the first frame performing decoding a base layer and an enhancement layer of the bit stream received from the photographing apparatus and mixing the intermediate image and a buffered image according to the reference data by stitching boundaries of the omnidirectional image obtained by dividing and photographing an object and connect boundaries of the image obtained by dividing and photographing an object to generate a two-dimensional planar omnidirectional image ([0060] FIG. 1).
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II. The applicant argues that LAROCHE fails to disclose the technical feature "a computing circuit coupled to the decoding circuit and configured to generate a reference data."
As to the above argument, LAROCHE teaches generating a reference data or a reference image from among a set of reference images 416 is selected, and a portion of the reference image, also called reference area or image portion ([0113], FIG. 4).
LAROCHE also teaches reference image portion is extracted from a reference image 68 ([0124], FIG. 5)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20180091821, hereinafter Jeon) in view of LAROCHE et al. (US 20250071333, hereinafter LAROCHE) and Guruva reddiar et al. (US 20220109838, hereinafter Guruva reddiar).
Regarding Claim 1, Jeon in view of LAROCHE discloses an image processing device ([0030] FIG. 1, image processing system), wherein the image processing device is coupled to a storage circuit and configured to receive a video data, and the video data comprises a first bitstream ([0049] FIG. 1, camera 111 consecutively captures an image to capture a video image) and a second bitstream ([0054] FIG. 1, second camera device 120 captures a video image), the image processing device comprising:
a decoding circuit configured to decode the first bitstream to generate a first frame ([0060] FIG. 1, decoder 220 decode the encoded video image according to SVC to generate a video image);
a frame composer coupled to the decoding circuit and configured to generate an intermediate image based on at least the first frame and to store the intermediate image in the storage circuit ([0060] FIG. 1, decode a base layer and an enhancement layer of the bit stream received from the photographing apparatus 100 to generate a video image); and
an image pre-mixer coupled to the storage circuit and configured to mix the intermediate image and a buffered image according to the reference data to generate a pre-mixed image wherein the buffered image includes a second frame corresponding to the second bitstream ([0062] FIG. 1, image processor 230 stitch boundaries of the omnidirectional image obtained by dividing and photographing an object and connect boundaries of the image obtained by dividing and photographing an object to generate a two-dimensional planar omnidirectional image);
wherein the buffered image has already been stored in the storage circuit ([0062] FIG. 1; [0125], encoder decoder, image processor, and/or the controller are implemented by one or more microprocessors and/or integrated circuits executing instructions stored in computer-readable media)
Jeon does not explicitly disclose a computing circuit coupled to the decoding circuit and configured to generate a reference data.
LAROCHE teaches a computing circuit coupled to the decoding circuit and configured to generate a reference data ([0113], FIG. 4, a reference image from among a set of reference images 416 is selected, and a portion of the reference image, also called reference area or image portion; [0124], FIG. 5, reference image portion is extracted from a reference image 68)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of generating a reference data as taught by LAROCHE ([0113]) into the encoding & decoding system of Jeon in order to provide systems for an improvement to the high level syntax structure, which leads to a reduction in complexity and/or signaling without any significant degradation in coding performance and in-loop mapping of the Luma component adjusts the dynamic range of the input signal by redistributing the codewords across the dynamic range to improve compression efficiency (LAROCHE, [0005]).
In addition to Jeon, Guruva reddiar teaches storing the buffered image ([0056], FIG. 5, a buffer pool 502 that stores a dynamic buffer of intra-frame data and inter-frame data (e.g., updated intra-frame data) with a video display controller circuitry 324 that includes video postprocessor circuitry; [0063], video display controller circuitry 324 generates video signals corresponding to the pixel (previously stored) data retrieved from the buffer pool 502 and video postprocessor circuitry 504 down samples and/or reduces a frame rate of the video frame pixel data to generate processed video frame(s)).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of generating a reference data as taught by Guruva reddiar ([0056]) into the encoding & decoding system of Jeon & LAROCHE in order to provide systems for utilizing a video frame segmentation module to analyze the video frame pixel data to identify the pixels of interest in the video frames, so that the segmentation can be performed efficiently (Guruva reddiar, [0140]).
Regarding Claim 3, Jeon in view of LAROCHE and Guruva reddiar discloses the image processing device of claim 2, Jeon discloses wherein one operation round comprises decoding the video data and generating the intermediate image and the pre-mixed image ([0117]-[0123], FIG. 8), and LAROCHE discloses the computing circuit generates the reference data according to whether the decoding circuit generates a frame of the first bitstream in an operation round and whether the decoding circuit generates a frame of the second bitstream in the operation round ([0113], FIG. 4, a reference image from among a set of reference images 416 is selected, and a portion of the reference image, also called reference area or image portion; [0124], FIG. 5, reference image portion is extracted from a reference image 68). The same reason or rational of obviousness motivation applied as used above in claim 1.
Regarding Claim 4, Jeon in view of LAROCHE and Guruva reddiar discloses the image processing device of claim 2, LAROCHE discloses wherein the buffered image further comprises a third frame corresponding to the first bitstream, when the reference data indicates that the intermediate image does not comprise a frame corresponding to the second bitstream, the image pre-mixer generates the pre-mixed image based on at least the first frame and the second frame, so that the pre-mixed image comprises the first frame and the second frame but does not comprise the third frame ([0113], FIG. 4, a reference image from among a set of reference images 416 is selected, and a portion of the reference image, also called reference area or image portion; [0124], FIG. 5, reference image portion is extracted from a reference image 68). The same reason or rational of obviousness motivation applied as used above in claim 1.
Regarding Claim 5, Jeon in view of LAROCHE and Guruva reddiar discloses the image processing device of claim 2, Jeon discloses wherein one operation round comprises decoding the video data and generating the intermediate image and the pre-mixed image, and the image pre-mixer further stores the pre-mixed image in the storage circuit and in a next operation round reads the pre-mixed image from the storage circuit as the buffered image ([0062] FIG. 1, image processor 230 stitch boundaries of omnidirectional image obtained by dividing and photographing an object and connect boundaries of the image obtained by dividing and photographing an object to generate a two-dimensional planar omnidirectional image).
Regarding Claim 6, Jeon in view of LAROCHE and Guruva reddiar discloses the image processing device of claim 5, Jeon discloses wherein the image pre-mixer comprises a run-length codec configured to encode the pre-mixed image before storing the pre-mixed image in the storage circuit and to decode the buffered image ([0114], FIGS. 1 to 7, when receiving and processing a video image captured by a plurality of camera devices, the image processing apparatus 200 encode the video image according to SVC and decode only an enhancement layer of a bit stream selected by the user so as to simultaneously process a plurality of bit streams and, when the user selects a desired video image, the image processing apparatus 200 may rapidly display the selected video image on a display)
Regarding Claim 7, Jeon in view of LAROCHE and Guruva reddiar discloses the image processing device of claim 2, Jeon discloses further comprising: a scaling circuit coupled to the decoding circuit and configured to adjust a size of the first frame; wherein the second frame contained in the buffered image is a frame adjusted by the scaling circuit ([0114], FIGS. 1 to 7, when receiving and processing a video image captured by a plurality of camera devices, the image processing apparatus 200 encode the video image according to SVC and decode only an enhancement layer of a bit stream selected by the user so as to simultaneously process a plurality of bit streams and, when the user selects a desired video image, the image processing apparatus 200 may rapidly display the selected video image on a display).
Regarding Claims 9 &11-15, Analogous rejection as the rejection of Claims 1 & 3-7 applies. Method claims 9 and 11-15 of using the corresponding image processing device claimed in claims 1 and 3-7, and the rejections of which are incorporated herein for the same reasons as used above.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20180091821, hereinafter Jeon) in view of LAROCHE et al. (US 20250071333, hereinafter LAROCHE), Guruva reddiar and Ma et al. (US 20070285500, hereinafter Ma)
Regarding Claim 8, Jeon in view of LAROCHE discloses the image processing device of claim 1, but does not explicitly disclose wherein a frame rate of the first bitstream is different from a frame rate of the pre-mixed image.
Ma teaches a frame rate of the first bitstream is different from a frame rate of the pre-mixed image ([0110], handle different frame rates, or differing frame arrival rates for multiple video inputs. One of efficient approaches to handle different frame rate is to keep the output mixed frame rate same as the one which has highest frame rate among all the input frame rates (i.e., 30 fps for the given example)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of handle different frame rates as taught by Ma ([0110]) into the encoding & decoding system of Jeon & LAROCHE in order to provide systems for an improvement of computation cost , quality of output mixed video stream by predicting the motion data for mixed output macroblocks in compressed video parameter domain and reducing processing delay are reduced. Memory usage is reduced and fluctuation in bandwidth of mixed video bit stream is reduced (Ma, [0010]).
Regarding Claim 16, Analogous rejection as the rejection of Claim 8 applies. Method claim 16 of using the corresponding image processing device claimed in claim 8, and the rejections of which are incorporated herein for the same reasons as used above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Samuel D Fereja whose telephone number is (469)295-9243. The examiner can normally be reached 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVID CZEKAJ can be reached at (571) 272-7327. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL D FEREJA/Primary Examiner, Art Unit 2487