DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/12/2026, in which claims 1, 3, 5, 6, 8, 10, 12, 13 were amended, has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of “wherein a sidewall of the second portion of the dielectric gate cut structure directly contacts both a sidewall of portion of a backside contact structure and a sidewall of a shallow trench isolation region” of claim 6 and “wherein a first sidewall of the second portion of the self-aligned gate cut structure directly contacts a first sidewall of a backside contact structure and wherein a first sidewall of a shallow trench isolation region directly contacts the first sidewall of the second portion of the self-aligned gate cut structure” of claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: claim 6 recites the limitation “a sidewall of the second portion of the dielectric gate cut structure directly contacts both a sidewall of portion of a backside contact structure and a sidewall of a shallow trench isolation region” and claim 13 recites the limitation “wherein a first sidewall of the second portion of the self-aligned gate cut structure directly contacts a first sidewall of a backside contact structure, wherein a first sidewall of a shallow trench isolation region directly contacts the first sidewall of the second portion of the self-aligned gate cut structure”. However, the specification does not describe the above claimed subject matter.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6 and 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 6 and 13, claim 6 recites the limitation “a sidewall of the second portion of the dielectric gate cut structure directly contacts both a sidewall of portion of a backside contact structure and a sidewall of a shallow trench isolation region” and claim 13 recites the limitation “wherein a first sidewall of the second portion of the self-aligned gate cut structure directly contacts a first sidewall of a backside contact structure, wherein a first sidewall of a shallow trench isolation region directly contacts the first sidewall of the second portion of the self-aligned gate cut structure”. However, the specification does not describe the above claimed subject matter and the drawings do not show above claimed subject matter. Accordingly, claims 6 and 13 were not in possession of Applicant at the time of filing.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Applicant is remined that MPEP 2163 (I)(B) requires “newly added claims or claim limitations must be supported in the specification through express, implicit, or inherent disclosure” thus, applicant should show support in the original disclosure for the new or amended claims. See, e.g., Hyatt v. Dudas, 492 F.3d 1365, 1370, n.4 (Fed. Cir. 2007) (citing MPEP § 2163.04 which provides that a "simple statement such as ‘applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim limitation’ ‘in the application as filed’ may be sufficient where the claim is a new or amended claim, the support for the limitation is not apparent, and applicant has not pointed out where the limitation is supported."); see also MPEP §§ 714.02 and 2163.06 ("Applicant should ... specifically point out the support for any amendments made to the disclosure."); and MPEP § 2163.04 (“If applicant amends the claims and points out where and/or how the originally filed disclosure supports the amendment(s), and the examiner finds that the disclosure does not reasonably convey that the inventor had possession of the subject matter of the amendment at the time of the filing of the application, the examiner has the initial burden of presenting evidence or reasoning to explain why persons skilled in the art would not recognize in the disclosure a description of the invention defined by the claims.").
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, claim 8 recites “a first nanosheet stack surrounded by a first gate; a second nanosheet stack surrounded by a second gate; and a self-aligned gate cut structure between and electrically isolating a first gate associated with the first nanosheet stack and a second gate associated with the second nanosheet stack.” It is unclear “a first gate” and “a second gate” recited in the limitation “a self-aligned gate cut structure between and electrically isolating a first gate associated with the first nanosheet stack and a second gate associated with the second nanosheet stack” is the same or different from “a first gate” and “a second gate” surrounding a first nanosheet stack and a second nanosheet stack.
For the purpose of this Action, the above limitation “a self-aligned gate cut structure between and electrically isolating a first gate associated with the first nanosheet stack and a second gate associated with the second nanosheet stack” of claim 8 will be interpreted and examined as--a self-aligned gate cut structure between and electrically isolating the first gate associated with the first nanosheet stack and the second gate associated with the second nanosheet stack--.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 20240304704) in view of Min et al. (US Pub. 20230070925)
Regarding claim 1, Lee et al. discloses in Fig. 5, paragraph [0061]
a first nanosheet transistor device;
a second nanosheet transistor device;
a dielectric gate cut structure [340U, 340L, 345] between and electrically isolating the first nanosheet transistor device from the second nanosheet transistor device;
a gate cut liner [341 and/or 342] along sidewalls of only a first portion [340U] of the dielectric gate cut structure [340U, 340L, 345], wherein a bottommost surface of the gate cut liner [341 and/or 342] is substantially flush with a bottommost surface of the first portion [340U] of the dielectric gate cut structure [340U, 340L, 345], and
wherein topmost surfaces of the gate cut liner [341 and/or 342] are substantially flush with topmost surface of the dielectric gate cut structure [340U, 340L, 345].
Lee et al. fails to disclose
the first portion of the dielectric gate cut structure comprises a positive tapered profile, and a second portion of the dielectric gate cut structure comprises a negative tapered profile.
Min et al. discloses in Fig. 3, Fig. 8, paragraph [0038], [0059]-[0060], [0069], [0103], [0105], [0137]-[0139],
wherein the first portion [160U] of the dielectric gate cut structure [160] comprises a positive tapered profile, and a second portion [160B] of the dielectric gate cut structure [160] comprises a negative tapered profile.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Min et al. into the method of Lee et al. to include the first portion of the dielectric gate cut structure comprises a positive tapered profile, and a second portion of the dielectric gate cut structure comprises a negative tapered profile. The ordinary artisan would have been motivated to modify Lee et al. in the above manner for the purpose of providing suitable alternative profile of the first and second portions of the dielectric gate cut structure that may improve performance and reliability [paragraph [0005], [0138]-[0139] of Min et al.].
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US Pub. 20200185266) in view of Lee et al. (US Pub. 20240304704)
Regarding claim 1, Zang et al. discloses in Fig. 1A, Fig. 1C, Fig. 5A
a first transistor device;
a second transistor device;
a dielectric gate cut structure [38, 28 and 34] between and electrically isolating the first transistor device from the second transistor device;
a second portion [34 and 38 within 34] of the dielectric gate cut structure [38, 28 and 34] comprises a negative tapered profile;
a gate cut liner [30] along sidewalls of only a first portion [28 and 38 within 28] of the dielectric gate cut structure [38, 28 and 34], wherein a bottommost surface of the gate cut liner [30] is substantially flush with a bottommost surface of the first portion [28 and 38 within 28] of the dielectric gate cut structure [38, 28 and 34], and
wherein topmost surfaces of the gate cut liner [30] are substantially flush with topmost surface of the dielectric gate cut structure [38, 28 and 34].
Zang et al. fails to disclose
the first transistor device comprises a first nanosheet transistor device;
the second transistor device comprises a second nanosheet transistor device;
the first portion of the dielectric gate cut structure comprises a positive tapered profile.
Lee et al. discloses in Fig. 5
the first transistor device comprises a first nanosheet transistor device;
the second transistor device comprises a second nanosheet transistor device;
the first portion of the dielectric gate cut structure [340 and 345] comprises a positive tapered profile.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Zang et al. to include the first transistor device comprises a first nanosheet transistor device; the second transistor device comprises a second nanosheet transistor device; the first portion of the dielectric gate cut structure comprises a positive tapered profile. The ordinary artisan would have been motivated to modify Zang et al. in the above manner for the purpose of providing suitable alternative profile of the first portion of the dielectric gate cut structure; providing nanosheet field-effect transistors to increase the integration degrees of integrated circuit devices and reduce the sizes of integrated circuit devices [paragraph [0003] of Lee et al.].
Regarding claim 8, Zang et al. discloses in Fig. 1A, Fig. 1C, Fig. 6A a semiconductor structure comprising:
a first gate [16, 44 and 42 on the left];
a second gate [16, 44 and 42 on the right];
a self-aligned gate cut structure [38, 28 and 34] between and electrically isolating the first gate [16, 44 and 42 on the left] and the second gate [16, 44 and 42 on the right],
wherein a second portion [34 and 38 within 34] of the dielectric gate cut structure [38, 28 and 34] comprises a negative tapered profile,
wherein the second portion of the self-aligned gate cut structure [38, 28 and 34] is entirely below both the first gate [16, 44 and 42 on the left] and the second gate [16, 44 and 42 on the right], and
wherein a topmost surface of a first portion of the self-aligned gate cut structure [38, 28 and 34] is substantially flush with topmost surfaces of both the first gate [16, 44 and 42 on the left] and the second gate [16, 44 and 42 on the right].
Zang et al. fails to disclose
a first nanosheet stack surrounded by the first gate;
a second nanosheet stack surrounded by the second gate;
the first gate associated with the first nanosheet stack and the second gate associated with the second nanosheet stack;
the first portion of the dielectric gate cut structure comprises a positive tapered profile.
Lee et al. discloses in Fig. 5
a first nanosheet stack surrounded by the first gate;
a second nanosheet stack surrounded by the second gate;
the first gate associated with the first nanosheet stack and the second gate associated with the second nanosheet stack;
the first portion of the dielectric gate cut structure [340 and 345] comprises a positive tapered profile.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Zang et al. to include a first nanosheet stack surrounded by the first gate; a second nanosheet stack surrounded by the second gate; the first gate associated with the first nanosheet stack and the second gate associated with the second nanosheet stack; the first portion of the dielectric gate cut structure comprises a positive tapered profile. The ordinary artisan would have been motivated to modify Zang et al. in the above manner for the purpose of providing suitable alternative profile of the first portion of the dielectric gate cut structure; providing nanosheet field-effect transistors to increase the integration degrees of integrated circuit devices and reduce the sizes of integrated circuit devices [paragraph [0003] of Lee et al.].
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US Pub. 20200185266) in view of Lee et al. (US Pub. 20240304704) as applied to claim 1 and claim 8 above and further in view of Jeon et al. (US Pub. 20190378903)
Regarding claims 2 and 9, Zang et al. and Lee et al. fails to disclose
an air gap embedded within the dielectric/self-aligned gate cut structure.
Jeon et al. discloses in Fig. 2,
an air gap [180] embedded within the dielectric/self-aligned gate cut structure [170].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Zang et al. and Lee et al. to include an air gap embedded within the dielectric/self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Zang et al. and Lee et al. in the above manner for the purpose of improve an insulation effect of the gate isolation layer [paragraph [0039] of Jeon et al.].
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US Pub. 20200185266) in view of Lee et al. (US Pub. 20240304704) as applied to claim 1 and claim 8 above and further in view of Su et al. (US Pub. 20220262915).
Regarding claims 4 and 11, Zang et al. discloses in Fig. 6B, paragraph [0033]
a source drain contacts [40/46] above and directly contacting a source drain region [20].
Zang et al. and Lee et al. fails to disclose
wherein the source drain contact extends laterally into the dielectric/ self-aligned gate cut structure.
Su et al. discloses in Fig. 12A-12B, 13A-B, 14A-B, 15A-B, paragraph [0024], [0035]-[0037]
wherein the source drain contact [260] extends laterally into the dielectric/ self-aligned gate cut structure [244-1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Su et al. into the method of Zang et al. and Lee et al. to include wherein the source drain contact extends laterally into the dielectric/ self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Zang et al. and Lee et al. in the above manner for the purpose of providing suitable configuration of source drain contact be connected to the source/drain patterns [Paragraph [0024] of SU et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 5, 7, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US Pub. 20200185266) in view of Lee et al. (US Pub. 20240304704) as applied to claim 1 and claim 8 above and further in view of Jeon et al. (US Pub. 20200381526)
Regarding claims 5 and 12, Zang et al. discloses in Fig. 5A, Fig. 6A
wherein the second portion [34 and 38 within 34] of the dielectric gate cut structure [38, 28 and 34] is embedded within a shallow trench isolation region [22] such that a topmost surface of the second portion [34 and 38 within 34] of the dielectric gate cut structure is substantially flush with a topmost surface of the shallow trench isolation region [22].
Zang et al. and Lee et al. fails to disclose
wherein the gate cut liner directly contacts a topmost surface of the second portion of the dielectric gate cut structure.
Jeon et al. discloses in Fig. 11, Fig. 19, paragraph [0138]
wherein the gate cut liner [80] directly contacts a topmost surface of the second portion [85E] of the dielectric gate cut structure [85].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Zang et al. and Lee et al. to include wherein the gate cut liner directly contacts a topmost surface of the second portion of the dielectric gate cut structure. The ordinary artisan would have been motivated to modify Zang et al. and Lee et al. in the above manner for the purpose of forming the dielectric gate cut structure having the second portion extending into the gate structures and overlapping the gate structures to prevent/reduce a leakage current or an electrical short between the gate structures [paragraph [0140] of Jeon et al.].
Regarding claims 7 and 14, Zang et al. and Lee et al. fails to discloses
wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than a smallest width of the first portion of the dielectric/self-aligned gate cut structure.
Jeon et al. discloses in Fig. 19, paragraph [0138]
wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than any width of the first portion of the dielectric/self-aligned gate cut structure.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Zang et al. and Lee et al. to include wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than any width of the first portion of the dielectric/self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Zang et al. and Lee et al. in the above manner for the purpose of forming the dielectric gate cut structure having the second portion extending into the gate structures and overlapping the gate structures to prevent/reduce a leakage current or an electrical short between the gate structures [paragraph [0140] of Jeon et al.].
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a smallest width of the second portion of the dielectric/self-aligned gate cut structure with respect to a smallest width of the first portion of the dielectric/self-aligned gate cut structure: a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than/is less than/is equal to a smallest width of the first portion of the dielectric/self-aligned gate cut structure. Absent unexpected results, it would have been obvious to try wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than a smallest width of the first portion of the dielectric/self-aligned gate cut structure to yield a suitable smallest width of the second portion of the dielectric/self-aligned gate cut structure with respect to a smallest width of the first portion of the dielectric/self-aligned gate cut structure with a reasonable expectation of success.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467)
Regarding claim 15, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0038], [0059]-[0060], [0069], [0103], [0105], [0137]-[0139], a semiconductor structure comprising:
first set of nanosheet channels [AP1] surrounded by a first gate structure [120];
second set of nanosheet channels [AP2] surrounded by a second gate structure [220];
a self-aligned gate cut structure between and electrically isolating the first gate structure [120] from the second gate structure [220].
Min et al. fails to disclose
wherein a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions.
However, Min et al. appears to discloses in Fig. 17 and Fig. 19 that a topmost surface of the second portion [160B] of the self-aligned gate cut structure [160] or a bottommost surface of the first portion [160U] of the self-aligned gate cut structure [160] can be varied.
Min et al. also discloses a topmost surface of the second portion [160B] of the self-aligned gate cut structure [160] and a bottommost surface of the first portion [160U] of the self-aligned gate cut structure are same level.
Kim discloses in Fig. 5
a topmost surface of the second portion [portion of 170 in the trench isolation regions 107b] of the self-aligned gate cut structure [170 and 180] a bottommost surface of the first portion [180] of the self-aligned gate cut structure [170 and 180] is substantially flush with topmost surfaces of adjacent shallow trench isolation regions [107b].
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Kim further discloses in Fig. 3-Fig. 5
a topmost surface of the second portion [170] of the self-aligned gate cut structure [170 and 180] or a bottommost surface of the first portion [180] of the self-aligned gate cut structure [170 and 180] can be varied.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim into the method of Min et al. to include wherein a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing suitable location of a topmost surface of the second portion of the self-aligned gate cut structure.
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a topmost surface of the second portion of the self-aligned gate cut structure with respect to topmost surfaces of adjacent shallow trench isolation regions: a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with/is higher than/is lower than topmost surfaces of adjacent shallow trench isolation regions. Absent unexpected results, it would have been obvious to try a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions to yield a suitable location of a topmost surface of the second portion of the self-aligned gate cut structure with a reasonable expectation of success.
Regarding claim 19, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0053]
wherein the second portion [160B] of the self-aligned gate cut structure is embedded within a shallow trench isolation region [105].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Jeon et al. (US Pub. 20190378903)
Regarding claim 16, Min et al. fails to disclose in embodiment of Fig. 8
an air gap embedded within the self-aligned gate cut structure.
However, Min et al. discloses in Fig. 17, paragraph [0164]
an air gap [AG] embedded within the self-aligned gate cut structure [160].
Jeon et al. discloses in Fig. 2,
an air gap [180] embedded within the self-aligned gate cut structure [170].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Min et al. to include an air gap embedded within the self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of improve an insulation effect of the gate isolation layer [paragraph [0039] of Jeon et al.].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Do et al. (US Pub. 20220328408)
Regarding claim 17, Min et al. fails to disclose
signal lines directly above the self aligned gate cut structure in a cell boundary.
Do et al. discloses in Fig. 10E, paragraph [0026], [0034], [0042], [0114], [0115], [0141]
signal lines [M1_I1 to M1_I4] directly above the self-aligned gate cut structure [CT] in a cell boundary.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Do et al. into the method of Min et al. to include signal lines directly above the self-aligned gate cut structure in a cell boundary. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing routing lines for connecting one cell with another cells [paragraph [0114]-[0115] of Do et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Su et al. (US Pub. 20220262915).
Regarding claim 18, Min et al. fails to disclose
a source drain contacts above and directly contacting a source drain region, wherein the source drain contact extends laterally into the self-aligned gate cut structure.
However, Min et al. discloses in paragraph [0136] “[a]lthough not shown, a via plug and/or a wiring line, which will be connected to the source/drain patterns 150, 250”.
Su et al. discloses in Fig. 12A-12B, 13A-B, 14A-B, 15A-B, paragraph [0024], [0035]-[0037]
a source drain contact [260] above and directly contacting a source drain region [230], wherein the source drain contact [260] extends laterally into the self-aligned gate cut structure [244-1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Su et al. into the method of Min et al. to include a source drain contact above and directly contacting a source drain region, wherein the source drain contact extends laterally into the self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing suitable configuration of source drain contact be connected to the source/drain patterns [Paragraph [0024] of SU et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above
Regarding claim 20, Min et al. fails to discloses in Fig. 8
wherein a smallest width of the second portion of the self-aligned gate cut structure is greater than a smallest width of the first portion of the self-aligned gate cut structure.
However, Min et al. suggests in Fig. 8-Fig. 14
a smallest width of the second portion [160B] of the self-aligned gate cut structure and a smallest width of the first portion [160U] of the self-aligned gate cut structure can be adjusted.
Thus, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure: a smallest width of the second portion of the self-aligned gate cut structure is greater than/is less than/is equal to a smallest width of the first portion of the self-aligned gate cut structure. Absent unexpected results, it would have been obvious to try wherein a smallest width of the second portion of the self-aligned gate cut structure is greater than a smallest width of the first portion of the self-aligned gate cut structure to yield a suitable smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure with a reasonable expectation of success.
Allowable Subject Matter
Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3 and 10, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “wherein a topmost surface of the backside power rail directly contacts both a bottommost surface of the self-aligned gate cut structure and a bottommost surface of a backside source drain contact” of claim 3 and 10 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Response to Arguments
Applicant’s arguments with respect to claims 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 06/12/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, Kim et al. discloses in Fig. 5 the claimed limitation “a topmost surface of the second portion [portion of 170 in the trench isolation regions 107b] of the self-aligned gate cut structure [170 and 180] and a bottommost surface of the first portion [180] of the self-aligned gate cut structure [170 and 180] is substantially flush with topmost surfaces of adjacent shallow trench isolation regions [107b].”
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It is further noted that the claimed language does not require an entire of topmost surface of the second portion is substantially flush with topmost surfaces of adjacent shallow trench isolation regions. Thus, even if a portion of topmost surface of the second portion is substantially flush with topmost surfaces of adjacent shallow trench isolation regions, it meets the claim. Further, according to Applicant’s disclosure, a surface of the second portion directly contacts the bottommost surface of the first portion is defined as a topmost surface of the second portion. Therefore, the Examiner’s interpretation is consistent with Applicant’s disclosure and consistent with the scope of the claim.
Min et al. suggests in Fig. 8-Fig. 14 a smallest width of the second portion [160B] of the self-aligned gate cut structure and a smallest width of the first portion [160U] of the self-aligned gate cut structure can be adjusted. Thus, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure: a smallest width of the second portion of the self-aligned gate cut structure is greater than/is less than/is equal to a smallest width of the first portion of the self-aligned gate cut structure. Absent unexpected results, it would have been obvious to try wherein a smallest width of the second portion of the self-aligned gate cut structure is greater than a smallest width of the first portion of the self-aligned gate cut structure to yield a suitable smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure with a reasonable expectation of success. “Obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).”
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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