DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 8, 12 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Min et al. (US Pub. 20230070925).
Regarding claim 1, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0038], [0059]-[0060], [0069], [0103], [0105], [0137]-[0139], a semiconductor structure comprising:
a first nanosheet transistor device [ transistor with active patterns AP1];
a second nanosheet transistor device [transistor with active patterns AP2];
a dielectric gate cut structure [160] between and electrically isolating the first nanosheet transistor device [transistor with active patterns AP1] from the second nanosheet transistor device [transistor with active patterns AP2], wherein a first portion [160U] of the dielectric gate cut structure [160] comprises a positive tapered profile, and a second portion [160B] of the dielectric gate cut structure [160] comprises a negative tapered profile.
Regarding claims 5 and 12, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0053]
wherein the second portion [160B] of the dielectric/self-aligned gate cut structure is embedded within a shallow trench isolation region [105].
Regarding claim 8, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0038], [0059]-[0060], [0069], [0103], [0105], [0137]-[0139], a semiconductor structure comprising:
a first nanosheet stack [active patterns AP1];
a second nanosheet stack [active patterns AP2];
a self-aligned gate cut structure [160] between and electrically isolating a first gate [120] associated with the first nanosheet stack [AP1] and a second gate [220] associated with the second nanosheet stack [AP2], wherein a first portion [160U] of the self-aligned gate cut structure [160] comprises a positive tapered profile, and a second portion [160B] of the self-aligned gate cut structure [160] comprises a negative tapered profile.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) as applied to claim 1 and claim 8 above and further in view of Jeon et al. (US Pub. 20190378903)
Regarding claims 2 and 9, Min et al. fails to disclose in embodiment of Fig. 8
an air gap embedded within the dielectric/self-aligned gate cut structure.
However, Min et al. discloses in Fig. 17, paragraph [0164]
an air gap [AG] embedded within the dielectric/self-aligned gate cut structure [160].
Jeon et al. discloses in Fig. 2,
an air gap [180] embedded within the dielectric/self-aligned gate cut structure [170].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Min et al. to include an air gap embedded within the dielectric/self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of improve an insulation effect of the gate isolation layer [paragraph [0039] of Jeon et al.].
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) as applied to claim 1 and claim 8 above and further in view of Do et al. (US Pub. 20220328408)
Regarding claims 3 and 10, Min et al. fails to disclose
signal lines directly above the dielectric/ self-aligned gate cut structure in a cell boundary.
Do et al. discloses in Fig. 10E, paragraph [0026], [0034], [0042], [0114], [0115], [0141]
signal lines [M1_I1 to M1_I4] directly above the dielectric/ self-aligned gate cut structure [CT] in a cell boundary.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Do et al. into the method of Min et al. to include signal lines directly above the dielectric/ self-aligned gate cut structure in a cell boundary. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing routing lines for connecting one cell with another cells [paragraph [0114]-[0115] of Do et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) as applied to claim 1 and claim 8 above and further in view of Su et al. (US Pub. 20220262915).
Regarding claims 4 and 11, Min et al. fails to disclose
a source drain contacts above and directly contacting a source drain region, wherein the source drain contact extends laterally into the dielectric/ self-aligned gate cut structure.
However, Min et al. discloses in paragraph [0136] “[a]lthough not shown, a via plug and/or a wiring line, which will be connected to the source/drain patterns 150, 250”.
Su et al. discloses in Fig. 12A-12B, 13A-B, 14A-B, 15A-B, paragraph [0024], [0035]-[0037]
a source drain contact [260] above and directly contacting a source drain region [230], wherein the source drain contact [260] extends laterally into the dielectric/ self-aligned gate cut structure [244-1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Su et al. into the method of Min et al. to include a source drain contact above and directly contacting a source drain region, wherein the source drain contact extends laterally into the dielectric/ self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing suitable configuration of source drain contact be connected to the source/drain patterns [Paragraph [0024] of SU et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) as applied to claim 1 and claim 8 above and further in view of Cheng et al. (US Pub. 20220139914)
Regarding claims 6 and 13, Min et al. fails to disclose
wherein the second portion of the dielectric/ self-aligned gate cut structure directly contacts a portion of a backside contact structure.
Cheng et al. discloses in Fig. 32A, Fig. 32B, paragraph [0042], [0046]-[0047],
wherein the second portion of the dielectric/ self-aligned gate cut structure [298] directly contacts a portion of a backside contact structure [306 and/or 314].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cheng et al. into the method of Min et al. to include wherein the second portion of the dielectric/ self-aligned gate cut structure directly contacts a portion of a backside contact structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of increasing the number of metal tracks available in the workpiece for directly connecting to source/drain contacts and vias, including the backside self-aligned source/drain contact [paragraph [0047] of Cheng et al.].
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) as applied to claim 1 above
Regarding claims 7 and 14, Min et al. fails to discloses in Fig. 8
wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than a smallest width of the first portion of the dielectric/self-aligned gate cut structure.
However, Min et al. suggests in Fig. 8-Fig. 14
a smallest width of the second portion [160B] of the dielectric/self-aligned gate cut structure and a smallest width of the first portion [160U] of the dielectric/self-aligned gate cut structure can be adjusted.
Thus, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a smallest width of the second portion of the dielectric/self-aligned gate cut structure with respect to a smallest width of the first portion of the dielectric/self-aligned gate cut structure: a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than/is less than/is equal to a smallest width of the first portion of the dielectric/self-aligned gate cut structure. Absent unexpected results, it would have been obvious to try wherein a smallest width of the second portion of the dielectric/self-aligned gate cut structure is greater than a smallest width of the first portion of the dielectric/self-aligned gate cut structure to yield a suitable smallest width of the second portion of the dielectric/self-aligned gate cut structure with respect to a smallest width of the first portion of the dielectric/self-aligned gate cut structure with a reasonable expectation of success.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467)
Regarding claim 15, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0038], [0059]-[0060], [0069], [0103], [0105], [0137]-[0139], a semiconductor structure comprising:
first set of nanosheet channels [AP1] surrounded by a first gate structure [120];
second set of nanosheet channels [AP2] surrounded by a second gate structure [220];
a self-aligned gate cut structure between and electrically isolating the first gate structure [120] from the second gate structure [220].
Min et al. fails to disclose
wherein a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions.
However, Min et al. appears to discloses in Fig. 17 and Fig. 19 that a topmost surface of the second portion [160B] of the self-aligned gate cut structure [160] or a bottommost surface of the first portion [160U] of the self-aligned gate cut structure [160] can be varied.
Min et al. also discloses a topmost surface of the second portion [160B] of the self-aligned gate cut structure [160] and a bottommost surface of the first portion [160U] of the self-aligned gate cut structure are same level.
Kim discloses in Fig. 5
a topmost surface of the second portion [portion of 170 in the trench isolation regions 107b] of the self-aligned gate cut structure [170 and 180] a bottommost surface of the first portion [180] of the self-aligned gate cut structure [170 and 180] is substantially flush with topmost surfaces of adjacent shallow trench isolation regions [107b].
PNG
media_image1.png
580
730
media_image1.png
Greyscale
Kim further discloses in Fig. 3-Fig. 5
a topmost surface of the second portion [170] of the self-aligned gate cut structure [170 and 180] or a bottommost surface of the first portion [180] of the self-aligned gate cut structure [170 and 180] can be varied.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim into the method of Min et al. to include wherein a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing suitable location of a topmost surface of the second portion of the self-aligned gate cut structure.
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a topmost surface of the second portion of the self-aligned gate cut structure with respect to topmost surfaces of adjacent shallow trench isolation regions: a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with/is higher than/is lower than topmost surfaces of adjacent shallow trench isolation regions. Absent unexpected results, it would have been obvious to try a topmost surface of the second portion of the self-aligned gate cut structure is substantially flush with topmost surfaces of adjacent shallow trench isolation regions to yield a suitable location of a topmost surface of the second portion of the self-aligned gate cut structure with a reasonable expectation of success.
Regarding claim 19, Min et al. discloses in Fig. 3, Fig. 8, paragraph [0053]
wherein the second portion [160B] of the self-aligned gate cut structure is embedded within a shallow trench isolation region [105].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Jeon et al. (US Pub. 20190378903)
Regarding claim 16, Min et al. fails to disclose in embodiment of Fig. 8
an air gap embedded within the self-aligned gate cut structure.
However, Min et al. discloses in Fig. 17, paragraph [0164]
an air gap [AG] embedded within the self-aligned gate cut structure [160].
Jeon et al. discloses in Fig. 2,
an air gap [180] embedded within the self-aligned gate cut structure [170].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeon et al. into the method of Min et al. to include an air gap embedded within the self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of improve an insulation effect of the gate isolation layer [paragraph [0039] of Jeon et al.].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Do et al. (US Pub. 20220328408)
Regarding claim 17, Min et al. fails to disclose
signal lines directly above the self aligned gate cut structure in a cell boundary.
Do et al. discloses in Fig. 10E, paragraph [0026], [0034], [0042], [0114], [0115], [0141]
signal lines [M1_I1 to M1_I4] directly above the self-aligned gate cut structure [CT] in a cell boundary.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Do et al. into the method of Min et al. to include signal lines directly above the self-aligned gate cut structure in a cell boundary. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing routing lines for connecting one cell with another cells [paragraph [0114]-[0115] of Do et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above and further in view of Su et al. (US Pub. 20220262915).
Regarding claim 18, Min et al. fails to disclose
a source drain contacts above and directly contacting a source drain region, wherein the source drain contact extends laterally into the self-aligned gate cut structure.
However, Min et al. discloses in paragraph [0136] “[a]lthough not shown, a via plug and/or a wiring line, which will be connected to the source/drain patterns 150, 250”.
Su et al. discloses in Fig. 12A-12B, 13A-B, 14A-B, 15A-B, paragraph [0024], [0035]-[0037]
a source drain contact [260] above and directly contacting a source drain region [230], wherein the source drain contact [260] extends laterally into the self-aligned gate cut structure [244-1].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Su et al. into the method of Min et al. to include a source drain contact above and directly contacting a source drain region, wherein the source drain contact extends laterally into the self-aligned gate cut structure. The ordinary artisan would have been motivated to modify Min et al. in the above manner for the purpose of providing suitable configuration of source drain contact be connected to the source/drain patterns [Paragraph [0024] of SU et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US Pub. 20230070925) in view of Kim et al. (US Pub. 20240079467) as applied to claim 15 above
Regarding claim 20, Min et al. fails to discloses in Fig. 8
wherein a smallest width of the second portion of the self-aligned gate cut structure is greater than a smallest width of the first portion of the self-aligned gate cut structure.
However, Min et al. suggests in Fig. 8-Fig. 14
a smallest width of the second portion [160B] of the self-aligned gate cut structure and a smallest width of the first portion [160U] of the self-aligned gate cut structure can be adjusted.
Thus, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure: a smallest width of the second portion of the self-aligned gate cut structure is greater than/is less than/is equal to a smallest width of the first portion of the self-aligned gate cut structure. Absent unexpected results, it would have been obvious to try wherein a smallest width of the second portion of the self-aligned gate cut structure is greater than a smallest width of the first portion of the self-aligned gate cut structure to yield a suitable smallest width of the second portion of the self-aligned gate cut structure with respect to a smallest width of the first portion of the self-aligned gate cut structure with a reasonable expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893