Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 5, 2023 and March 26, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-11, 13, and 15-19 are objected to because of the following informalities:
Claims 1 and 17 - objected to as being informal because it contains ("..."). The claim must be rewritten to recite the subject matter without placeholder or omissions.
Claims 2-11 - recites "A multistage feed network". The 'A' should be revised to 'The' in the preamble.
Claim 13 and 15-16 - recites "A superconducting system". The 'A' should be revised to 'The' in the preamble.
Claims 18-19 (line 1) - recites "A method for fabricating", the 'A' should be revised to 'The' in the preamble. Additionally, recites "fabricating a superconducting system", the 'a' should be revised to 'the' in the preamble.
Claims 18-19 (line 2) - recites "in first layers of a fabrication stack", the 'a' should be revised to 'the'.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 10, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112(pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 (lines 5-7) recites "wherein the first stage comprises a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes". It is unclear where the transmission line having a length of λ within the first stage is shown.
Claim 10 (lines 6-8) recites "wherein said stage comprises a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes". It is unclear where the transmission line having a length of λ within the second stage is shown.
Claim 17 (lines 3-4 and 11-15) recites "a superconducting circuit comprising a plurality of tiles, each comprising at least one Josephson junction" and "the method comprising: 1) forming, in first layers of a fabrication stack, the multistage feed network and the plurality of tiles except for the at least one Josephson junction; and 2) forming, in second layers of the fabrication stack, the at least one Josephson junction". It is unclear if the Josephson junction is included, or not included in the structure, as the first part of the claim states that it is comprised within, but it's not included later in the claim.
Claims 18-19 inherit the defects of the associated parent claim and/or any intervening claims.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 12-13, and 17-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Herr er al. (US 20230208400 A1); hereinafter Herr.
Regarding Claim 1, Herr discloses a multistage feed network [paragraph 0059; Fig. 4A/4B, 405/405A/405B] for distributing a signal [paragraph 0044; signal is outputted from 225] for feeding a superconducting circuit [Fig. 4A/4B, 210/215/220], wherein the multistage feed network comprises: a number N stages being a first stage [Fig. 4B, wires in parallel within 405A], ..., and a Nth stage [Fig. 3B, VAC1 nodes with connected wires; Fig. 4B, wires in parallel within 405B to 215/220], arranged in a sequential order [Fig. 4A/4B], and a plurality of two-port networks [Fig. 4A, 405A/405B], each configured to electrically connect to two adjacent stages in between; wherein the first stage is configured to electrically connect to a signal source [Fig. 4B, 225] for receiving a first incoming signal [paragraph 0044], and to distribute the first incoming signal to a plurality of first outgoing signals [Fig. 4B, plurality of signals within 405A]; ... and wherein the Nth stage is configured to receive a plurality of Nth incoming signals [Fig. 3B, VAC1 nodes with connected wires; Fig. 4B, wires in parallel within 405B to 215/220], and to distribute each of the plurality of Nth incoming signals [Fig. 4B, 405B outputs] to a plurality of Nth outgoing signals [Fig. 3B, VAC1; Fig. 4B, the common nodes 215/220]; wherein for each stage [Fig. 4B, 1st stage: wires in parallel within 405A; 2nd stage: wires between 405A/405B], except for the Nth stage, each of the plurality (pluralities) of outgoing signals of said stage is configured to be electrically coupled to one of the plurality of incoming signals of its immediate subsequent stage by one of the plurality of two-port networks [Fig. 4A/4B, transmission lines 405A/405B]; wherein said one of the plurality of two-port networks is configured to perform impedance matching between said stage and its immediate subsequent stage [paragraphs 0060-0061]; wherein the pluralities of Nth outgoing signals are configured to be fed to the superconducting circuit [Fig. 2B, 250; Fig. 3B, VAC1; Fig. 4B, outputs of 405B]; wherein at least one stage of the number N stages comprises a mesh network [Fig. 3B, 305A] made of interconnected superconducting wires such that the incoming signal(s) of said stage is configured to be distributed to the outgoing signals of said stage by said mesh network with a minimal deviation of signal amplitude and of signal phase [paragraphs 0041, 0058]; wherein the signal source is an Alternating Current, AC, voltage source [paragraph 0044]; wherein the first incoming signal is a power/clock combined signal [paragraphs 0031, 0038]; and wherein N is an integer, and N > 2 [Fig, 4A/4B, N=3].
Regarding Claim 2, Herr discloses the multistage feed network according to claim 1, wherein said one of the plurality of two-port networks comprises at least one transmission line element having a length of one-half wavelength (λ/2) [paragraph 0056]; wherein the at least one transmission line element comprises a single transmission line [Fig. 3B, 310] having a length of one-half wavelength (λ/2) [paragraph 0056], or two transmission lines connected in series each having a length of one quarter wavelength (λ/4) [paragraph 0060]; wherein the wavelength (λ) is the wavelength of a signal transmitted through the transmission line(s) [paragraphs 0044, 0062].
Regarding Claim 3, Herr discloses the multistage feed network according to claim 2, wherein the at least one transmission line element is implemented as a lumped element network comprising at least one inductor and at least one capacitor [paragraph 0062].
Regarding Claim 4, Herr discloses the multistage feed network according to claim 1, wherein the Nth stage comprises a bottom mesh network made of interconnected superconducting wires configured to feed the pluralities of Nth outgoing signals to the superconducting circuit [Fig. 3B].
Regarding Claim 12, Herr discloses a superconducting system [Fig. 1, 3B, 4A, 4B], comprising: a superconducting circuit [Fig. 2A/2B/2C4A/4B, 205/210/215/220] comprising a plurality of tiles [Fig. 1, 105A-105I]; wherein each of the plurality of tiles comprises: at least one resonant circuit [205] comprising: an inductor [215] comprising a first terminal and a second terminal, and at least one capacitor [220] comprising a first terminal electrically connected to the second terminal of the inductor; and at least one Josephson junction [210] comprising a first terminal electrically connected to a second terminal of the at least one capacitor and a second terminal electrically connected to a ground or virtual ground node [ground]; and the multistage feed network according to claim 1 configured to feed an outgoing signal of the pluralities of Nth outgoing signals [see claim 1 rejection above] to the terminal shared by the inductor and the at least one capacitor.
Regarding Claim 13, Herr discloses the superconducting system according to claim 12, wherein an inductance of the inductor and a capacitance of the at least one capacitor are selected to cause the at least one resonant circuit to resonate at a frequency that substantially matches a particular frequency of said outgoing signal to facilitate switching a state of the at least one Josephson junction via a single flux quantum, SFQ, pulse [Abstract; paragraph 0047].
Regarding Claim 17, as best understood, Herr discloses a method for fabricating a superconducting system [Fig. 5A/5B/6], wherein the superconducting system comprises: a superconducting circuit [Fig. 2A/2B/2C4A/4B, 205/210/215/220] comprising a plurality of tiles [Fig. 1, 105A-105I], each comprising at least one Josephson junction [210], and a multistage feed network [Fig. 4A/4B] for distributing a signal [Fig. 3B, VAC1; Fig. 4B, outputs of 405B] for feeding the superconducting circuit; wherein the multistage feed network comprises a number N stages being a first stage [Fig. 4B, wires in parallel within 405A], ..., and a Nth stage [Fig. 3B, VAC1 nodes with connected wires; Fig. 4B, wires in parallel within 405B to 215/220], arranged in a sequential order [Fig. 4A/4B], and a plurality of two- port networks [405A/405B], each configured to electrically connect to two adjacent stages in between; the method comprising: 1) forming, in first layers of a fabrication stack [Fig. 5A, 505A/505B/515], the multistage feed network and the plurality of tiles except for the at least one Josephson junction [paragraphs 0073-0078; Fig. 6, 605]; and 2) forming, in second layers of the fabrication stack [Fig. 5A, 510], the at least one Josephson junction [paragraphs 0073-0078; Fig. 6, 610]; wherein the first stage is configured to electrically connect to a signal source for receiving a first incoming signal [Fig. 4B, 225], and to distribute the first incoming signal to a plurality of first outgoing signals [Fig. 3B, VAC1; Fig. 4B, output of 405]; ... and wherein the Nth stage is configured to receive a plurality of Nth incoming signals [Fig. 3B, VAC1 nodes with connected wires; Fig. 4B, wires in parallel within 405B to 215/220], and to distribute each of the plurality of Nth incoming signals [Fig. 4B, 405B outputs] to a plurality of Nth outgoing signals [Fig. 3B, VAC1; Fig. 4B, the common nodes 215/220]; wherein for each stage [Fig. 4B, 1st stage: wires in parallel within 405A; 2nd stage: wires between 405A/405B], except for the Nth stage, each of the plurality (pluralities) of outgoing signals of said stage is configured to be electrically coupled to one of the plurality of incoming signals of its immediate subsequent stage by one of the plurality of two-port networks [Fig. 4A/4B, transmission lines 405A/405B]; wherein said one of the plurality of two-port networks is configured to perform impedance matching between said stage and its immediate subsequent stage [paragraphs 0060-0061]; wherein the pluralities of Nth outgoing signals are configured to be fed to the superconducting circuit [Fig. 2B, 250; Fig. 3B, VAC1; Fig. 4B, outputs of 405B]; wherein at least one stage of the number N stages comprises a mesh network [Fig. 3B, 305A] made of interconnected superconducting wires such that the incoming signal(s) of said stage is configured to be distributed to the outgoing signals of said stage by said mesh network with a minimal deviation of signal amplitude and of signal phase [paragraphs 0041, 0058]; wherein the signal source is an Alternating Current, AC, voltage source [paragraph 0044]; wherein the first incoming signal is a power/clock combined signal [paragraphs 0031, 0038]; and wherein N is an integer, and N > 2 [Fig, 4A/4B, N=3].
Regarding Claim 18, as best understood, Herr discloses the method for fabricating the superconducting system according to claim 17, wherein the step of 1) forming, in first layers of the fabrication stack, the multistage feed network and the plurality of tiles except for the at least one Josephson junction [Fig. 5A, 505A, 505B, 515; Fig. 6, 605] comprises: forming, in the first layers of the fabrication stack, the plurality of tiles each comprising at least one resonant circuit [205] comprising an inductor [215] and at least one capacitor [220], wherein the inductor comprising a first terminal and a second terminal, and the at least one capacitor comprising a first terminal electrically connected to the second terminal of the inductor; wherein the at least one Josephson junction [210] comprises a first terminal electrically connected to a second terminal of the at least one capacitor and a second terminal electrically connected to a ground or virtual ground node [ground].
Regarding Claim 19, as best understood, Herr discloses the method for fabricating the superconducting circuit according to claim 17, wherein the step of 1) forming, in first layers of the fabrication stack, the multistage feed network and the plurality of tiles except for the at least one Josephson junction comprises: forming at least two stages of the multistage feed network by interleaving two metal layers of the first layers [paragraph 58].
Allowable Subject Matter
Claims 7 and 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 5-6, 8-9, 11, 14-16, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Amit R Bhatia/Examiner, Art Unit 2842
/REGIS J BETSCH/SPE, Art Unit 2844