Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 12/05/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-9, 13-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Decker (Pub. No. 2005/0268258 A1).
Regarding claims 1, 8, and 15, Decker discloses:
A method for optimizing error-checking logic in a processor design (see Abstract, A rule-based design consultant and analysis method for an integrated circuit ("IC") layout design compares an IC design against a list of rules….), method comprising:
performing static analysis on the processor design, wherein the processor design includes one or more latches and one or more checkers (see par [0002-0004], Semantic checkers evolved into structural rule checkers: Structural rule checkers mapped coded …. This process allowed for a set of synthesizability checks, and more complex structural checking such as the existence of latches…., see par [0137-0138], Design analyzer 402 may include a static timing analysis engine 428 that reads industry standard timing constraints ….);
generating mapping between the one or more latches and the one or more checkers (see par [0003-0006], Semantic checkers evolved into structural rule checkers: Structural rule checkers mapped coded language for a design onto a simple generic structural netlist…, see par [0089], [0103-0104]);
determining checker set cover based on the mapping (see par [0006], a rule-based design consultant and analysis method optionally checks of the actual synthesis and physical implementation of the design as well as timing…, see par [0093-0099], the rule-based design consultant can make sure the circuit is receiving all the timing information, such as clock definitions and I/O constraints…, [wherein the rule-based design is the checker set cover based]);
preselecting timing critical checkers from the one or more checkers (see par [0006], [0167], Paths that do not meet timing are referred to as critical paths. Critical path object list 714 displays information about each element in the critical path…., see par [0179], a user selects the multiplexer in the high congestion rule report, other reports in which the multiplexer appears, such as the timing critical path report….);
determining redundant checkers based on checker activity (see par [0042], Synthesis typically includes optimization of the HDL code, such as by elimination of redundant terms, [wherein the elimination of redundant which is the checkers have been determined]);
eliminating redundant checkers; and determining whether convergence criteria has been met (see par [0042], Synthesis typically includes optimization of the HDL code, such as by elimination of redundant terms, [wherein the elimination of redundant which is the checkers have been determined], see par [0137], wherein the components or timing critical paths that require synthesis technology to optimize…see par [0115], This rule can also be used to drive automatic correction of the issue…).
Regarding claims 2, 9, and 16, Decker discloses:
wherein performing the static analysis further comprises: identify and organize the processor design into sets of timing paths (see par [0006], This enables timing and area analysis features that identify, for example, high-density areas and timing critical paths…, see par [0136-0138]), wherein the timing paths are associated with the one or more checkers and the one or more latches see par [0006], This enables timing and area analysis features that identify, for example, high-density areas and timing critical paths…, see par [0136-0138], see par [0003-0006], [0102]); calculate delay of each of the sets of timing paths; validating all path delays of the sets of timing paths conform to timing constraints; and identify and list the one or more checkers and the one or more latches based on all of the path delays of the sets of timing paths that has conformed (see par [0140], [0143-0149], [wherein the report obtain the list of latches and checkers with the path critical delay]).
Regarding claims 6 and 13, Decker discloses:
wherein eliminating checkers further comprises: removing the redundant checkers from the set cover (see par [0042], Synthesis typically includes optimization of the HDL code, such as by elimination of redundant terms, [wherein the elimination of redundant which is removed]).
Regarding claims 7, 14, and 20, Decker discloses:
wherein determining whether convergence criteria have been met further comprises: iteratively repeating a step of, i) determining the checker set cover, ii) preselecting timing critical checkers from the one or more checkers, iii) determining redundant checkers based on checker activity and iv) eliminating redundant checkers until the set cover meets the converge criteria (see par [0148], Subsequently, the design may be analyzed again, based on a revised version of the source code…, see the rejection in claim 1 above).
Allowable Subject Matter
Claims 3-5, 10-12, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest the limitation as in the claims.
Conclusion
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/BRIAN NGO/Primary Examiner, Art Unit 2851
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