DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2-3 are objected to because of the following informalities:
Re. claim 2: The phrase “preparing a substrate having conducting layers” as recited in line 3 appears to be –(a) preparing a substrate having conducting layers--.
The phrase “or applying adhesive component material on the surface” as recited in lines 7-8 appears to be –or applying an adhesive component material on the surface--.
The phrase “dicing the structure to get a wafer level component” as recited in line 11 appears to be –dicing the structure to get the wafer level component--.
Re. claim 2: The phrase “the substrate is copper clad laminate (CCL)” as recited in line 3 appears to be –the substrate is a copper clad laminate (CCL)--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re. claim 1: The phrase “the circuit board containing the wafer level” as recited in line 1 lacks antecedent basis.
The phrase “the upper surface down to the lower surface” as recited in lines 4-5 lacks antecedent basis.
The phrase “the upper surface” as recited in line 9 lacks antecedent basis.
The phrase “the top surface of the wafer level component wherein the dummy chip height level is aligned to the height level of the copper clad laminate plate” as recited in lines 12-13 lacks antecedent basis.
The phrase “the whole upper top surface” as recited in line 14 lacks antecedent basis.
The phrase “the whole lower bottom surface” as recited in line 17 lacks antecedent basis.
Re. claim 2: The phrase “the circuit board containing the wafer level” as recited in line 1 lacks antecedent basis.
The phrase “the upper surface down to the lower surface” as recited in lines 4-5 lacks antecedent basis.
The phrase “the surface of dummy wafer” as recited in line 8 lacks antecedent basis.
The phrase “adjusting the thickness of the structure of the step (d) by grinding the lower bottom surface of the structure” as recited in lines 10-11 lacks antecedent basis.
The phrase “the lower surface of the structure” as recited in line 14 lacks antecedent basis.
The phrase “the whole surface of the substrate” as recited in line 15 lacks antecedent basis.
Re. claim 4: The phrase “for forming the route which electrically connects the electrode of the embedded wafer level component to the outer circuit of the circuit board” as recited in lines 2-3 lacks antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 1029a)(1) as being anticipated by Lee et al. (PGPub 2013/0027896 A1).
Lee et al. teach a process of fabricating a circuit board containing a wafer level component, comprising steps of: preparing a substrate having conducting layers (112, Fig. 2, paragraph [0058]) on both surfaces and drilling the substrate to form a cavity (115, Fig. 2, paragraph [0059]) of a predetermined size that penetrates from the upper surface down to the lower surface; attaching an adhesive tape (117, Fig. 3, paragraph [0060]) to the lower surface of the substrate; inserting the wafer level component (120, Fig. 4, paragraph [0061])into the cavity and settling the wafer level component on the adhesive tape; applying an adhesive component material (150, Fig. 5, paragraph [0062])on top of the upper surface of the wafer level component; attaching a dummy chip (130, Fig. 6, paragraph [0063]) via the adhesive component material so that the dummy chip is adhered to the top surface of the wafer level component wherein the dummy chip height level is aligned to the height level of a copper clad laminate plate after the attachment; applying a first insulating layer (162, Fig. 7, paragraph [0069]) on the whole upper top surface of the substrate wherein the dummy chip is glued; removing the adhesive tape at the lower surface of the substrate (Fig. 8, paragraph [0069]); and attaching a second insulating layer (164, Fig. 8, paragraph [0070]) on the whole lower bottom surface of the substrate wherein the adhesive tape is removed.
Re. claim 3: It is noted that copper clad laminate (CCL) is inherently and primarily used as a base material for printed circuit boards (PCBs), providing both the conductive copper layer for circuit paths and the insulating substrate for structural support as shown in Fig. 2.
Re. claim 4: Since the scope of the claimed invention is the manufacturing process for the circuit board, the limitations as recited in claim 4 is how to use the circuit board. It is noted that the claim 4 can be drafted to recite the intended working environment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. as applied to claim 1 above, and further in view of Tuominen et al. (PGPub 2011/0291293 A1).
Lee et al. teach all limitations as set forth above, but silent how to prepare the wafer level component. Tuominen et al. teach a process of making a circuit board of an electronic module including a process of wafer grinding or thinning (equivalent with cutting) a component in order to adjust a thickness of the component in order to improve product warpage (paragraph [0113]). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating a circuit board containing a wafer level component of Lee et al. by preparing the wafer level component winding by preparing processes as taught by Tuominen et al. in order to produce a minimum thickness of a final product and to achieve improved product warpage.
The Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Moon et al. (PGPub 2016/0165732 A1), Chou et al. (PGPub 2011/0225816 A), Nagata (PGPub 2010/0163290 A1, and Sato et al. (US PAT. 5,858,816) are cited to further show the state of the art with respect to a fabricating method of the circuit board embedding an electrical component.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM.
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/PAUL D KIM/Primary Examiner, Art Unit 3729
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