Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The corrections made to the specification in the response filed on July 22, 2026 are accepted by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities: claim 4 recites the limitation “the trim pattern has a width covering two of the partition wall pillar in the second direction,” on page 4 lines 14-15. This limitation contains a typographical error because two of the partition wall pillar should be plural. For examination purposes, this limitation will be interpreted as reciting the trim pattern has a width covering two of the partition wall pillars in the second direction. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: claim 13 recites the limitation “a horizontal cross section of each the plurality of second cylinders has a circular shape,” on page 7 lines 13-14. This limitation contains a typographical error each the plurality of second cylinders should be each of the plurality of second cylinders. For examination purposes, this limitation will be interpreted as reciting a horizontal cross section of each of the plurality of second cylinders has a circular shape. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a partition wall pillar having a shape of a second cylinder is arranged between the plurality of electrode structures adjacent to each other in the first direction,” on page 3 lines 20-21. This limitation renders claim 1 indefinite because it is unclear how a partition wall pillar is arranged between the plurality of electrode structures. The examiner first notes that claim 1 previously recites “wherein the plurality of electrode structures is arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction,” on page 3 lines 14-16. The examiner next notes that the minimum dimensions of a two-dimensional array are two rows and two columns. The examiner now notes that it is unclear how the plurality of electrode structures is adjacent to each other in a first direction because claim 1 previously recited the plurality of electrode structure is arranged in a two-dimensional array and also how a partition wall pillar is arranged between electrode structures of the plurality of electrode structures. For examination purposes, this limitation will be interpreted as reciting a partition wall pillar having a shape of a second cylinder is arranged between each two electrode structures of the plurality of electrode structures that are adjacent to each other in the first direction.
Claims 2-8 are also rejected for containing the same limitation because claims 2-8 depend from claim 1.
Claim 12 recites the limitations “wherein the first electrode and the switching material layer together have a shape of a second cylinder,” on page 6 lines 20-21 and “wherein the first electrode comprises a plurality of second cylinders arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction,” on page 6 lines 21-23. These limitations render claim 12 indefinite because it is unclear how the first electrode and the switching material layer together have a shape of a second cylinder and the first electrode comprises a plurality of second cylinders arranged in a two-dimensional array structure. For examination purposes, the second limitation recited above will be interpreted as reciting wherein a plurality of the second cylinders is arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction.
Claims 13-16 are also rejected for containing the same limitation because claims 13-16 depend from claim 12.
Claim 12 recites the limitation “a partition wall pillar having a shape of a third cylinder is arranged between the plurality of second cylinders adjacent to each other in the first direction,” on page 7 lines 1-2. This limitation renders claim 12 indefinite because it is unclear how a partition wall pillar is arranged between the plurality of second cylinders. The examiner first notes that claim 12 as currently interpreted previously recites wherein a plurality of the second cylinders is arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction. The examiner next notes that the minimum dimensions of a two-dimensional array are two rows and two columns. The examiner now notes that it is unclear how the plurality of second cylinders is adjacent to each other in a first direction because claim 12 is interpreted to previously recite the plurality of second cylinders is arranged in a two-dimensional array and also how a partition wall pillar is arranged between second cylinders of the plurality of second cylinder. For examination purposes, this limitation will be interpreted as reciting a partition wall pillar having a shape of a third cylinder is arranged between each two second cylinders of the plurality of second cylinders that are adjacent to each other in the first direction.
Claims 13-16 are also rejected for containing the same limitation because claims 13-16 depend from claim 12.
Claim 13 recites the limitation “the plurality of second cylinders and the third cylinder partially overlap each other in the first direction,” on page 7 lines 10-11. This limitation renders claim 13 indefinite because it is unclear how the entire plurality of second cylinders partially overlaps the third cylinder. For examination purposes, claim 13 will be interpreted as reciting each two second cylinders of the plurality of second cylinders that are adjacent to each other in the first direction and the third cylinder arranged there between partially overlap each other in the first direction, a horizontal cross section of each of the plurality of second cylinders have a circular shape; and a horizontal cross section of each of the third cylinders comprises a concave portion at opposite sides thereof in the first direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa et al. (US 8,299,571) in view of Hinoue et al. (US 10,950,627) further in view of Lue (US 2015/0340371).
Regarding Claim 1:
Ozawa discloses a three-dimensional (3D) vertical memory device, comprising:
a substrate (the resistance-change memory cell array of the first embodiment is formed on a substrate, See col. 6 lines 7-14);
a plurality of electrode structures (column shaped vertical electrodes and variable resistance film, See figs. 1A-1B, 6A-6B, ref. nos. 12, 13, col. 3 lines 24-53, and col. 5 lines 54-63. The examiner notes that the vertical electrode and variable resistance film are shown extending in a vertical direction in figure 1A. The examiner also notes that the hole etched into the conductive layers and the insulating films is shown extending in the vertical direction in figure 8A.) extending in a vertical direction on the substrate, each of the plurality of electrode structures having a shape of a first cylinder (column shaped vertical electrodes and variable resistances film have a shape of a cylinder, See figs. 6A-6B, 8A-8B ref. nos. 12, 13) and comprising a first electrode (column shaped vertical electrode, See figs. 1A-1B, 6A-6B, ref. no. 12, col. 3 lines 24-53, and col. 5 lines 54-63) and a switching material layer (variable resistance film, See figs. 1A-1B, 6A-6B, ref. no. 13, col. 3 lines 60-67, and col. 4 lines 1-2); and
a gate stack structure (horizontal electrode and interelectrode insulating film, See fig. 1A, ref. no. 11, fig. 8B, ref. nos. 11, 16, and col. 3 lines 23-53) comprising a gate electrode (horizontal electrode, See figs. 1A, 8B, ref. no. 11 and col. 6 lines 6-48) and an interlayer insulating layer (interelectrode insulating film, See fig. 8B, ref. no. 16 and col. 6 lines 6-48) that are alternately stacked on the substrate along a sidewall of the plurality of electrode structures, the gate electrode is electrically connected to the switching material layer (the horizontal electrodes are electrically connected to the variable resistance films because the horizontal electrodes are in contact with the variable resistance films, See figs. 1A, 6A-6B, 8B, ref. nos. 11, 13),
wherein the plurality of electrode structures is arranged in a two-dimensional array structure (the column shaped vertical electrode and variable resistance film are arranged in a 2x2 grid, See fig. 9B and col. 6 lines 49-59) on a plane perpendicular to the vertical direction, and constitutes a plurality of lines extending in a first direction on the plane (the left two column shaped vertical electrodes and variable resistance films are in a line from top to bottom and the right two column shaped vertical electrodes and variable resistances film are in a line from top to bottom, See fig. 9B).
Ozawa does not disclose on the plane, the electrode structures of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction, and a partition wall pillar having a shape of a second cylinder is arranged between the electrode structures adjacent to each other in the first direction, and the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Hinoue discloses on the plane, the electrode structures of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction (rows of alternating memory openings and oval shaped pillar structures laterally offset by one half pitch, See fig. 15B, ref. no. 49, 242, 244, col. 29 lines 20-27, and col. 31 lines 5-14), and a partition wall pillar arranged between the electrode structures adjacent to each other in the first direction (oval shaped pillar structures with a etch stop sacrificial liner and a sacrificial fill material, See fig. 15B, ref. nos. 242, 244, and col. 29 lines 11-36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa to include the electrode structures of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction and a partition wall pillar arranged between the electrode structures adjacent to each other in the first direction as taught Hinoue so that the column shaped vertical electrodes and variable resistance films can be located closer together to increase memory density.
The above stated combination of Ozawa and Hinoue does not disclose a partition wall pillar having a shape of a second cylinder is arranged between the electrode structures adjacent to each other in the first direction and the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Lue discloses a partition wall pillar (Isolation pillar, See figs. 2, 5B, ref. nos. 28, 29 and paragraph 45) having a shape of a second cylinder (the isolation pillars are shown in figures 2 and 5B having a shape of a cylinder, See fig. 2, 5B, ref. nos. 28, 29) is arranged between the electrode structures adjacent to each other in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa and Hinoue to include a partition wall pillar having a shape of a second cylinder is arranged between the electrode structures adjacent to each other in the first direction as taught in Lue in order to isolate neighboring vertical electrodes and variable resistance films.
The above stated combination of Ozawa, Hinoue, and Lue does not disclose the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Lue discloses the gate stack structure has a split plate electrode shape (the even word line structure and the odd word line structure form a split plate electrode shape, See fig. 13, ref. nos. 200, 201 and paragraph 79), each layer of the gate electrode of the gate stack structure having a first plate electrode (the even word line structure is in contact with the left sidewalls of the active pillars, See fig. 13, ref. nos. 200, 202-1 through 202-5, 208-1 through 208-5) and a second plate electrode (the odd word line structure is in contact with the right sidewalls of the active pillars, See fig. 13, ref. nos. 200, 202-1 through 202-5, 208-1 through 208-5) in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other (the even word line structure and the odd word line structure have word line extensions into the array of active pillars that are interdigitated, See fig. 13, ref. nos. 200, 201, and paragraph 79).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa, Hinoue, and Lue to include the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other as taught Lue in order to reduce the area constraints for word line drivers by driving word lines with a comb structure instead of driving each word line individually.
Regarding Claim 2:
The above stated combination of Ozawa, Hinoue, and Lue discloses the first cylinder (active pillars, See Lue, fig. 5B, ref. nos. 80-2, 80-3, and paragraph 56) and the second cylinder partially (Isolation pillar, See Lue figs. 5B, ref. no. 29 and paragraph 45) overlap each other in the first direction (See Lue fig. 5B, ref. nos. 29, 80-2, 80-3. The examiner also notes the Hinoue teaches each memory opening cuts through a segment of each etch stop sacrificial line, See Hinoue fig. 15B, ref. nos. 49, 242, and col. 29 lines 53-57); a horizontal cross section of the first cylinder has a circular shape (See Lue, fig. 5B, ref. nos. 80-2, 80-3, and paragraph 56); and a horizontal cross section of the second cylinder comprises a concave portion at opposite sides thereof in the first direction (See Lue figs. 5B, ref. no. 29).
Regarding Claim 5:
Ozawa discloses the first electrode is arranged in a central portion of the first cylinder (column shaped vertical electrode is in the center the cylinder include the column shaped vertical electrode and variable resistance film, See figs. 6A-6B, 8A-8B ref. nos. 12, 13), the first electrode having a shape of a third cylinder having a smaller diameter than the first cylinder (See figs. 6A-6B, 8A-8B ref. no. 12); and the switching material layer (variable resistance film has a circular pipe shape extending in the vertical direction and surrounding the column shaped vertical electrode, See figs. 1A, 6A-6B, 8A-8B ref. nos. 12, 13) has a circular pipe shape extending in the vertical direction and surrounding the first electrode.
Regarding Claim 6:
Ozawa discloses the switching material layer comprises a bottom surface that covers a lower surface of the third cylinder (The examiner notes the fabrication process for forming the variable resistance layer deposits material for forming the variable resistance layer at the bottom of the hole and this material will cover the bottom surface of the vertical electrode, See figs. 8A, 8B and col. 22-48).
Regarding Claim 12:
Ozawa discloses a three-dimensional (3D) vertical memory device, comprising:
a substrate (the resistance-change memory cell array of the first embodiment is formed on a substrate, See col. 6 lines 7-14);
a first electrode (column shaped vertical electrode, See figs. 1A-1B, 6A-6B, ref. nos. 12, col. 3 lines 24-53, and col. 5 lines 54-63. The examiner notes that the vertical electrode is shown extending in a vertical direction in figure 1A. The examiner also notes that the hole etched into the conductive layers and the insulating films is shown extending in the vertical direction in figure 8A.) on the substrate, the first electrode extending in a vertical direction and having a shape of a first cylinder (the column shaped vertical electrode has a shape of a first cylinder, See figs. 6A-6B, 8A-8B, ref. no. 12);
a switching material layer (variable resistance film, See figs. 1A-1B, 6A-6B, ref. nos. 12, 13, col. 3 lines 24-53, and col. 5 lines 54-63. The examiner notes that the variable resistance film is shown extending in a vertical direction in figure 1A. The examiner also notes that the hole etched into the conductive layers and the insulating films is shown extending in the vertical direction in figure 8A.) having a circular pipe shape extending in the vertical direction and surrounding the first electrode (the variable resistance film has a circular pipe shape extending in the vertical direction and surrounding the column shaped vertical electrode, See figs. 1A, 6A-6B, 8A-8B, ref. nos. 12, 13); and
a gate stack structure (horizontal electrode and interelectrode insulating film, See fig. 1A, ref. no. 11, fig. 8B, ref. nos. 11, 16, and col. 3 lines 23-53) comprising a gate electrode (horizontal electrode, See figs. 1A, 8B, ref. no. 11 and col. 6 lines 6-48) and an interlayer insulating layer (interelectrode insulating film, See fig. 8B, ref. no. 16 and col. 6 lines 6-48) that are alternately stacked on the substrate along a sidewall of the switching material layer, the gate electrode is electrically connected to the switching material layer (the horizontal electrode is electrically connected to the variable resistance film because the horizontal electrode is in contact with the variable resistance film, See figs. 1A, 6A-6B, 8B, ref. nos. 11, 13),
wherein the first electrode and the switching material layer together have a shape of a second cylinder (column shaped vertical electrode and variable resistance film have a shape of a cylinder, See figs. 6A-6B, 8A-8B ref. nos. 12, 13), wherein the first electrode comprises a plurality of second cylinders arranged in a two-dimensional array structure (the column shaped vertical electrodes and variable resistance films are arranged in a 2x2 grid, See fig. 9B and col. 6 lines 49-59) on a plane perpendicular to the vertical direction, and constitutes a plurality of lines extending in a first direction on the plane (the left two column shaped vertical electrodes and variable resistance films are in a line from top to bottom and the right two column shaped vertical electrodes and variable resistances film are in a line from top to bottom, See fig. 9B).
Ozawa does not disclose on the plane, the plurality of second cylinders of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction, a partition wall pillar having a shape of a third cylinder is arranged between the plurality of second cylinders adjacent to each other in the first direction, and the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Hinoue discloses on the plane, the plurality of second cylinders of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction (rows of alternating memory openings and oval shaped pillar structures laterally offset by one half pitch, See fig. 15B, ref. no. 49, 242, 244, col. 29 lines 20-27, and col. 31 lines 5-14), and a partition wall pillar arranged between the second cylinders adjacent to each other in the first direction (oval shaped pillar structures with a etch stop sacrificial liner and a sacrificial fill material, See fig. 15B, ref. nos. 242, 244, and col. 29 lines 11-36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa to include the plurality second cylinders of two lines adjacent to each other in a second direction perpendicular to the first direction are arranged in a zigzag manner in the first direction with an offset of a 1/2 pitch in the first direction and a partition wall pillar arranged between the second cylinders adjacent to each other in the first direction as taught Hinoue so that the column shaped vertical electrodes and variable resistance films can be located closer together to increase memory density.
The above stated combination of Ozawa and Hinoue does not disclose a partition wall pillar having a shape of a third cylinder is arranged between the plurality of second cylinders adjacent to each other in the first direction and the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Lue discloses a partition wall pillar (Isolation pillar, See figs. 2, 5B, ref. nos. 28, 29 and paragraph 45) having a shape of a third cylinder (the isolation pillars are shown in figures 2 and 5B having a shape of a cylinder, See fig. 2, 5B, ref. nos. 28, 29) is arranged between the second cylinders adjacent to each other in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa and Hinoue to a partition wall pillar having a shape of a third cylinder is arranged between the second cylinders adjacent to each other in the first direction as taught Lue in order to isolated neighboring vertical electrodes and variable resistance films.
The above stated combination of Ozawa, Hinoue, and Lue does not disclose the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other.
Lue discloses the gate stack structure has a split plate electrode shape (the even word line structure and the odd word line structure form a split plate electrode shape, See fig. 13, ref. nos. 200, 201 and paragraph 79), each layer of the gate electrode of the gate stack structure having a first plate electrode (the even word line structure is in contact with the left sidewalls of the active pillars, See fig. 13, ref. nos. 200, 202-1 through 202-5, 208-1 through 208-5) and a second plate electrode (the odd word line structure is in contact with the right sidewalls of the active pillars, See fig. 13, ref. nos. 200, 202-1 through 202-5, 208-1 through 208-5) in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other (the even word line structure and the odd word line structure have word line extensions into the array of active pillars that are interdigitated, See fig. 13, ref. nos. 200, 201, and paragraph 79).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) vertical memory device of Ozawa, Hinoue, and Lue to include the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other as taught Lue in order to reduce the area constraints for word line drivers by driving word lines with a comb structure instead of driving each word line individually.
Regarding Claim 13:
The above stated combination of Ozawa, Hinoue, and Lue discloses the plurality of second cylinders (active pillars, See Lue, fig. 5B, ref. nos. 80-2, 80-3, and paragraph 56) and the third cylinder partially (Isolation pillar, See Lue figs. 5B, ref. no. 29 and paragraph 45) overlap each other in the first direction (See Lue fig. 5B, ref. nos. 29, 80-2, 80-3. The examiner also notes the Hinoue teaches each memory opening cuts through a segment of each etch stop sacrificial line, See Hinoue fig. 15B, ref. nos. 49, 242, and col. 29 lines 53-57); a horizontal cross section of each the plurality of second cylinder has a circular shape (See Lue, fig. 5B, ref. nos. 80-2, 80-3, and paragraph 56); and a horizontal cross section of the third cylinder comprises a concave portion at opposite sides thereof in the first direction (See Lue figs. 5B, ref. no. 29).
Allowable Subject Matter
Claims 3-4, 7-8, and 14-16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for indication of allowable subject matter: with respect to claim 3, the disclosures and illustrations of Ozawa, Hinoue, and Lue as discussed above fail to teach or suggest the limitations of claims 3 because Ozawa does not disclose on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines of the plurality of electrode structures at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Additionally, Hinoue does not disclose on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines of the plurality of electrode structures at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Further, Lue does not disclose on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines of the plurality of electrode structures at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Ozawa, Hinoue, and Lue to teach and/or suggest the limitations of claims 3, thus claim 3 includes allowable subject matter. Claim 4 depends from claim 3, and thus, claim 4 also includes allowable subject matter because claim 4 includes the subject matter of claim 3.
With respect to claim 7, the disclosures and illustrations of Ozawa, Hinoue, and Lue as discussed above fail to teach or suggest the limitation of claims 7 because Ozawa does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Additionally, Hinoue does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Further, Lue does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Ozawa, Hinoue, and Lue to teach and/or suggest the limitations of claims 7, thus claim 7 includes allowable subject matter. Claim 8 depends from claim 7, and thus, claim 8 also includes allowable subject matter because claim 8 includes the subject matter of claim 7.
With respect to claim 14, the disclosures and illustrations of Ozawa, Hinoue, and Lue as discussed above fail to teach or suggest the limitations of claim 14 because Ozawa does not on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Additionally, Hinoue does not disclose on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Further Lue does not disclose on the plane, a trim pattern having an inverted L shape or an L shape is arranged at edges of the plurality of lines at opposite sides in the first direction, the trim pattern is composed of a same material as the partition wall pillar. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Ozawa, Hinoue, and Lue to teach and/or suggest the limitations of claim 14. Therefore, claim 14 includes allowable subject matter.
With respect to claim 15, the disclosures and illustrations of Ozawa, Hinoue, and Lue as discussed above fail to teach or suggest the limitations of claim 15 because Ozawa does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Additionally, Hinoue does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Further, Lue does not disclose a first carbon layer arranged between the first electrode and the switching material layer and a second carbon layer arranged between the gate electrode and the switching material layer. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Ozawa, Hinoue, and Lue to teach and/or suggest the limitations of claims 15, thus claim 15 includes allowable subject matter. Claim 16 depends from claim 15, and thus, claim 15 also includes allowable subject matter because claim 16 includes the subject matter of claim 15.
Response to Arguments
Applicant's arguments filed July 22, 2026 have been fully considered but they are not persuasive.
The applicant’s argument that the combination of Ozawa, Hinoue, and Lue does not disclose the gate stack structure has a split plate electrode shape, each layer of the gate electrode of the gate stack structure having a first plate electrode and a second plate electrode in contact with opposite sidewalls of the plurality of electrode structures in the second direction, the first plate electrode and the second plate electrode each having a comb shape crossed with each other is not persuasive because this limitation is taught by Lue, as discussed above.
The applicant’s arguments with respect to the proposed combination of the cited prior art not disclosing or suggested each and every limitation of claim 6 fails to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
