Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim limitations “logic block to receive,” “logic block to select,” “logic block to determine,” “transfer engine to receive,” “transfer engine to write,” and “transfer engine to generate,” have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because they use generic placeholder(s) “logic block,” and “engine” coupled with functional language “receive,” “select,” “determine,” “write,” and “generate,” without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder(s) is not preceded by a structural modifier.
Since the claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claims 31-39 have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows lack of sufficient and adequate structure (or material or algorithm) for performing the above functions.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 31-39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 31-39 are rejected under 112(b) because the specification does not disclose adequate and sufficient structure (or material or acts or algorithm) for performing the recited functions (invoking the 112, sixth paragraph) in the claims resulting in no definite boundaries.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-24, 26-28, 31-34, 36-38, and 40 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Boucher et al. (US 20080126553).
Regarding claim 21, Boucher discloses a method, comprising:
receiving, by a network interface controller (NIC), a request to read matching results associated with a first packet of a multi-packet message and stored in a data structure indicating a state of a respective message, the request associated with a subsequent packet of the multi-packet message (All received message frames are examined 53 by the INIC comparator circuits to determine whether they match a CCB held by the CPD. CPD 30 checks to see whether the word that summarizes the fast-path candidate matches a CCB held in a cache 62. when a subsequent packet from the same connection as the initial packet is received from the network 25 by CPD 30, the packet headers and data are validated by the receive logic 32, and the headers are parsed to create a summary of the message packet and a hash for finding a corresponding CCB, the summary and hash contained in a word or words. The word or words are temporarily stored in memory 60 along with the packet. The processor 55 checks for a match between the hash and each CCB that is stored in the cache 62 and, finding a match; [0057, 0060-0061]);
placing the request in a queue of a plurality of queues (Requests which utilize the queues include Processor Request 802, Transmit Sequencer Request 804, and Receive Sequencer Request 806; [0100]);
checking, for a respective queue of the plurality of queues, an indicator of whether to allow the respective queue to access the matching results; determining, based on the indicator, that the respective queue is allowed to access the matching results (Determining which of these various requests will get to use the queue manager in the next cycle is handled by priority logic Arbiter 815. After Arbiter 815 has selected the next operation to be performed, the variables of QRAM 825 are fetched and modified according to the selected operation by a QALU 828, and an SRAM Read Request 830 or an SRAM Write Request 840 may be generated; [0100-0101]); and
granting, to the respective queue, access to the matching results in response to determining that the respective queue is allowed to access the matching results (The status is fed to Arbiter 815 to signal that the operation previously requested has been fulfilled. The Status Register 822 updates the four queue registers to reflect the new status of the queue that was accessed. Similarly updated are SRAM Addresses 833, Body Write Request 835 and Body Read Requests 838, which are accessed via DMA to and from SRAM head and tails for that queue. Alternatively, various processes may wish to write to a queue, as shown by Q Write Data 844; [0101]).
Regarding claim 22, Boucher discloses selecting the queue in which the request is placed (Selects the queue to which the freed buffer descriptors will be written once the packet transmission has been terminated, either successfully or unsuccessfully. 7) Bits 14:10 (name: XmtQId). Selects the queue from which the transmit buffer descriptors will be fetched for data packets. 8) Bits 09:05 (name: CtrlQId). Selects the queue from which the transmit buffer descriptors will be fetched for control packets; [0141]).
Regarding claim 23, Boucher discloses wherein selecting the queue comprises applying a hash function to at least one of: an index of an entry in the data structure; and a number of a traffic class associated with the request (The INIC 200 in this embodiment can support up to 256 CCBs which are maintained in a table in the DRAM 460. There is also, however, a CCB index in hash order in the SRAM 440 to save sequential searching. Once a hash has been generated, the CCB is cached in SRAM, with up to sixteen cached CCBs in SRAM in this example. Allocation of the sixteen CCBs cached in SRAM is handled by a least recently used register, described below. These cache locations are shared between the transmit 484 and receive 486 processors so that the processor with the heavier load is able to use more cache buffers. There are also eight header buffers and eight command buffers to be shared between the sequencers; [0089]).
Regarding claim 24, Boucher discloses determining a set of qualified queues in response to checking the indicator; arbitrating the set of qualified queues based on a scheduling algorithm; and allowing a request placed in a respective qualified queue to obtain the corresponding matching results (Determining which of these various requests will get to use the queue manager in the next cycle is handled by priority logic Arbiter 815. The status is also fed to Arbiter 815 to signal that the operation previously requested has been fulfilled, inhibiting duplication of requests; [0100-0101]).
Regarding claim 26, Boucher discloses receiving, by an inbound transfer engine of the NIC, the first packet of the multi-packet message; storing the state of the multi-packet message in the matching results of the data structure (received message frames are examined 53 by the network microprocessor or INIC comparator circuits to determine whether they match a CCB held by the CPD; [0057].
when a message packet is received from the remote host 22 via network 25, the packet enters hardware receive logic 32 of the CPD 30, which checksums headers and data, and parses the headers, creating a word or words which identify the message packet and status; [0059]);
receiving, by the inbound transfer engine of the NIC, the subsequent packet (when a subsequent packet from the same connection as the initial packet is received from the network 25 by CPD 30, the packet headers and data are validated by the receive logic 32, and the headers are parsed to create a summary of the message packet and a hash for finding a corresponding CCB, the summary and hash contained in a word or words. The word or words are temporarily stored in memory 60 along with the packet. The processor 55 checks for a match between the hash and each CCB that is stored in the cache 62; [0061]); and
generating, by the inbound transfer engine, the request to read the matching results associated with the subsequent packet of the multi-packet message (Requests which utilize the queues include Processor Request 802, Transmit Sequencer Request 804, and Receive Sequencer Request 806. Other requests for the queues are DRAM to SRAM Request 808 and SRAM to DRAM Request 810, which operate on behalf of the queue manager in moving data back and forth between the DRAM and the SRAM head or tail of the queues. Determining which of these various requests will get to use the queue manager in the next cycle is handled by priority logic Arbiter 815. To enable high frequency operation the queue manager is pipelined, with Register A 818 and Register B 820 providing temporary storage, while Status Register 822 maintains status until the next update. The queue manager reserves even cycles for DMA, receive and transmit sequencer requests and odd cycles for processor requests; [0100]).
Regarding claim 27, Boucher discloses wherein checking the indicator comprises: determining that a bit at a head of the respective queue indicates that the matching results are available to be used when processing a remainder of the associated message (Comparators 920 compare the signal from that line 935 with the block numbers and comparator C8 provides a true output for the block R8 that matches the signal, while all the other comparators output false. Logic circuits 930, under control from the processor 470, use select lines 959 to choose the input from line 935 for MUX15, storing the number 12 in the MRU block R15. Logic circuits 930 also send signals along the pairs of select lines for MUX8 and higher multiplexors, aside from MUX15, to shift their output one block to the left, by selecting as inputs to each multiplexor MUX8 and higher the value that had been stored in register blocks one block to the right (R9-R15); [0108]);
determining that a credit is available to return the matching results; and responsive to determining that the bit is set and that the credit is available, determining that the respective queue is allowed to access the matching results (queue manager interface 2205 of the receive sequencer always attempts to maintain a free buffer descriptor 2207 for use by the packet processing sequencer 2204. Bit 2208 is a ready bit that indicates that free-buffer descriptor 2207 is available for use by the packet processing sequencer 2204. If queue manager interface 2205 does not have a free buffer descriptor (bit 2208 is not set), then queue manager interface 2205 requests one from queue manager 2103 via request line 2209. (Request line 2209 is actually a bus which communicates the request, a queue ID, a read/write signal and data if the operation is a write to the queue.); [0116]).
Regarding claim 28, Boucher discloses wherein the multi-packet message comprises at least one of: a PUT message; a GET message; and an atomic memory operations (AMO) message (hardware processing of message packets received by INIC 150 from network 155 is shown in more detail in FIG. 7; [0067]).
Regarding claim 31, the claim is interpreted and rejected for the reasons cited in claim 21. Furthermore, Boucher discloses a network interface controller (NIC) (FIG. 7; hardware logic for the INIC; [0030]), comprising:
a storage device to store a data structure; and a message state table logic block (The processed headers and data from the received packet are then stored in INIC storage 185, as well as the word or words summarizing the headers and status of the packet; [0066]).
Regarding claim 32, the claim is interpreted and rejected for the reasons cited in claim 23.
Regarding claim 33, the claim is interpreted and rejected for the reasons cited in claim 24.
Regarding claim 34, the claim is interpreted and rejected for the reasons cited in claim 26.
Regarding claim 36, the claim is interpreted and rejected for the reasons cited in claim 26.
Regarding claim 37, the claim is interpreted and rejected for the reasons cited in claim 27.
Regarding claim 38, the claim is interpreted and rejected for the reasons cited in claim 28.
Regarding claim 40, the claim is interpreted and rejected for the reasons cited in claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Boucher et al. (US 20080126553) in view of Raindel et al. (US 20150288624).
Regarding claim 29, Boucher does not expressly disclose receiving, by the NIC, a retry request to read matching results associated with a single-packet GET message, wherein the retry request is associated with a retry packet, and wherein an entry in the data structure stores matching results for the single packet GET message.
In an analogous art, Raindel discloses receiving, by the NIC, a retry request to read matching results associated with a single-packet GET message, wherein the retry request is associated with a retry packet, and wherein an entry in the data structure stores matching results for the single packet GET message (In response to receiving the doorbell message, NIC logic 68 sends a get work request message 208 to the host, to retrieve the respective work request. The NIC receives respective work request 212, and then sends a get message request 216 to accelerator 46. In some embodiments, the NIC retrieves the work request (arrows 208 and 212) using DMA without involving the host. In response to receiving message 216, GPU 80 copies the respective message 220 from queue 140 to sender buffer 64 in the NIC. In an embodiment, copying the message is done using DMA without involving the GPU. NIC logic 68 then delivers the message to the network (indicated by message sending 224); [0050]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Raindel into the system of Boucher in order to achieve low processing latency by starting to process a received massage independently of updating the control indices of the completion notifications queue by the host (Raindel; [0044]).
Regarding claim 30, the combination of Boucher and Raindel, particularly Raindel discloses returning, to an inbound transfer engine of the NIC: an index of the entry in the data structure storing the matching results associated with the single-packet GET message; and an indicator of the retry packet (The work queue stores requests to send messages to the network. In response to receiving the doorbell message, the NIC gets or retrieves the corresponding work request from the host and initiates a direct copy of the message from the accelerator memory to the sending buffer of the NIC. the structures and the management of the queue of the received messages may be divided between the accelerator and the host in various ways. In some embodiments, the accelerator manages the notifications queue part, which requires only small computational resources, whereas the host manages the control indices of the queue, a task that is typically not performed well by accelerators; [0024-0026]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Raindel into the system of Boucher in order to achieve low processing latency by starting to process a received massage independently of updating the control indices of the completion notifications queue by the host (Raindel; [0044]).
Claim(s) 39 is rejected under 35 U.S.C. 103 as being unpatentable over Boucher et al. (US 20080126553) in view of Talla et al. (US 20100325495).
Regarding claim 39, Boucher does not expressly disclose wherein the message state table logic block is further to: receive a notification of an error associated with the multi-packet message, the notification comprising an error response packet associated with the multi-packet message; and log the error associated with the multi-packet message.
In an analogous art, Talla discloses wherein the message state table logic block is further to: receive a notification of an error associated with the multi-packet message, the notification comprising an error response packet associated with the multi-packet message; and log the error associated with the multi-packet message (Interface Slave 604 sends an error message 620A to an Interface Master 602, responsive to the Interface Slave 604 experiencing an error with a shared resource. Responsive to receiving error message 620A, Interface Master 602 may send a LINK_DOWN message 624A to one or more Interface Slaves 604, and, in some embodiments, may reset the shared resource, such as NIC 552. In a further embodiment, IM 602 may record an entry in Error Log 603 with a timestamp; [0235]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Talla into the system of Boucher in order to reduce errors and improve efficiency by resetting resources at a core experiencing a failure without coordination with other cores (Talla; [0004]).
Allowable Subject Matter
Claims 25 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 25, if rewritten in independent form including all of the limitations of the base claim and any intervening claims, would comprise a combination of elements which is not taught by the prior art of record. The same reasoning applies to claim 35 mutatis mutandis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Flajslik et al. (US 20170093770), “TECHNOLOGIES FOR RECEIVE SIDE MESSAGE INSPECTION AND FILTERING.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OUSSAMA ROUDANI whose telephone number is (571)272-4727. The examiner can normally be reached 8:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, UN C CHO can be reached on (571) 272 7919. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OUSSAMA ROUDANI/ Primary Examiner, Art Unit 2413
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