Prosecution Insights
Last updated: August 17, 2026
Application No. 18/529,320

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§Other
Filed
Dec 05, 2023
Priority
Aug 11, 2023 — RE 10-2023-0105301
Examiner
HSIEH, HSIN YI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
51%
Grant Probability
Moderate
1-2
OA Rounds
1y 2m
Est. Remaining
56%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allowance Rate
326 granted / 640 resolved
-17.1% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
26 currently pending
Career history
695
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.2%
-2.8% vs TC avg
§102
20.1%
-19.9% vs TC avg
§112
40.7%
+0.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I of Figs. 10A-10B in the reply filed on 06/29/2026 is acknowledged. Claims 10, 12, 15, 17-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/29/2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/05/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 13, 16 and 22-25 is/are rejected under 35 U.S.C. 102a(1)/a(2) as being anticipated by Hwang et al. (US 2011/0180941 A1). Regarding claim 13, Hwang et al. teaches in Figs. 19A, 19B, 25A and 25B (a modified embodiment of the embodiment 2; [0134, 0097]), a semiconductor device (3D semiconductor devices; [0005]) comprising: a first support (105; Fig. 25B, [0046]) including a first inclined surface (the left side surface of 105; Fig. 25B, [0046]); a first gate structure (175/135; [0101, 0076]) including first insulating layers (135 of silicon oxide; [0076]) and first conductive layers (175; [0101]) alternately stacked along the first inclined surface (the left side surface of 105); a second support (205; Fig. 25B, [0064]) positioned over or on the first support (105) and including a second inclined surface (the left side surface of 205; Fig. 25B); a second gate structure (275/235; [0108, 0076]) including second insulating layers (235 of silicon oxide; [0076]) and second conductive layers (275; [0108]) alternately stacked along the second inclined surface (the left side surface of 205); a channel structure (150/250/P1; Fig. 19B, [0071, 0083]) extending through the second gate structure (275/235) and the first gate structure (175/135); a first contact plug (the P1s connecting to 175; Fig. 19B, [0083]) including a top surface (the top surface of the P1s connecting to 175) positioned at substantially the same level as a top surface of the channel structure (the top surface of 150/250/P1; see Fig. 19B), on the first gate structure (175/135); and a second contact plug (the P1s connecting to 275; Fig. 19A, [0083]) connected to at least one second conductive layer (275) among the second conductive layers (275), on the second gate structure (275/235). Regarding claim 16, Hwang et al. teaches the semiconductor device of claim 14, further comprising: a third contact plug (M1; Fig. 19B, [0083]) positioned over or on the first contact plug (the P1s connecting to 175) and connected to the first contact plug (the P1s connecting to 175; Fig. 19B). Regarding claim 22, Hwang et al. teaches the semiconductor device of claim 13, wherein the first gate structure (175/135) includes a first cell region (175/135 in CAR; Fig. 19B, [0046]) in which the first conductive layers (175) extend in a first direction (the horizontal direction in Fig. 19B) and a first contact region (175/135 in CNR; Fig. 19B, [0046]) extending along the first inclined surface (the left side surface of 105; see Fig. 25B), wherein the second gate structure (275/235) includes a second cell region (275/235 in CAR; Fig. 19B, [0046]) in which the second conductive layers (275) extend in the first direction (the horizontal direction in Fig. 19B) and a second contact region (275/235 in CNR; Fig. 19B, [0046]) extending along the second inclined surface (the left side surface of 205; see Fig. 25B), wherein the first contact region (175/135 in CNR) and the second contact region (275/235 in CNR) overlap in a third direction (the vertical direction in Fig. 19B) crossing the first direction (the horizontal direction in Fig. 19B). Regarding claim 23, Hwang et al. teaches the semiconductor device of claim 22, wherein a top surface of the first conductive layers (175) is positioned at substantially the same level, in the first contact region (175/135 in CNR). Regarding claim 24, Hwang et al. teaches the semiconductor device of claim 22, wherein a top surface of the second conductive layers (275) is positioned at substantially the same level, in the second contact region (275/235 in CNR). Regarding claim 25, Hwang et al. teaches the semiconductor device of claim 13, wherein the first inclined surface (the left side surface of 105) and the second inclined surface (the left side surface of 205) have an inclination of an acute angle (see Fig. 25B). Allowable Subject Matter Claims 1-9 and 11 are allowed. Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of "a first contact plug extending through the second gate structure and connected to at least one first conductive layer among the first conductive layers" as recited in claim 1 and “wherein the first contact plug extends through the second gate structure and is connected to at least one first conductive layer among the first conductive layers” of claim 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra V Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HSIN YI HSIEH/Primary Examiner, Art Unit 2899 7/11/2026
Read full office action

Prosecution Timeline

Dec 05, 2023
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §Other (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12696592
LIGHT EMITTING DEVICE
3y 8m to grant Granted Jul 28, 2026
Patent 12690296
METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT
2y 11m to grant Granted Jul 21, 2026
Patent 12677507
LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT
4y 12m to grant Granted Jul 07, 2026
Patent 12666723
THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING ESD PROTECTION CIRCUIT
5y 3m to grant Granted Jun 23, 2026
Patent 12652828
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES
4y 5m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
51%
Grant Probability
56%
With Interview (+5.5%)
3y 11m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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