Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 17 is objected to because of the following informalities: Claim 17 is labeled twice in claims. One of them should be labeled 20. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 19 recites typo Error! Reference Source not found should be deleted. Claim 19 is interpreted as dependent on claim 18. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 18 recite the limitation “a quantity of the set of vias is based on satisfying a signal integrity threshold associated with the at least one signal pin of the plurality of signal pins” is indefinite since there could be an unlimited possibility of thresholds for the signal integrity based of an unlimited number of vias. Appropriate correction is required.
Claim 7 recites the limitation “a pattern of the set of vias is based on satisfying the signal integrity threshold” is indefinite since there could be an unlimited possibility of thresholds for the signal integrity based of an unlimited number of patterns. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1, 7-15, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over in view of Liu et al. (CN 211829260 U; published in 10/30/2020) in view of Peng et al. (US 2019/0280434 A1) hereinafter Peng.
Regarding claim 1, Liu discloses a printed circuit board (2;Fig.2) comprising: a plurality of layers (Fig.7); a footprint (211;Fig.6) fabricated on an outer layer of the plurality of layers (top layer of 21); a plurality of signal pins (121) and a pin (121), wherein the plurality of signal pins and the pin are included in the footprint (see 122 and 24 in Fig.3); and a ground guard (212) comprising: a set of ground pads (see 211 and 213); a plurality of ground layers (27) of the plurality of layers; and a set of vias (28 and 281), wherein: the set of vias are located on the set of ground pads (see Fig.6) and configured to connect the plurality of ground layers (27); the set of vias are located between the pin (second 121) and at least one signal pin (first 121) of the plurality of signal pins in a direction parallel to a plane of the plurality of layers (see vias extending in the planar direction of 21); and a quantity of the set of vias is based on satisfying a signal integrity threshold associated with the at least one signal pin of the plurality of signal pins( a certain signal integrity threshold is met when the plurality of ground vias on 212 and 211 is placed as shown in Fig.5).
Liu is silent with respect to the pin being a ground pin.
Peng discloses a ground pin (320; Fig.6-7; [0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Peng to modify the pin of Liu in order to perform various circuit operations.
Regarding claim 7, Liu wherein a pattern of the set of vias is based on satisfying the signal integrity threshold (a certain signal integrity threshold is met when the pattern of ground vias on 212 and 211 is placed as shown in Fig.5)
Regarding claim 8, Liu discloses the claimed invention except for a distance between two or more vias of the set of vias is based on a signal frequency associated with the at least one signal pin of the plurality of signal pins. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a distance between two or more vias of the set of vias is based on a signal frequency associated with the at least one signal pin of the plurality of signal pins in order to reduce noise transmitting through the signal lines, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Regarding claim 9, Liu discloses wherein the set of vias comprise a plurality of through hole vias (see 281; Fig.8) extending from a top layer of the plurality of layers to a bottom layer of the plurality of layers (see Fig.8).
Regarding claim 10, Liu discloses another intermediate layer is a last intermediate layer of the plurality of layers (see layer 272 in Fig.7).
Regarding claim 11, Liu discloses wherein the set of vias comprise at least one of: one or more micro vias (see 281); and one or more through-hole vias (23;Fig.8).
Regarding claim 12, Liu discloses wherein the set of vias comprise one or more non signal-carrying vias (see 281).
Regarding claim 13, Liu discloses, wherein the set of vias comprise: one or more first vias of a first size (see 281) and one or more second vias of a second size (see 23).
Regarding claim 14, a modified Liu discloses wherein each of the plurality of signal pins is located an equal distance from the ground pin (see 121 equal distance from each other).
Regarding claim 15, aa modified Liu discloses wherein the plurality of signal pins comprise four signal pins (see four 121 in Fig.3).
Regarding claim 18, Liu discloses an apparatus comprising: a printed circuit board (2;Fig.5), wherein the printed circuit board comprises: a plurality of layers (see Fig.7); a footprint fabricated on an outer layer ( see 211 and 212) of the plurality of layers; a plurality of signal pins (see 121) and a pin (121), wherein the plurality of signal pins and the pin are included in the footprint (see footprint on 21); and a ground guard comprising: a set of ground pads (211 and 212;Fig.6); a plurality of ground layers (see 27;Fig.8) of the plurality of layers; and a set of vias (281), wherein: the set of vias are located on the set of ground pads and connect the plurality of ground layers (see Fig.8); the set of vias are located between the pin and at least one signal pin of the plurality of signal pins in a direction parallel to a plane of the plurality of layers (see lined up vias of 281) ; and a quantity of the set of vias is based on satisfying a signal integrity threshold associated with the at least one signal pin of the plurality of signal pins ( a certain signal integrity threshold is met when the plurality of ground vias on 212 and 211 is placed as shown in Fig.5).
Allowable Subject Matter
Claim 20 is allowed over prior art of record.
Claim 2-6,16 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claim 2-6, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a solder mask disposed on the outer layer of the plurality of layers, wherein: a first opening of the solder mask corresponds to a boundary of a ground via included in the set of vias; at least a portion of a second opening of the solder mask is located between two signal pins of the plurality of signal pins; and the solder mask overlaps at least a portion of a path corresponding to the set of ground pads " in combination with the remaining limitations of the claim 1.
Regarding claim 16, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein: the plurality of signal pins are arranged based on a square shape, a rectangular shape, a diamond shape, a circular shape, or an oval shape; and the plurality of signal pins surround the ground pin " in combination with the remaining limitations of the claim 1.
Regarding claim 19, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a solder mask disposed on the outer layer of the plurality of layers, wherein: a first opening of the solder mask corresponds to a boundary of a ground via included in the set of vias; at least a portion of a second opening of the solder mask is located between two signal pins of the plurality of signal pins; and the solder mask overlaps at least a portion of a path corresponding to the set of ground pads " in combination with the remaining limitations of the claim 19.
Regarding claim 20, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach
" forming a ground guard of the multilayer assembly, the ground guard comprising a set of ground pads, a plurality of ground layers of the plurality of intermediate layers, and a set of vias, wherein: the set of vias are located on the set of ground pads and connect the plurality of ground layers; the set of vias are located between a ground pin and at least one signal pin of a plurality of signal pins in a direction parallel to a plane of the multilayer assembly; the ground pin and the plurality of signal pins are included in a footprint fabricated on an outer conductive layer of the set of outer conductive layers; and forming the set of vias is based on satisfying a signal integrity threshold associated with the at least one signal pin; and forming a solder mask on the outer conductive layer, wherein: a first opening of the solder mask corresponds to a boundary of a ground via included in the set of vias; at least a portion of a second opening of the solder mask is located between two signal pins of the plurality of signal pins; and the solder mask overlaps at least a portion of a path corresponding to the set of ground pads” in combination with the remaining limitations of the claim 20.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848