DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to amendment of application, submitted 2-JAN-2026.
Claims 1-4, 6-11, 13, 16-18 are amended.
Claims 1-20 remain pending.
Applicant’s amendments to the claims have overcome each and every rejection under 35 U.S.C. 101 previously set forth in the final office action mailed 1-OCT-2025
Although not part of Applicant’s arguments, the amendments to claim 4 also overcome the objection to claim 4 previously set forth. The objection to claim 4 has been withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2-JAN-2026 has been entered.
Response to Arguments
Applicant’s arguments, see page 10, filed 2-JAN-2026, with respect to the rejections under 35 U.S.C. 101 have been fully considered and are persuasive due to amendments. The rejections under 35 U.S.C. 101 have been withdrawn.
Applicant amended the independent claims to include claim elements which Examiner identified to render dependent claims eligible in a previous Office Action. Therefore, the independent claims and the claims dependent upon them are eligible.
Applicant’s arguments, see pages 11-13, filed 2-JAN-2026, with respect to the rejection(s) of claims 1, 8, 16 under 35 U.S.C. 103 have been fully considered and are persuasive due to amendments. Therefore, the rejection has been withdrawn.
Applicant’s further arguments to claims 1, 8, and 16 are based on newly amended limitations to the independent claims. Applicant’s arguments center around the prior art not addressing the newly amended limitations. Therefore, the office action is updated to address the new limitations below.
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Claim Objections
Claim 16 is objected to because of the following informalities:
In lines 23-24, “write the data into unprogrammed memory cell page” should read “write the data into an unprogrammed memory cell page” (bolded for emphasis).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1: The newly amended limitation of “performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting performing an erase page check wherein a target parameter is not greater than the first threshold, is not supported by the originally filed written description, and constitutes new matter.
In the original claim 1, and within the specification in Fig. 8 and [0111], the erase page check is specifically omitted when the target parameter is not greater than a first threshold, and a case where the erase page check is performed when the target parameter is not greater than the first threshold would not be supported.
Similarly, the newly amended limitation of “writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting writing data to a second non-adjacent word line to the first word line occurring when the erase page check is passed is not supported by the originally filed written description, and constitutes new matter.
In the original claim 6, from which this limitation was rolled up from, this non-adjacent word line writing only occurs when the erase page check fails, as shown by S170 and S180 in Fig. 8, S220 in Fig. 12, and Figs. 13-14, and the non-adjacent writing does not occur when the erase page check passes as currently claimed. This is further supported by S150 and S160 in Fig. 8, S210 in Fig. 9, and the examples from Fig. 10 and Fig. 11, which describe sending the first write command, which results in writing to the adjacent word line without any kind of non-adjacency, when the erase page check passes. Therefore, the invention as originally filed and claimed is understood to write to non-adjacent word lines only when the erase page check fails (and the number of programmed word lines is greater than a threshold), and is further understood to only write to word lines that are not non-adjacent when the erase page check passes.
Since claims 2-7 depend upon claim 1, claims 2-7 inherit these deficiencies and are rejected for the same reasons.
Regarding claim 8: The newly amended limitation of “performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting performing an erase page check wherein a target parameter is not greater than the first threshold, is not supported by the originally filed written description, and constitutes new matter.
In the original claim 8, and within the specification in Fig. 8 and [0111], the erase page check is specifically omitted when the target parameter is not greater than a first threshold, and a case where the erase page check is performed when the target parameter is not greater than the first threshold would not be supported.
Similarly, the newly amended limitation of “in response to the first memory cell block passing the erase page check, writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting writing data to a second non-adjacent word line to the first word line occurring when the erase page check is passed is not supported by the written description, and constitutes new matter.
In the original claim 13, from which this limitation was rolled up from, this non-adjacent word line writing only occurs when the erase page check fails, as shown by S170 and S180 in Fig. 8, S220 in Fig. 12, and Figs. 13-14, and the non-adjacent writing does not occur when the erase page check passes as currently claimed. This is further supported by S150 and S160 in Fig. 8, S210 in Fig. 9, and the examples from Fig. 10 and Fig. 11, which describe sending the first write command, which results in writing to the adjacent word line without any kind of non-adjacency, when the erase page check passes. Therefore, the invention as originally filed and claimed is understood to write to non-adjacent word lines only when the erase page check fails (and the number of programmed word lines is greater than a threshold), and is further understood to only write to word lines that are not non-adjacent when the erase page check passes.
Since claims 9-15 depend upon claim 8, claims 9-15 inherit these deficiencies and are rejected for the same reasons.
Regarding claim 16: The newly amended limitation of “perform an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting performing an erase page check wherein a target parameter is not greater than the first threshold, is not supported by the originally filed written description, and constitutes new matter.
In the original claim 16, and within the specification in Fig. 8 and [0111], the erase page check is specifically omitted when the target parameter is not greater than a first threshold, and a case where the erase page check is performed when the target parameter is not greater than the first threshold would not be supported.
Similarly, the newly amended limitation of “in response to the first memory cell block passing the erase page check, send a first write command to the memory, the first write command instructing a peripheral circuit of the memory to write the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines” (bolded for emphasis) was not described in the specification or previously presented claims. That is, the newly amended claim reciting writing data to a second non-adjacent word line to the first word line occurring when the erase page check is passed is not supported by the written description, and constitutes new matter.
In the original claim 18, from which this limitation was rolled up from, this non-adjacent word line writing only occurs when the erase page check fails, as shown by S170 and S180 in Fig. 8, S220 in Fig. 12, and Figs. 13-14, and the non-adjacent writing does not occur when the erase page check passes as currently claimed. This is further supported by S150 and S160 in Fig. 8, S210 in Fig. 9, and the examples from Fig. 10 and Fig. 11, which describe sending the first write command, which results in writing to the adjacent word line without any kind of non-adjacency, when the erase page check passes. Therefore, the invention as originally filed and claimed is understood to write to non-adjacent word lines only when the erase page check fails (and the number of programmed word lines is greater than a threshold), and is further understood to only write to word lines that are not non-adjacent when the erase page check passes.
Since claims 17-20 depend upon claim 16, claims 17-20 inherit these deficiencies and are rejected for the same reasons.
Relevant Prior Art Cited by Examiner
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KIM et al., U.S. Pub. No. 2015009558, teaches a system which, during a sudden power-off event where reliability of a previous write cannot be guaranteed, searching for a boundary page, checking the erase states of unprogrammed pages, performing dummy programming at a boundary page, then proceeding to write normally after the boundary page, which also includes embodiments where dummy programming is performed for additional word lines.
MOON et al., U.S. Pub. No. 20140369124, teaches a system which adjusts erase verification voltages according to wear factors including an erase count of a block.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(a), set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter:
The reasons for allowability of claim 1 are the prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “An operation method of a memory controller, comprising: in response to a data write instruction, determining a first memory cell block into which data is to be written; determining whether a target parameter of the first memory cell block is greater than a first threshold, wherein the target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block; performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold, and wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block: and writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines.”
The closest prior art of record is Shukla, which teaches the in response to a data write instruction, determining a first memory cell block into which data is to be written; determining whether a target parameter of the first memory cell block is greater than a first threshold; performing an erase page check on the first memory cell block; writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, but does not teach the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold… wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block… writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines.
As such, the prior art made of record neither anticipates nor renders obvious the above-recited combinations for at least the reasons specified.
Regarding claim 1: while Shukla teaches a system that, in response to a data write instruction, determines a first memory cell block into which data is to be written, and determines whether a target parameter is greater than a threshold, and performs erase page checks on the memory cell block, and writes data into unprogrammed memory cell pages coupled to a second word line in the block, where there are a number of first word lines that are coupled to programmed memory cell pages in the first memory cell blocks, Shukla does not teach the particular combination of conditions and actions where a target parameter is a placement duration, the erase page check is performed in a case that the target parameter is not greater than the first threshold, where the read voltage to perform the erase page check is determined based on the placement duration, an erase count of the block, or a read count of the block, and writing the data into a non-adjacent word line when the block passes the erase page check.
Other prior art discloses the target parameter being a placement duration, the read voltage to perform the erase page check is determined based on the erase count of the block, and writing the data into a non-adjacent word line, but does not appear to disclose the erase page check being performed when the target parameter is not greater than the first threshold (representing wear), or writing data into a non-adjacent word line when the block passes an erase page check.
Therefore, there is no teaching or motivation that would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention for performing an erase page check in a case where the target parameter is not greater than the first threshold, or writing data into a non-adjacent word line in a case where the block passes an erase page check.
Therefore, a rejection for anticipation by Shukla or obviousness over Shukla in view of the other prior art would be improper.
Claims 2-7 depend on claim 1, and would be allowable for the same reasons.
The reasons for allowability of claim 8 are the prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “A memory controller, comprising: a buffer configured to store a target parameter of a first memory cell block; and a processor configured to: in response to a data write instruction, determine the first memory cell block into which data is to be written; determine whether the target parameter of the first memory cell block is greater than a first threshold, wherein the target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block; performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold, and wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block and in response to the first memory cell block passing the erase page check, writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines.”
The closest prior art of record is Shukla, which teaches the memory controller, comprising: a buffer configured to store a target parameter of a first memory cell block; and a processor configured to: in response to a data write instruction, determining a first memory cell block into which data is to be written; determining whether a target parameter of the first memory cell block is greater than a first threshold; performing an erase page check on the first memory cell block; writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, but does not teach the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold… wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block… writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines.
As such, the prior art made of record neither anticipates nor renders obvious the above-recited combinations for at least the reasons specified.
Regarding claim 8: while Shukla teaches a memory controller, a buffer that stores a parameter, and a processor configured to: in response to a data write instruction, determines a first memory cell block into which data is to be written, and determines whether a target parameter is greater than a threshold, and performs erase page checks on the memory cell block, and writes data into unprogrammed memory cell pages coupled to a second word line in the block, where there are a number of first word lines that are coupled to programmed memory cell pages in the first memory cell blocks, Shukla does not teach the particular combination of conditions and actions where a target parameter is a placement duration, the erase page check is performed in a case that the target parameter is not greater than the first threshold, where the read voltage to perform the erase page check is determined based on the placement duration, an erase count of the block, or a read count of the block, and writing the data into a non-adjacent word line when the block passes the erase page check.
Other prior art discloses the target parameter being a placement duration, the read voltage to perform the erase page check is determined based on the erase count of the block, and writing the data into a non-adjacent word line, but does not appear to disclose the erase page check being performed when the target parameter is not greater than the first threshold (representing wear), or writing data into a non-adjacent word line when the block passes an erase page check.
Therefore, there is no teaching or motivation that would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention for performing an erase page check in a case where the target parameter is not greater than the first threshold, or writing data into a non-adjacent word line in a case where the block passes an erase page check.
Therefore, a rejection for anticipation by Shukla or obviousness over Shukla in view of the other prior art would be improper.
Claims 9-15 depend on claim 8, and would be allowable for the same reasons.
The reasons for allowability of claim 16 are the prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “A memory system, comprising: a memory controller coupled to a memory and is configured to: in response to a data write instruction, determine a first memory cell block into which data is to be written; determine whether a target parameter of the first memory cell block is greater than a first threshold, wherein the target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block; perform an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold, and wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block: and in response to the first memory cell block passing the erase page check, send a first write command to the memory, the first write command instructing a peripheral circuit of the memory to write the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines; and the memory configured to in response to the first write command, write the data into unprogrammed memory cell page coupled to the second word line in the first memory cell block.”
The closest prior art of record is Shukla, which teaches the memory controller coupled to a memory and is configured to: in response to a data write instruction, determining a first memory cell block into which data is to be written; determining whether a target parameter of the first memory cell block is greater than a first threshold; performing an erase page check on the first memory cell block; send a first write command to the memory to write the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block… the memory configured to in response to the first write command, write the data into unprogrammed memory cell page coupled to the second word line in the first memory cell block, but does not teach the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is not greater than the first threshold… wherein a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block… writing, via an instruction provided to a peripheral circuit, the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block, wherein the first memory cell block passes the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block, and the second word line is not adjacent to the first word lines.
As such, the prior art made of record neither anticipates nor renders obvious the above-recited combinations for at least the reasons specified.
Regarding claim 16: while Shukla teaches a memory controller coupled to a memory and is configured to: in response to a data write instruction, determines a first memory cell block into which data is to be written, and determines whether a target parameter is greater than a threshold, and performs erase page checks on the memory cell block, and writes data into unprogrammed memory cell pages coupled to a second word line in the block, where there are a number of first word lines that are coupled to programmed memory cell pages in the first memory cell blocks, Shukla does not teach the particular combination of conditions and actions where a target parameter is a placement duration, the erase page check is performed in a case that the target parameter is not greater than the first threshold, where the read voltage to perform the erase page check is determined based on the placement duration, an erase count of the block, or a read count of the block, and writing the data into a non-adjacent word line when the block passes the erase page check.
Other prior art discloses the target parameter being a placement duration, the read voltage to perform the erase page check is determined based on the erase count of the block, and writing the data into a non-adjacent word line, but does not appear to disclose the erase page check being performed when the target parameter is not greater than the first threshold (representing wear), or writing data into a non-adjacent word line when the block passes an erase page check.
Therefore, there is no teaching or motivation that would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention for performing an erase page check in a case where the target parameter is not greater than the first threshold, or writing data into a non-adjacent word line in a case where the block passes an erase page check.
Therefore, a rejection for anticipation by Shukla or obviousness over Shukla in view of the other prior art would be improper.
Claims 17-20 depend on claim 16, and would be allowable for the same reasons.
Conclusion
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/K.H.P./Examiner, Art Unit 2133
/KHOA D DOAN/Primary Examiner, Art Unit 2133