DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to amendment of application, submitted 23-APRIL-2026.
Claims 1, 5, 8, 12, 16, 18 are amended.
Claims 1-20 remain pending.
Response to Arguments
Applicant’s arguments, see Page 9, filed 23-APRIL-2026, with respect to rejections under 35 U.S.C. 112(a) have been fully considered and are persuasive due to amendments. The rejections under 35 U.S.C. 112(a) have been withdrawn.
Applicant amended the claims to remove a set of conditions and outcomes, which contradicted the conditions and outcomes described in the originally filed instant disclosure, present within the previous set of claims.
Applicant's arguments filed 23-APRIL-2026 have been fully considered but they are not persuasive.
1. With respect to Applicant’s arguments regarding the objection to claim 16, that the claim does not recite the typographical issue, Examiner disagrees. Examiner notes that Applicant appears to be referring to a section of the text different from what Examiner had objected to. As shown in the previous office action, the objection specified lines 23-24, corresponding to the text underlined in the screenshot below which shows the error in the most recent set of claims. Thus, the objection is maintained.
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2. With respect to Applicant’s arguments that the claims are in condition for allowance because the previous office action indicated allowable subject matter if the rejections under 35 U.S.C. 112(a) could be overcome, Examiner respectfully disagrees. As shown in the previous office action and discussed in the latest interview, the subject matter that was rejected under 35 U.S.C. 112(a) for lacking written description in the original disclosure was the same subject matter that was indicated as allowable subject matter. Since the rejected subject matter is the same as the allowable subject matter, by amending to remove the subject matter to overcome the rejection under 35 U.S.C. 112(a), Applicant has necessarily also amended to remove the allowable subject matter, and the reasons for indicating allowable subject matter are rendered moot. The claims are thus rejected over previously applied prior art.
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Claim Objections
Claims 6, 8, 13, 16 are objected to because of the following informalities:
In claim 6 lines 4-5, “third threshold” should instead read “second threshold” to refer back to the number of programmed word lines threshold recited in claim 1 line 18, to maintain consistency with the disclosure.
In claim 8 line 11, “performing” should read “perform”
In claim 8 line 16, “writing” should read “write”
In claim 13 lines 5-6, “third threshold” should instead read “second threshold” to refer back to the number of programmed word lines threshold recited in claim 8 line 21, to maintain consistency with the disclosure.
In claim 16 lines 23-24, “write the data into unprogrammed memory cell page” should read “write the data into an unprogrammed memory cell page” (bolded for emphasis).
In claim 18 line 5, “third threshold” should instead read “second threshold” to refer back to the number of programmed word lines threshold recited in claim 16 lines 20-21, to maintain consistency with the disclosure.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
Claims 1-3, 6, 8-10, 13-14, 16-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over
Shukla et al., U.S. Pub. No. 20160172045 (hereinafter 'Shukla') in view of
Yu et al., U.S. Patent No. 11315649 (hereinafter “Yu”) further in view of
MOON et al., U.S. Pub. No. 20140369124 (hereinafter “Moon”) further in view of
Yang et al., U.S. Pub. No. 20170116075 (hereinafter ‘Yang’)
Regarding claim 1: Shukla teaches An operation method of a memory controller, comprising:
in response to a data write instruction, determining a first memory cell block into which data is to be written; (Fig. 8A Shukla teaches that when programming requests are received at step 520, one or more blocks in which data is to be stored are identified at step 522. See also [0065]).
determining whether a target parameter of the first memory cell block is greater than a first threshold… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is greater than the first threshold (Fig. 19, Shukla teaches a programming operation step 904 that determines if a parameter is higher than a limit, and if it is, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910. See also [0117]))
writing, via an instruction to a peripheral circuit, the data into an unprogrammed memory cell page… in the first memory cell block, wherein the first memory cell block fails the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block and the number of first word lines is less than a second threshold, and the second page is not adjacent to the first programmed pages (Fig. 25, [0040], and [0141-143], Shukla teaches that after disturb errors are detected as in Fig. 19 step 912 (failing the erase page check), the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, and that if the space is not insufficient (number of word lines is less than a threshold), read disturb can be handled by programming into upper pages that are not adjacent to the last programmed pages, as the lower pages which may be adjacent to the last programmed pages are skipped)
Shukla does not appear to explicitly disclose wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block, a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yu teaches wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block or writing (Col 1, lines 52-59, Yu teaches that an erase program interval may be determined for a block, representing a time period elapsed after an erasure of the first block may be determined at the time of receiving a write request).
Shukla and Yu are analogous art because they are from the same field of endeavor, controlling write operations according to memory status.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla and Yu to achieve the method of, in response to a data write instruction, determining a block into which data is to be written, determining whether a target parameter is greater than a first threshold, the target parameter taking into account the time elapsed after an erasure of a block, and programming the data into the block if the target parameter is smaller than the threshold.
One of ordinary skill in the art would have been motivated to make this modification in order to take into account a known characteristic of the memory being degraded when the elapsed time is long as discussed in Yu Col. 1, lines 37-41 “In view of the characteristics of some flash memory devices, in a case where the EPI is long, a threshold voltage distribution characteristic thereof may be degraded, and as a result, the 40 reliability of data may be degraded.”.
While Shukla/Yu teach the read count (Shukla [0116]), placement duration (Yu Col. 19, lines 15-20), and an erase count (Shukla [0093]) being used to adjust verification operations to account for degradation, Shukla/Yu do not appear to explicitly disclose a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Moon teaches a read voltage to perform the erase page check is determined based on… an erase count of the first memory cell block ([0126], Moon teaches that the level of an erase verification voltage may be determined according to the erase mode. Furthermore, in [0103-0104], Moon teaches that access modes (including the erase mode) are determined based on a cumulative effective wear of a block, which is indicative of the number of erase cycles performed on a memory block. Therefore, the level of an erase verification voltage (used to verify erase states) are determined based on an erase count of the first memory cell block.)
Shukla/Yu and Moon are analogous art because they are from the same field of endeavor, managing memory devices.
Since Shukla/Yu similarly teach read count, placement duration, and erase count all being determining wear factors for performing erase page checks, in combination with the teachings of Moon that an erase verification voltage should be adjusted according to wear factors, including the erase count, the combination of using the read count, placement duration, and erase count to determine the erase verification voltage is obvious.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla/Yu and Moon to achieve the combined result of performing an erase page check when the target parameter is greater than a threshold, where the erase page check is performed with a erase verification voltage adjusted based on an erase count, read count, and placement duration, which also writes the data into the block when the block passes the erase page check.
One of ordinary skill in the art would have been motivated to make this modification in order to minimize erase voltage stress and thereby extending the life of a device as discussed in Moon [0132].
While Shukla teaches writing to non-adjacent pages, specifically noting to skip lower pages to program to upper pages when read disturb errors are detected, Shukla/Yu/Moon does not appear to explicitly disclose writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yang teaches writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines. (Fig. 13 and [0111], Yang teaches checking for an erased condition, and upon a determination that there is sufficient error, programming continuing at an open word line that is not the word line immediately after the last programmed word line, ie. coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word lines “If there is a sufficient amount of errors in the open neighbor word line then the memory cells connected to the open neighbor word line will be padded by programming those memory cells using pseudo data. Examples of pseudo data include copies of data on the identified word line, a predetermined data pattern, random data, or any other type of mock data. After padding the data in step 956, controller 122 updates the system information for the neighbor word line and programming can continue for that block at the next open word line (if there is one).”).
Shukla/Yu/Moon and Yang are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Shukla/Yu/Moon and Yang each disclose responding to detected disturb errors by skipping memory spaces and programming into spaces not adjacent to the programmed spaces before spaces with disturb errors. One of ordinary skill in the art would have recognized that the pages of Shukla could have been substituted pages for the word lines of Yang because both the pages and word lines serve the purpose of units of memory space that can be checked for errors and programmed to, and word lines are comprised of pages. Furthermore, one of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a unit of memory space by which to check for errors and program to.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modify the writing to non-adjacent pages of Shukla/Yu/Moon to be replaced with the writing to non-adjacent word lines of Yang to yield the predictable result of writing to non-adjacent word lines in response to detected disturb errors.
Regarding claim 2: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 1, from which claim 2 depends.
Shukla/Yu/Moon/Yang further teaches in response to the target parameter of the first memory cell block being greater than the first threshold, performing an erase page check on the first memory cell block; and (Fig. 19, Shukla teaches that if the parameter is higher than the limit at step 904, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910. See also [0117])
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block passing the erase page check, writing the data into the first memory cell block. (Fig. 19, Shukla teaches that the proper erased state verification is checked at step 912, and if the unprogrammed region is properly verified, it goes to steps 906 and 908, where the data is programmed into the block. See also [0119])
Regarding claim 3: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 2, from which claim 3 depends.
Shukla/Yu/Moon/Yang further teaches the target parameter of the first memory cell block comprises the read count of the first memory cell block; (Fig. 19, Shukla teaches that the value that is compared in step 902 is a read count for the programmed region of the block, ie. the target parameter of the first memory cell block comprises a read count of the first memory cell block)
Regarding claim 6: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 2, from which claim 6 depends
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block failing the erase page check, determining whether a number of programmed memory cell pages in the first memory cell block is greater than a third threshold; in response to the number of pages being greater than the third threshold, determining a second memory cell block into which the data is to be written. (Fig. 25, [0143], Shukla teaches that after disturb errors are detected as in Fig. 19 step 912 (See also [0040] where Shukla mentions this type of verification is to detect read disturbance), the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, or if another block is needed to continue programming to instead, ie. determining whether a number of programmed memory cell pages in the first memory cell block is greater than a third threshold; in response to the number of the pages being greater than the third threshold, determining a second memory cell block into which the data is to be written. “If the amount of user data for the programming request exceeds the size of the one or more upper pages, the managing circuitry identifies one or more alternate blocks for programming the remaining user data at step 968”. Examiner notes that word lines are comprised of pages, and are both units of memory space (Shukla [0050] teaches that “A page is the smallest unit of programming”). Examiner also notes that the amount of space available is directly inversely correlated to the amount of space currently used. Checking for whether the used space is too high is equivalent to checking whether the available space is too low. Therefore, checking whether available space is too low is interpreted the same as checking whether the amount of programmed space exceeds a threshold)
Regarding claim 8: Shukla teaches:
A memory controller, comprising: a buffer configured to store a target parameter of a first memory cell block; and ([0117] Shukla teaches a memory controller that accesses a running count of the amount of reads to a block, ie. A memory controller, comprising: a buffer configured to store a target parameter of a first memory cell block “At step 902, the number of times the block or the programmed region of the corresponding block has been read since a last erase cycle is determined. The managing circuitry can access a read count value that is updated each time the block is read in one example”. Examiner notes that although it is not explicitly shown that there is a buffer component storing the parameters, since the managing circuitry accesses the parameter that is updated each read, a buffer is taught by the reference)
a processor configured to: ([0058], Fig. 6, and Fig. 7 Shukla teaches that the managing circuitry that performs the process of Fig. 19 and other memory processes in the system comprises processing hardware “Managing circuitry for memory array 100 can be considered to comprise one or more of the control circuitry 120, row decoders 140, column decoders 142, read/write circuits 130, or controller 144, for example.” The sense blocks of the read/write circuits 130 contain processors 222.)
in response to a data write instruction, determine a first memory cell block into which data is to be written; (Fig. 8A Shukla teaches that when programming requests are received at step 520, one or more blocks in which data is to be stored are identified at step 522. See also [0065]).
determine whether a target parameter of the first memory cell block is greater than a first threshold… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is greater than the first threshold (Fig. 19, Shukla teaches a programming operation step 904 that determines if a parameter is higher than a limit, and if it is, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910. See also [0117]))
writing, via an instruction to a peripheral circuit, the data into an unprogrammed memory cell page… in the first memory cell block, wherein the first memory cell block fails the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block and the number of first word lines is less than a second threshold, and the second page is not adjacent to the first programmed pages (Fig. 25, [0040], and [0141-143], Shukla teaches that after disturb errors are detected as in Fig. 19 step 912 (failing the erase page check), the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, and that if the space is not insufficient (number of word lines is less than a threshold), read disturb can be handled by programming into upper pages that are not adjacent to the last programmed pages, as the lower pages which may be adjacent to the last programmed pages are skipped)
Shukla does not appear to explicitly disclose wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block, a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yu teaches wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block or writing (Col 1, lines 52-59, Yu teaches that an erase program interval may be determined for a block, representing a time period elapsed after an erasure of the first block may be determined at the time of receiving a write request).
Shukla and Yu are analogous art because they are from the same field of endeavor, controlling write operations according to memory status.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla and Yu to achieve the method of, in response to a data write instruction, determining a block into which data is to be written, determining whether a target parameter is greater than a first threshold, the target parameter taking into account the time elapsed after an erasure of a block, and programming the data into the block if the target parameter is smaller than the threshold.
One of ordinary skill in the art would have been motivated to make this modification in order to take into account a known characteristic of the memory being degraded when the elapsed time is long as discussed in Yu Col. 1, lines 37-41 “In view of the characteristics of some flash memory devices, in a case where the EPI is long, a threshold voltage distribution characteristic thereof may be degraded, and as a result, the 40 reliability of data may be degraded.”.
While Shukla/Yu teach the read count (Shukla [0116]), placement duration (Yu Col. 19, lines 15-20), and an erase count (Shukla [0093]) being used to adjust verification operations to account for degradation, Shukla/Yu do not appear to explicitly disclose a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Moon teaches a read voltage to perform the erase page check is determined based on… an erase count of the first memory cell block ([0126], Moon teaches that the level of an erase verification voltage may be determined according to the erase mode. Furthermore, in [0103-0104], Moon teaches that access modes (including the erase mode) are determined based on a cumulative effective wear of a block, which is indicative of the number of erase cycles performed on a memory block. Therefore, the level of an erase verification voltage (used to verify erase states) are determined based on an erase count of the first memory cell block.)
Shukla/Yu and Moon are analogous art because they are from the same field of endeavor, managing memory devices.
Since Shukla/Yu similarly teach read count, placement duration, and erase count all being determining wear factors for performing erase page checks, in combination with the teachings of Moon that an erase verification voltage should be adjusted according to wear factors, including the erase count, the combination of using the read count, placement duration, and erase count to determine the erase verification voltage is obvious.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla/Yu and Moon to achieve the combined result of performing an erase page check when the target parameter is greater than a threshold, where the erase page check is performed with a erase verification voltage adjusted based on an erase count, read count, and placement duration, which also writes the data into the block when the block passes the erase page check.
One of ordinary skill in the art would have been motivated to make this modification in order to minimize erase voltage stress and thereby extending the life of a device as discussed in Moon [0132].
While Shukla teaches writing to non-adjacent pages, specifically noting to skip lower pages to program to upper pages when read disturb errors are detected, Shukla/Yu/Moon does not appear to explicitly disclose writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yang teaches writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines. (Fig. 13 and [0111], Yang teaches checking for an erased condition, and upon a determination that there is sufficient error, programming continuing at an open word line that is not the word line immediately after the last programmed word line, ie. coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word lines “If there is a sufficient amount of errors in the open neighbor word line then the memory cells connected to the open neighbor word line will be padded by programming those memory cells using pseudo data. Examples of pseudo data include copies of data on the identified word line, a predetermined data pattern, random data, or any other type of mock data. After padding the data in step 956, controller 122 updates the system information for the neighbor word line and programming can continue for that block at the next open word line (if there is one).”).
Shukla/Yu/Moon and Yang are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Shukla/Yu/Moon and Yang each disclose responding to detected disturb errors by skipping memory spaces and programming into spaces not adjacent to the programmed spaces before spaces with disturb errors. One of ordinary skill in the art would have recognized that the pages of Shukla could have been substituted pages for the word lines of Yang because both the pages and word lines serve the purpose of units of memory space that can be checked for errors and programmed to, and word lines are comprised of pages. Furthermore, one of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a unit of memory space by which to check for errors and program to.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modify the writing to non-adjacent pages of Shukla/Yu/Moon to be replaced with the writing to non-adjacent word lines of Yang to yield the predictable result of writing to non-adjacent word lines in response to detected disturb errors.
Regarding claim 9: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 8, from which claim 9 depends.
Shukla/Yu/Moon/Yang further teaches in response to the target parameter of the first memory cell block being greater than the first threshold, perform an erase page check on the first memory cell block; and (Fig. 19, Shukla teaches that if the parameter is higher than the limit at step 904, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910. See also [0117])
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block passing the erase page check, write the data into the first memory cell block. (Fig. 19, Shukla teaches that the proper erased state verification is checked at step 912, and if the unprogrammed region is properly verified, it goes to steps 906 and 908, where the data is programmed into the block. See also [0119])
Regarding claim 10: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 9, from which claim 10 depends.
Shukla/Yu/Moon/Yang further teaches the target parameter of the first memory cell block comprises the read count of the first memory cell block (Fig. 19, Shukla teaches that the value that is compared in step 902 is a read count for the programmed region of the block. See also [0117])
Shukla/Yu/Moon/Yang further teaches the buffer is configured to perform at least one of: store the read count of the first memory cell block; or store the placement duration of the first memory cell block. ([0117] Shukla teaches a buffer that contains the read count “At step 902, the number of times the block or the programmed region of the corresponding block has been read since a last erase cycle is determined. The managing circuitry can access a read count value that is updated each time the block is read in one example.”).
Regarding claim 13: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 9, from which claim 13 depends.
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block failing the erase page check, determine whether a number of programmed memory cell pages in the first memory cell block is greater than a third threshold; in response to the number of pages being greater than the third threshold, determine a second memory cell block into which the data is to be written. (Fig. 25, [0143], Shukla teaches that after disturb errors are detected as in Fig. 19 step 912 (See also [0040] where Shukla mentions this type of verification is to detect read disturbance), the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, or if another block is needed to continue programming to instead, ie. determining whether a number of programmed memory cell pages in the first memory cell block is greater than a third threshold; in response to the number of the pages being greater than the third threshold, determining a second memory cell block into which the data is to be written. “If the amount of user data for the programming request exceeds the size of the one or more upper pages, the managing circuitry identifies one or more alternate blocks for programming the remaining user data at step 968”. Examiner notes that word lines are comprised of pages, and are both units of memory space (Shukla [0050] teaches that “A page is the smallest unit of programming”). Examiner also notes that the amount of space available is directly inversely correlated to the amount of space currently used. Checking for whether the used space is too high is equivalent to checking whether the available space is too low. Therefore, checking whether available space is too low is interpreted the same as checking whether the amount of programmed space exceeds a threshold)
Regarding claim 14: The combination of Shukla, Yu, Moon, and Yang teach all limitations of claim 13, from which claim 14 depends.
Shukla/Yu/Moon/Yang further teaches in response to the number of the first word lines being not greater than the third threshold, write invalid data into an unprogrammed memory cell page located between the programmed memory cell pages and the unprogrammed memory cell page coupled to the second word line; (Fig. 13 Yang teaches writing pseudo data to a word line at 956 when it is skipped for writing to a non-adjacent word line at 958. See also [0111]. Examiner interprets “pseudo data” as the claimed “invalid data”)
One of ordinary skill in the art would have been motivated to make this modification to reduce the potential for electrons to drift between cells, as discussed in Yang [0032] “Programming the memory cells on the open neighbor word with pseudo data, will increase the amount of charge in the charge trapping material for the memory cells connected to open neighbor word line, thereby reducing the potential for electrons to drift within the charge trapping material from memory cells connected to the identified word line to the memory cells connected to open neighbor word line.”
Regarding claim 16: Shukla teaches A memory system, comprising:
a memory controller coupled to a memory and is configured to: (Fig. 6, Shukla teaches a control circuitry 120 connected to a memory 100 via read/write circuits 130A and 130B).
in response to a data write instruction, determine a first memory cell block into which data is to be written; (Fig. 8A Shukla teaches that when programming requests are received at step 520, one or more blocks in which data is to be stored are identified at step 522. See also [0065]).
determine whether a target parameter of the first memory cell block is greater than a first threshold… performing an erase page check on the first memory cell block, wherein the target parameter of the first memory cell block is greater than the first threshold (Fig. 19, Shukla teaches a programming operation step 904 that determines if a parameter is higher than a limit, and if it is, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910. See also [0117]))
send a first write command to the memory, the first write command instructing a peripheral circuit of memory to write the data into an unprogrammed memory cell page… in the first memory cell block, wherein the first memory cell block fails the erase page check, and wherein a number of first word lines are coupled to programmed memory cell pages in the first memory cell block and the number of first word lines is less than a second threshold, and the second page is not adjacent to the first programmed pages; (Fig. 25, [0040], and [0141-143], Shukla teaches that after disturb errors are detected as in Fig. 19 step 912 (failing the erase page check), the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, and that if the space is not insufficient (number of word lines is less than a threshold), read disturb can be handled by programming into upper pages that are not adjacent to the last programmed pages, as the lower pages which may be adjacent to the last programmed pages are skipped)
the memory configured to, in response to the first write command, write the data into second unprogrammed memory cell page… in the first memory cell block ([0057-0058] and Fig. 6, Shukla teaches that commands are transferred from controller 144 to the memory die 112, where the control circuitry 120 on 112 performs the memory operations, which would include the first write command instructing the memory to write the data into the first memory cell block; and the memory configured to: in response to the first write command, write the data into the first memory cell block “Commands and data are transferred between the host and controller 144 via lines 132 and between the controller and the one or more memory die 112 via lines 134… The control circuitry 120 cooperates with the read/write circuits 130A and 130B to perform memory operations on the memory array 100.”)
Shukla does not appear to explicitly disclose wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block, a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yu teaches wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block or writing (Col 1, lines 52-59, Yu teaches that an erase program interval may be determined for a block, representing a time period elapsed after an erasure of the first block may be determined at the time of receiving a write request).
Shukla and Yu are analogous art because they are from the same field of endeavor, controlling write operations according to memory status.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla and Yu to achieve the method of, in response to a data write instruction, determining a block into which data is to be written, determining whether a target parameter is greater than a first threshold, the target parameter taking into account the time elapsed after an erasure of a block, and programming the data into the block if the target parameter is smaller than the threshold.
One of ordinary skill in the art would have been motivated to make this modification in order to take into account a known characteristic of the memory being degraded when the elapsed time is long as discussed in Yu Col. 1, lines 37-41 “In view of the characteristics of some flash memory devices, in a case where the EPI is long, a threshold voltage distribution characteristic thereof may be degraded, and as a result, the 40 reliability of data may be degraded.”.
While Shukla/Yu teach the read count (Shukla [0116]), placement duration (Yu Col. 19, lines 15-20), and an erase count (Shukla [0093]) being used to adjust verification operations to account for degradation, Shukla/Yu do not appear to explicitly disclose a read voltage to perform the erase page check is determined based on the placement duration, an erase count of the first memory cell block, and a read count of the first memory cell block, or writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Moon teaches a read voltage to perform the erase page check is determined based on… an erase count of the first memory cell block ([0126], Moon teaches that the level of an erase verification voltage may be determined according to the erase mode. Furthermore, in [0103-0104], Moon teaches that access modes (including the erase mode) are determined based on a cumulative effective wear of a block, which is indicative of the number of erase cycles performed on a memory block. Therefore, the level of an erase verification voltage (used to verify erase states) are determined based on an erase count of the first memory cell block.)
Shukla/Yu and Moon are analogous art because they are from the same field of endeavor, managing memory devices.
Since Shukla/Yu similarly teach read count, placement duration, and erase count all being determining wear factors for performing erase page checks, in combination with the teachings of Moon that an erase verification voltage should be adjusted according to wear factors, including the erase count, the combination of using the read count, placement duration, and erase count to determine the erase verification voltage is obvious.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla/Yu and Moon to achieve the combined result of performing an erase page check when the target parameter is greater than a threshold, where the erase page check is performed with a erase verification voltage adjusted based on an erase count, read count, and placement duration, which also writes the data into the block when the block passes the erase page check.
One of ordinary skill in the art would have been motivated to make this modification in order to minimize erase voltage stress and thereby extending the life of a device as discussed in Moon [0132].
While Shukla teaches writing to non-adjacent pages, specifically noting to skip lower pages to program to upper pages when read disturb errors are detected, Shukla/Yu/Moon does not appear to explicitly disclose writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines.
However, Yang teaches writing… the data into an unprogrammed memory cell page coupled to a second word line in the first memory cell block… the second word line is not adjacent to the first word lines. (Fig. 13 and [0111], Yang teaches checking for an erased condition, and upon a determination that there is sufficient error, programming continuing at an open word line that is not the word line immediately after the last programmed word line, ie. coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word lines “If there is a sufficient amount of errors in the open neighbor word line then the memory cells connected to the open neighbor word line will be padded by programming those memory cells using pseudo data. Examples of pseudo data include copies of data on the identified word line, a predetermined data pattern, random data, or any other type of mock data. After padding the data in step 956, controller 122 updates the system information for the neighbor word line and programming can continue for that block at the next open word line (if there is one).”).
Shukla/Yu/Moon and Yang are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Shukla/Yu/Moon and Yang each disclose responding to detected disturb errors by skipping memory spaces and programming into spaces not adjacent to the programmed spaces before spaces with disturb errors. One of ordinary skill in the art would have recognized that the pages of Shukla could have been substituted pages for the word lines of Yang because both the pages and word lines serve the purpose of units of memory space that can be checked for errors and programmed to, and word lines are comprised of pages. Furthermore, one of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a unit of memory space by which to check for errors and program to.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modify the writing to non-adjacent pages of Shukla/Yu/Moon to be replaced with the writing to non-adjacent word lines of Yang to yield the predictable result of writing to non-adjacent word lines in response to detected disturb errors.
Shukla does not appear to explicitly disclose wherein a target parameter includes a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block
However, Yu teaches a placement duration of the first memory cell block, and the placement duration of the first memory cell block is a time difference between a current moment and a moment at which an erase operation was last performed on the first memory cell block (Col 1, lines 52-59, Yu teaches that an erase program interval may be determined for a block, representing a time period elapsed after an erasure of the first block may be determined at the time of receiving a write request).
Shukla and Yu are analogous art because they are from the same field of endeavor, controlling write operations according to memory status.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Shukla and Yu to achieve the method of, in response to a data write instruction, determining a block into which data is to be written, determining whether a target parameter is greater than a first threshold, the target parameter taking into account the time elapsed after an erasure of a block, and programming the data into the block if the target parameter is smaller than the threshold.
One of ordinary skill in the art would have been motivated to make this modification in order to take into account a known characteristic of the memory being degraded when the elapsed time is long as discussed in Yu Col. 1, lines 37-41 “In view of the characteristics of some flash memory devices, in a case where the EPI is long, a threshold voltage distribution characteristic thereof may be degraded, and as a result, the 40 reliability of data may be degraded.”.
Regarding claim 17: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 16, from which claim 17 depends.
Shukla/Yu/Moon/Yang further teaches in response to the target parameter of the first memory cell block being greater than the first threshold, send a detection command to the memory, (Fig. 19 and [0118], Shukla teaches that if the parameter is higher than the limit at step 904, the unprogrammed region of the block will be verified to ensure it is properly in an erased state at step 910.)
Shukla/Yu/Moon/Yang further teaches the detection command instructing the memory to perform the erase page check on the first memory cell block (At [0057-0058], Shukla teaches that commands are passed between the controller and memory, which would include the commands for verifying the unprogrammed region of the block “Commands and data are transferred between the host and controller 144 via lines 132 and between the controller and the one or more memory die 112 via lines 134… The control circuitry 120 cooperates with the read/write circuits 130A and 130B to perform memory operations on the memory array 100.”)
Shukla/Yu/Moon/Yang further teaches receive a detection result sent by the memory and determine whether the first memory cell block passes the erase page check; and (Fig. 23 and [0135], Shukla teaches that the memory managing circuitry reports a pass status if the unprogrammed region is successfully verified at step 936; the pass status being interpreted as the claimed detection result “If the un-programmed region is verified for the erased state, the managing circuitry reports a status of pass for the block at step 936.”)
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block passing the erase page check, send the first write command to the memory; and (Fig. 19, Shukla teaches that the proper erased state verification is checked at step 912, and if the unprogrammed region is properly verified, it goes to steps 906 and 908, where the data is programmed into the block. See also [0119])
Shukla/Yu/Moon/Yang further teaches the memory is further configured to: in response to the detection command, perform the erase page check on the first memory cell block, and send the detection result to the memory controller (Fig. 23 and [0134-0135], Shukla teaches a process by which the memory managing circuit performs an erase verification check at 926 before reporting a status of pass at 936 if successfully verified. The pass status being the one verified at 912 in Fig. 19 for programming the unprogrammed region of the block. “At step 926, the un-programmed region of the memory block is verified for the erased state. Step 926 may include verifying the memory cells in the un-programmed or erased region for the erased state while excluding memory cells in the already programmed region from verification. Various erase verify pass voltages may be used in the programmed region. Moreover, an erase verify pass voltage may be used for one or more word lines (e.g., WLn+3) in the un-programmed region to aid in enabling conduction of memory cells on an adjacent word line in the programmed region (e.g., WLn+2) as earlier described. At step 926, the managing circuitry determines whether the memory block passed partial block erase verification or whether the verification was otherwise successful. If the un-programmed region is verified for the erased state, the managing circuitry reports a status of pass for the block at step 936.”)
Regarding claim 18: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 17, from which claim 18 depends.
Shukla/Yu/Moon/Yang further teaches in response to the first memory cell block failing the erase page check, determine whether the number of first word lines coupled to the programmed memory cell pages in the first memory cell block is greater than a third threshold; (Fig. 25 and [0143], Shukla teaches that after disturb is detected, the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, ie. determine whether a number of programmed memory cell pages in the first memory cell block is greater than a third threshold “If the amount of user data for the programming request exceeds the size of the one or more upper pages, the managing circuitry identifies one or more alternate blocks for programming the remaining user data at step 968”. Examiner notes that word lines are comprised of pages, and are both units of memory space (Shukla [0050] teaches that “A page is the smallest unit of programming”). Examiner also notes that the amount of space available is directly inversely correlated to the amount of space currently used. Checking for whether the used space is too high is equivalent to checking whether the available space is too low. Therefore, checking whether available space is too low is interpreted the same as checking whether the amount of programmed space exceeds a threshold)
Shukla/Yu/Moon/Yang further teaches the memory is further configured to, in response to a second write command, write the data into the unprogrammed memory cell page coupled to the second word line in the first memory cell block ([0057-0058] and Fig. 6, Shukla teaches that commands are transferred from controller 144 to the memory die 112, where the control circuitry 120 on 112 performs the memory operations, which would include the first write command instructing the memory to write the data into the first memory cell block; and the memory configured to: in response to the first write command, write the data into the first memory cell block “Commands and data are transferred between the host and controller 144 via lines 132 and between the controller and the one or more memory die 112 via lines 134… The control circuitry 120 cooperates with the read/write circuits 130A and 130B to perform memory operations on the memory array 100.”)
Regarding claim 20: The combination of Shukla, Yu, Moon, and Yang teach all limitations of claim 18, from which claim 20 depends.
Shukla/Yu/Moon/Yang further teaches the second write command further instructs to write invalid data into an unprogrammed memory cell page located between the programmed memory cell pages and the unprogrammed memory cell page coupled to the second word line; and the memory is further configured to in response to the second write command, write the invalid data into the unprogrammed memory cell page located between the programmed memory cell pages and the unprogrammed memory cell page coupled to the second word line. (Fig. 13 Yang teaches writing pseudo data to a word line at 956 when it is skipped for writing to a non-adjacent word line at 958. See also [0111]. Examiner interprets “pseudo data” as the claimed “invalid data”)
One of ordinary skill in the art would have been motivated to make this modification to reduce the potential for electrons to drift between cells, as discussed in Yang [0032] “Programming the memory cells on the open neighbor word with pseudo data, will increase the amount of charge in the charge trapping material for the memory cells connected to open neighbor word line, thereby reducing the potential for electrons to drift within the charge trapping material from memory cells connected to the identified word line to the memory cells connected to open neighbor word line.”
Claims 4, 5, 11, 12 are rejected under 35 U.S.C. 103 as being unpatentable over
Shukla et al., U.S. Pub. No. 20160172045 (hereinafter 'Shukla') in view of
Yu et al., U.S. Patent No. 11315649 (hereinafter “Yu”) further in view of
MOON et al., U.S. Pub. No. 20140369124 (hereinafter “Moon”) further in view of
Yang et al., U.S. Pub. No. 20170116075 (hereinafter ‘Yang’) further in view of
Chang et al., U.S. Pub. No. 20220075715 (hereinafter ‘Chang’)
Regarding claim 4: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 3, from which claim 4 depends.
Shukla/Yu/Moon/Yang does not appear to explicitly disclose determining the first threshold based on the erase count of the first memory cell block.
However, Chang teaches determining the first threshold based on the erase count of the first memory cell block (Table 1, Chang teaches an example mapping of erase counts to determine a read count threshold, ie. determining the first threshold based on an erase count of the first memory cell block. See also [0088])
Shukla/Yu/Moon/Yang and Chang are analogous art because they are from the same field of endeavor, memory controllers that detect and mitigate read disturb errors during programming.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined The operation method of claim 3, as disclosed by Shukla/Yu/Moon, with further determining the first threshold based on the erase count of the first memory cell block, as disclosed by Chang.
One of ordinary skill in the art would have been motivated to make this modification in order to account for predictable inaccuracies caused by well-known variations in error rate based on memory health factors like erase counts, which one of ordinary skill in the art would recognize as an obvious option.
Regarding claim 5: The combination of Shukla, Yu, Moon, Yang, and Chang teaches all limitations of claim 4, from which claim 5 depends.
Shukla/Yu/Moon/Yang/Chang further teaches determining whether the erase count of the first memory cell block is greater than a third threshold; in response to the erase count of the first memory cell block being greater than the third threshold, determining the first threshold to be a threshold a; and in response to the erase count of the first memory cell block being not greater than the third threshold, determining the first threshold to be a threshold b, wherein the threshold a is smaller than the threshold b (Table 1, Chang teaches in the mapping of erase count to a read count threshold, as erase count goes into the high groupings, the read count threshold is set lower. For example, in the Open SLC group, every time the erase count crosses the threshold into another range, the read count threshold goes lower, ie. in response to the erase count of the first memory cell block being greater than the second threshold, determining the first threshold to be a threshold a; and in response to the erase count of the first memory cell block being not greater than the second threshold, determining the first threshold to be a threshold b, wherein the threshold a is less than the threshold b. See also [0088])
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 4.
Regarding claim 11: The combination of Shukla, Yu, Moon, and Yang teach claim 10, from which claim 11 depends.
Shukla/Yu/Moon/Yang does not appear to explicitly disclose determine the first threshold based on the erase count of the first memory cell block.
However, Chang teaches determine the first threshold based on an erase count of the first memory cell block (Table 1, Chang teaches an example mapping of erase counts to determine a read count threshold, ie. determine the first threshold based on an erase count of the first memory cell block. See also [0088])
Shukla/Yu/Moon/Yang and Chang are analogous art because they are from the same field of endeavor, memory controllers that detect and mitigate read disturb errors during programming.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined The memory controller of claim 10, as disclosed by Shukla/Yu/Moon/Yang, wherein the processor is further configured to determine the first threshold based on the erase count of the first memory cell block, as disclosed by Chang.
One of ordinary skill in the art would have been motivated to make this modification in order to account for predictable inaccuracies caused by well-known variations in error rate based on memory health factors like erase counts, which one of ordinary skill in the art would recognize as an obvious option.
Regarding claim 12: The combination of Shukla, Yu, Moon, Yang, and Chang teach all limitations of claim 11, from which claim 12 depends.
Shukla/Yu/Moon/Yang/Chang further teaches determine whether the erase count of the first memory cell block is greater than a third threshold; in response to the erase count of the first memory cell block being greater than the third threshold, determine the first threshold to be a threshold a; and in response to the erase count of the first memory cell block being not greater than the third threshold, determine the first threshold to be a threshold b, wherein the threshold a is less than the threshold b (Table 1, Chang teaches in the mapping of erase count to a read count threshold, as erase count goes into the high groupings, the read count threshold is set lower. For example, in the Open SLC group, every time the erase count crosses the threshold into another range, the read count threshold goes lower, ie. in response to the erase count of the first memory cell block being greater than the second threshold, determine the first threshold to be a threshold a; and in response to the erase count of the first memory cell block being not greater than the second threshold, determine the first threshold to be a threshold b, wherein the threshold a is less than the threshold b . See also [0088])
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 11.
Claims 7, 15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over
Shukla et al., U.S. Pub. No. 20160172045 (hereinafter 'Shukla') in view of
Yu et al., U.S. Patent No. 11315649 (hereinafter “Yu”) further in view of
MOON et al., U.S. Pub. No. 20140369124 (hereinafter “Moon”) further in view of
Yang et al., U.S. Pub. No. 20170116075 (hereinafter ‘Yang’) further in view of
Camp et al., U.S. Patent No. 10115472 (hereinafter ‘Camp’).
Regarding claim 7: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 6, from which claim 7 depends.
Shukla/Yu/Moon/Yang further teaches in response to the number of the first word lines being not greater than the third threshold, writing invalid data into an unprogrammed memory cell page located between the programmed memory cell pages and the unprogrammed memory cell page coupled to the second word line; and: (Fig. 13 Yang teaches writing pseudo data to a word line at 956 when it is skipped for writing to a non-adjacent word line at 958. See also [0111]. Examiner interprets “pseudo data” as the claimed “invalid data”)
Although Shukla teaches finding an alternate block in response to the number of the first word lines being greater than the third threshold, Shukla/Yu/Moon/Yang do not appear to explicitly disclose writing invalid data into the unprogrammed memory cell page in the first memory cell block.
However, Camp teaches writing invalid data into the unprogrammed memory cell page coupled to the second word line in the first memory cell block. (Fig. 11, Camp teaches when closing a block due to read disturb, to program dummy data into the remaining unprogrammed pages before proceeding. See also Col. 12, lines 26-32. Programming dummy data into the remaining unprogrammed pages would include any second word line, so writing to pages coupled to the second word line is taught. Examiner interprets “dummy data” as the claimed “invalid data”).
Shukla/Yu/Moon/Yang and Camp are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined The operation method of claim 6, further comprising: in response to the number of the first word lines being not greater than the third threshold, writing invalid data into an unprogrammed memory cell page located between the programmed memory cell pages and the unprogrammed memory cell page coupled to the second word line; and in response to the number of the first word lines being greater than the third threshold, as disclosed by Shukla/Yu/Moon/Yang, with writing invalid data into the unprogrammed memory cell page in the first memory cell block, as disclosed by Camp.
One of ordinary skill in the art would have been motivated to make this modification in order to prevent further electron drifting caused by large charge differences between neighboring word lines as discussed in Camp [0032] “To prevent future drifting, the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data. Programming the memory cells on the open neighbor word with pseudo data, will increase the amount of charge in the charge trapping material for the memory cells connected to open neighbor word line, thereby reducing the potential for electrons to drift within the charge trapping material from memory cells connected to the identified word line to the memory cells connected to open neighbor word line.”
Regarding claim 15: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 13, from which claim 15 depends.
Although Shukla teaches finding an alternate block in response to the number of the first word lines being greater than the third threshold, Shukla/Yu/Moon/Yang do not appear to explicitly disclose write invalid data into the unprogrammed memory cell page in the first memory cell block.
However, Camp teaches write invalid data into the unprogrammed memory cell page coupled to the second word line in the first memory cell block. (Fig. 11, Camp teaches when closing a block due to read disturb, to program dummy data into the remaining unprogrammed pages before proceeding. See also Col. 12, lines 26-32. Programming dummy data into the remaining unprogrammed pages would include any second word line, so writing to pages coupled to the second word line is taught. Examiner interprets “dummy data” as the claimed “invalid data”).
Shukla/Yu/Moon/Yang and Camp are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined The memory controller of claim 13, wherein the processor is further configured to: in response to the number of the first word lines being greater than the third threshold, as disclosed by Shukla/Yu/Moon/Yang, with writing invalid data into the unprogrammed memory cell page in the first memory cell block, as disclosed by Camp.
One of ordinary skill in the art would have been motivated to make this modification in order to prevent further electron drifting caused by large charge differences between neighboring word lines as discussed in Camp [0032] “To prevent future drifting, the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data. Programming the memory cells on the open neighbor word with pseudo data, will increase the amount of charge in the charge trapping material for the memory cells connected to open neighbor word line, thereby reducing the potential for electrons to drift within the charge trapping material from memory cells connected to the identified word line to the memory cells connected to open neighbor word line.”
Regarding claim 19: The combination of Shukla, Yu, Moon, and Yang teaches all limitations of claim 18, from which claim 19 depends.
Shukla/Yu/Moon/Yang further teaches in response to the number of the first word lines being greater than the third threshold, determine a second memory cell block into which the data is to be written, and (Fig. 25 and [0143], Shukla teaches that after disturb is detected, the amount of available space is checked to determine if there is insufficient space to continue programming in the same block, or if another block is needed to continue programming to instead, ie. in response to the number of the first word lines being greater than the third threshold, determine a second memory cell block into which the data is to be written “If the amount of user data for the programming request exceeds the size of the one or more upper pages, the managing circuitry identifies one or more alternate blocks for programming the remaining user data at step 968”. )
Shukla/Yu/Moon/Yang do not appear to explicitly disclose send a third write command to the memory, the third write command instructing to write invalid data into the unprogrammed memory cell page in the first memory cell block; and the memory is further configured to: in response to the third write command, write the invalid data into the unprogrammed memory cell page in the first memory cell block.
However, Camp teaches send a third write command to the memory, the third write command instructing to write invalid data into the unprogrammed memory cell page in the first memory cell block; and the memory is further configured to: in response to the third write command, write the invalid data into the unprogrammed memory cell page coupled to the second word line in the first memory cell block. (Fig. 11, Camp teaches when closing a block due to read disturb, to program dummy data into the remaining unprogrammed pages before proceeding. See also Col. 12, lines 26-32. Programming dummy data into the remaining unprogrammed pages would include any second word line, so writing to pages coupled to the second word line is taught. Examiner interprets “dummy data” as the claimed “invalid data”).
Shukla/Yu/Moon/Yang and Camp are analogous art because they are from the same field of endeavor, memory controllers that mitigate detected disturb effects by skipping spaces and programming dummy data in the skipped spaces.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined The memory system of claim 18, wherein, the memory controller is further configured to: in response to the number of the first word lines being greater than the third threshold, determine a second memory cell block into which the data is to be written, as disclosed by Shukla/Yu/Moon/Yang, to also send a third write command to the memory, the third write command instructing to write invalid data into the unprogrammed memory cell page in the first memory cell block; and the memory is further configured to: in response to the third write command, write the invalid data into the unprogrammed memory cell page in the first memory cell block, as disclosed by Camp.
One of ordinary skill in the art would have been motivated to make this modification in order to prevent further electron drifting caused by large charge differences between neighboring word lines as discussed in Camp [0032] “To prevent future drifting, the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data. Programming the memory cells on the open neighbor word with pseudo data, will increase the amount of charge in the charge trapping material for the memory cells connected to open neighbor word line, thereby reducing the potential for electrons to drift within the charge trapping material from memory cells connected to the identified word line to the memory cells connected to open neighbor word line.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.H.P./ Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/ Supervisory Patent Examiner, Art Unit 2133
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