Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-8 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al (US 2015/0162427).
Re claims 1 and 10: Lee et al teaches a semiconductor device and the method of manufacturing thereof comprising, as following: A semiconductor device, comprising: a substrate 101; a buffer layer on the substrate 103; an n- type epitaxial layer on the buffer layer 110; a protective layer “g” on the n- type epitaxial layer; a p type layer 120 disposed in a trench structure (c; 130) on the protective layer “g”, and penetrating the protective layer and within the n- type epitaxial layer; a gate insulating layer 22 on the p type layer; and a gate electrode 13 on the gate insulating layer (see para 0076 through para 0099; and see figs. 3A-3F, specifically fig. 3F).
Re claim 7: wherein the protective layer “g” includes SiO2 (see para. 0148).
Re claim 8: wherein the gate insulating layer 22 includes SiO2 (see para. 0124).
Re claim 11: Lee et al teaches a semiconductor device and the method of manufacturing thereof comprising, as following: wherein the forming of the p type layer, the gate insulating layer, and the gate electrode is performed by an etching process (see para. 0086).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. The teachings of Lee et al have been discussed above.
Re claims 4-5: Although, Lee et al discloses that the buffer layer 101 and the n- type epitaxial layer 110 includes gallium nitride (see para. 0059 through 0060), Lee et al is silent that these layers further consist of gallium oxide. However, at the time the invention was made or filed, it would have been obvious to one of ordinary skill in the art, who has expert knowledge of the manufacturing of the MOSFET/semiconductor, would have substituted the gallium nitride with the gallium oxide because gallium oxide has a wider bandgap (4.9eV) than gallium nitride (3.4 eV) allowing it to handle higher voltages (above 10kV) with lower losses, making it (gallium oxide) suitable for next-generation power devices. Further, while gallium nitride dominates high-frequency and LED markets, the gallium oxide is primarily targeted at high-voltage and high-efficiency applications. Accordingly, such incorporation of gallium oxide to the teachings of Lee et al would have been obvious design variation to one of ordinary skill in the art to further accommodate what application is being design and manufactured thereof.
Allowable Subject Matter
Claims 2-3, 6, 9 and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, taken alone or in combination thereof, fails to specifically teach, as following:
Re claims 2, 9 and 12-16: the semiconductor device further includes an n+ type epitaxial layer on the n- type epitaxial layer; a source electrode on the n+ type epitaxial layer and the protective layer; and a drain electrode on the n+ type epitaxial layer and the protective layer.
Re claims 3 and 17: wherein the p type layer includes NiOX (0.98≤x≤1).
Re claim 6: wherein the n- type epitaxial layer has a concentration of 1E16 cm-3 to1E19 cm-3.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Joo et al (US 2023/0045172); Park et al (US 2023/0207683); Shih et al (US 2021/0288167); Todd (US 2002/0000612); Pak et al (US 2024/0136301); Okabe et al (US 6,603,173); and Chen (US 2012/0205772) discloses a semiconductor device and method for manufacturing thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL G LEE, SPE TC2800 whose telephone number is (571)272-2398. The examiner can normally be reached M-F (430am-330pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allana Bidder, DIRECTOR TC2800 can be reached at (571)272-5560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL G LEE/Supervisory Patent Examiner, Art Unit 2876