DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tian (US 2018/0151142 hereinafter Tian).
As to claim 1, Tian discloses in Figs. 1-5, a display device (e.g., LCD panel, Fig. 2; para. [0004-0018]), comprising: a display panel including a plurality of gate lines (e.g., panel main body 203 with TFT MOS devices connected via gate lines controlled by GOA unit, Fig. 2; para. [0019-0020]); a gate driving circuit configured to drive the plurality of gate lines (e.g., GOA signal controller 202 with level-shifting circuit 2021 driving gate lines via level-shifted control signals ST, HC1-8, LC1/LC2 on second circuit line, Fig. 3; paras. [0019
]-[0022]); and a panel defect detection circuit configured to detect panel defects of the display panel by outputting a test result signal using at least one of either a signal input to the gate driving circuit or a signal output from the gate driving circuit as a test signal, and a reference signal (e.g., detection circuit in GOA 202 monitors currents I_ST, I_LC, I_HC of level-shifted output signals on second circuit line as test signals via ports 2024-2028, compares to reference threshold Iscp (e.g., 30 mA), and outputs test result signal T_SCP (notification signal) to indicate defects like shorts if exceeded, Fig. 3-4; paras. [0023]-[0030]).
As to claim 2, Huang discloses the display device of claim 1 (see above), wherein the test result signal has a low level voltage if a voltage level of the test signal and a voltage level of the reference signal are equal, and the test result signal has a high level voltage if the voltage level of the test signal and the voltage level of the reference signal are different from each other (e.g., T_SCP has low/invalid level if test current (e.g., normal 20 mA) equals/matches below reference threshold Iscp (30 mA), and high/valid level if different/exceeds threshold indicating defect, with timing sequence showing VOUT high/low transitions, Fig. 5; paras. [0031]-[0040]).
As to claim 14, Tian discloses a panel defect detection circuit (e.g., in GOA signal controller 202, Fig. 3; para. [0023]), comprising: a test circuit configured to output a test result signal using a test signal and a reference signal (e.g., circuit compares detection currents I_F1/I_F2/I_F3 to threshold Iscp and outputs T_SCP, Fig. 4; paras. [0023]-[0030]); and a signal supply circuit configured to supply the test signal and the reference signal to the test circuit (e.g., first/second circuit lines and timing controller 201 supply timing control signals (inputs) and level-shifted outputs for current monitoring, with ports 2023-2028, Fig. 3; paras. [0020]-[0022]), wherein the test signal is a signal input to a gate driving circuit for driving a plurality of gate lines disposed on a display panel, or a signal output from the gate driving circuit to one of the plurality of gate lines (e.g., test signal from inputs (timing controls STV/HCK/LC) or outputs (level-shifted ST/HC1-8/LC1/LC2 to gate lines), Fig. 2; paras. [0018]-[0022]).
As to claim 15, Tian discloses a panel defect detection method (e.g., short-circuit protection method, Fig. 4; para. [0029]), comprising: receiving a test signal and a reference signal (e.g., receive detection currents I_F1 etc. from outputs and threshold Iscp, para. [0030]); generating a test result signal based on the test signal and the reference signal (e.g., generate T_SCP if current > Iscp, with time count, paras. [0031]-[0035]); and determining whether a panel defect occurred in a display panel based on the test result signal (e.g., determine short if T_SCP valid, triggering shutdown, paras. [0036]-[0040]), wherein the test signal corresponds to one of a signal input to a gate driving circuit for driving a plurality of gate lines disposed on the display panel, and a signal output from the gate driving circuit to one of the plurality of gate lines (e.g., inputs (timing controls) or outputs (level-shifted signals to gate lines), Fig. 2; paras. [0018]-[0022]).
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng (US 10838285 hereinafter Zeng).
As to claim 16, Zeng discloses a display device (e.g., GOA display panel, Fig. 1; col. 2, ln. 1-20), comprising: a display panel including a plurality of gate lines and a plurality of clock signal lines (e.g., scanning lines 104 and clock signal lines to terminals 105/106, Fig. 1; col. 3, ln. 1-20); a gate driving circuit electrically connected to the plurality of gate lines, the gate driving circuit configured to receive clock signals from the plurality of clock signal lines and output gate signals to the plurality of gate lines (e.g., scan driving circuit 101 (GOA) receives CK1-8 and outputs to scanning lines, Fig. 2; col. 3, ln. 20-50); and a panel defect detection circuit configured to detect a defect occurred within the display device based on at least one of either the clock signals input to the gate driving circuit or the gate signals output from the gate driving circuit (e.g., testing setup uses grouped clock inputs/outputs for pure color patterns, detecting defects via visual comparison to expected pure colors, col. 4, ln. 1-col. 5, ln. 67).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian (US 2018/0151142 hereinafter Tian), in view of Chaji et al. (US 2014/0329339 hereinafter Chaji).
As to claim 3, Tian discloses the display device of claim 1 (see above), wherein the test result signal includes a first type, a second type, and a third type (e.g., T_SCP types based on high-level periods: sustained overcurrent >20 μs for confirmed defect (valid high), transient <5 μs for no flag (low), intermediate counts like 5 μs for partial evaluation, Fig. 5; paras. [0031]-[0040]).
Huang does not explicitly disclose the first type having two high level voltage periods, the second type having no high level voltage period, and the third type having one high level voltage period. However, Chaji teaches test result signals with varying types based on high-level periods from multi-phase comparisons (e.g., multiple mismatches over pulses for shorts (two high periods), none for normal, one for opens/partial in quick/detailed scans, Figs. 5A-B; paras. [0046]-[0050]). A POSITA would have found it obvious to combine Tian's time-thresholded T_SCP with Chaji's period-based classification to classify defects by pulse counts (e.g., two high for confirmed, none for normal, one for transient/partial), motivated by reducing false positives and enabling nuanced diagnostics in gate-enabled testing (Chaji, para. [0051]).
Allowable Subject Matter
Claims 4-13, 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 4-13, 17-20, the prior art does not disclose all the features as recited in the claims above, such as a level conversion circuit configured to convert a voltage level of the output signal to a selected value or less and output an output signal having the converted voltage level as the test result signal, as recited in claims 4-6, 12-13; wherein the controller is configured to determine whether the panel defect exists in the display panel based on at least one of a number and a length of high level voltage periods included in the test result signal, as recited in claims 7-11; and wherein the panel defect detection circuit detects the defect based on using at least one of either the clock signals input to the gate driving circuit or the gate signals output from the gate driving circuit as a test signal, as recited in claims 17-20.
Conclusion
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 11/29/2025