Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Since a new ground of rejection is being applied against unamended claims, this action is not made final. Accordingly, claims 1-21 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20040041927 A1, hereinafter, "Cho") in view of Goma & Hsieh (JP 2018504013 A, hereinafter, "Goma") and Okada & Nishiya (US 20200412987 A1, hereinafter, "Okada").
Regarding Claim 1, Cho teaches a solid-state imaging apparatus comprising: a pixel circuit (Cho, pg. 4, para. 2, ln. 1-2, "The pixel array may include a plurality of pixels arranged in a predetermined number of rows and columns (eg, M rows and N columns)."); a detection and selection circuit (Cho, pg. 5, para. 3, ln. 10-11, "…the row selection transistor SEL…"); and an AD conversion circuit, wherein the pixel circuit outputs a plurality of pixel signals corresponding to mutually different gains or sensitivities (Cho, pg. 4, para. 3, ln. 4, "…may provide timing signals to an analog to digital converter [ADC]."), the detection and selection circuit: includes a sample and hold circuit that holds the plurality of pixel signals output from the pixel circuit (Cho, Figs. 4 & 8, [0058], ln. 1-3, 5-6, "A column line 22 from the pixel array 12 is coupled to four inputs of a sample and hold circuit. The first input is a Vsig1 input 133 which is coupled to a sampling capacitor 161 for storing and holding a Vsig.sub.Long pixel signal…The third input is a Vsig2 input 129 which is coupled to a capacitor 137 which samples and holds a Vsig.sub.Short pixel signal."), compares one or more of the plurality of pixel signals held in the sample and hold circuit with a reference value (Cho, Fig. 8a, [0061], ln. 2-3, "The comparator 121 compares the Vsig1 133 signal and the V.sub.theshold 119 signal…"). Cho does not teach to generate a signal selection signal that instructs selection of a pixel signal among the plurality of pixel signals, selects at least one pixel signal among the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal, and selectively outputs the at least one pixel signal selected from the sample and hold circuit, and the detection and selection circuit is arranged in a stage before the AD conversion circuit that AD converts the at least one pixel signal selectively output from the sample and hold circuit of the detection and selection circuit. However, Goma teaches to generate a signal selection signal that instructs selection of a pixel signal among the plurality of pixel signals, selects at least one pixel signal among the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal, and selectively outputs the at least one pixel signal selected from the sample and hold circuit (Goma, pg. 13, para. 1, ln. 1-4, "The figure shows how the charge from the colored pixels is read out from the shared pixel architecture according to the timing scheme [not shown in this figure] and 'dumped' in parallel in the sample and hold capacitor, Based on the selection signal SEL [not shown in this figure] and the transfer gate signals TG_1 to TG_4, it indicates whether or not the data will be continuously shifted out later."). Goma does not teach the detection and selection circuit is arranged in a stage before the AD conversion circuit that AD converts the at least one pixel signal selectively output from the sample and hold circuit of the detection and selection circuit. However, Okada teaches the detection and selection circuit is arranged in a stage before the AD conversion circuit that AD converts the at least one pixel signal selectively output from the sample and hold circuit of the detection and selection circuit (Okada, Fig. 4, [0066], ln. 3-4, "The signal held by the S/H unit 111 is supplied to the ADC 112. The signal supplied to the ADC 112 is an analog signal, and the ADC 112 converts the supplied analog signal into a digital signal."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Okada and Goma with those of Cho because it is well known in the art to select at least one pixel signal from a sample and hold circuit and selectively output it from said circuit. It is also well known in the art to arrange the selection and detection circuits in a stage before the ADC circuit.
Claims 2 & 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Hasegawa et al (US 20190305792 A1, hereinafter, "Hasegawa").
Regarding Claim 2, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Hasegawa teaches a first semiconductor chip including a pixel array, the pixel array including a plurality of pixel circuits, each of which is the pixel circuit, and a vertical signal line (Hasegawa, Fig. 19, [0318], ln. 1-2, "…FIG. 19, pixels 312 (in the pixel region 212) formed on the sensor die 221…"); and a second semiconductor chip ([0312], ln. 3, "…a logic die 222…") including the detection and selection circuit (Hasegawa[204], ln. 1-2, "The control unit 81 controls the attenuation unit 82 in accordance with the amplitude of the VSL signal to attenuate the VSL signal input to the comparator 73.") and stacked on the first semiconductor chip (Hasegawa Fig. 19, [0317], ln. 1-2, "…the two-layer image sensor 220…"), wherein the pixel array and the vertical signal line are divided into a plurality of pixel arrays and a plurality of vertical signal lines (Hasegawa[0318], ln. 2-3, "…sensor die 221 are divided into pixel blocks 31.sub.1 each including at least one pixel 312."), and the detection and selection circuit (Hasegawa [0201], ln. 2, "…a control unit 81, and an attenuation unit 82.") is provided in each of the plurality of pixel arrays (Hasegawa [0320], ln. 1-3, "Each signal processing circuit 321 includes an ADC 322 configured to perform AD conversion of a pixel signal as an electric signal output from each pixel 312 of the corresponding pixel block 31.sub.1 of the sensor die 221…). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Hasegawa with those of Cho, Goma, and Okada to reduce manufacturing costs, as it is well known in the art to use a multichip construction.
Regarding Claim 18, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Hasegawa teaches a first semiconductor chip including a pixel array, the pixel array including a plurality of pixel circuits, each of which is the pixel circuit, and a vertical signal line (Hasegawa, Fig. 19, [0318], ln. 1-2, "…FIG. 19, pixels 312 (in the pixel region 212) formed on the sensor die 221…"); and a second semiconductor chip (Hasegawa [0312], ln. 3, "…a logic die 222…") including the detection and selection circuit (Hasegawa [204], 1-2, "The control unit 81 controls the attenuation unit 82 in accordance with the amplitude of the VSL signal to attenuate the VSL signal input to the comparator 73.") and stacked on the first semiconductor chip (Hasegawa Fig. 18B, [0317], ln. 1-2, "…the two-layer image sensor 220…"), wherein the vertical signal line is divided into vertically arranged segments per row of the pixel array (Hasegawa [0324], ln. 1-3, "Each signal processing circuit 321 is connected with the pixel block 31.sub.1 corresponding to the signal processing circuit 321 [or disposed at a position facing to the signal processing circuit 321] through a signal line 323."), and the detection and selection circuit is provided per pixel circuit (Hasegawa [0326], ln. 1-3, "…AD conversion scheme is called an area AD conversion (ADC) scheme. According to the area ADC scheme, AD conversion can be performed in parallel on pixel signals in a number equal to the number of signal processing circuits 321, which is equal to X×Y…" for X x Y = 1 x 1 since [0318], ln. 3-4, "…[X and Y are integers equal to or larger than one].").
Claims 3 & 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, Sugawa et al (EP 1746820 A1, hereinafter, "Sugawa"), and Johansson (US 20130027589 A1, hereinafter, "Johansson").
Regarding Claim 3, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Sugawa teaches the plurality of pixel signals include a first pixel signal for low illuminance (Sugawa, [0080], ln. 26, "…the pre-saturated charges…") , a second pixel signal for medium illuminance (Sugawa [0080], ln. 26, "…the supersaturated charges…"), and a third pixel signal for high illuminance (Sugawa [0080], ln. 26, "…the ultra-supersaturated charges…"), the reference value in the detection and selection circuit includes a first reference value (Sugawa, [0083], ln. 1, "The reference voltage potential Vo…") and a second reference value (Sugawa [0083], ln. 6, "The reference voltage potential Vo'…"), the first reference value includes a value corresponding to a level, of the second pixel signal, that corresponds to a level at a boundary immediately before a saturation level of the first pixel signal (Sugawa [0083], ln. 1-2, "The reference voltage potential Vo is selected to have a preceding voltage potential prior to the saturation of the photodiode PD…), and the second reference value corresponds to a level at a boundary immediately before a saturation level of the second pixel signal (Sugawa [0083], ln. 6-7, "The reference voltage potential Vo' is selected to have a preceding voltage potential prior to the saturation of the storage capacitor element Cs…). Sugawa does not teach the solid-state imaging apparatus further comprises a combining circuit that calculates, by interpolation processing, an unselected pixel signal based on the at least one pixel signal selected, and combines the at least one pixel signal selected and the unselected pixel signal calculated by interpolation processing. However, Johansson teaches the solid-state imaging apparatus further comprises a combining circuit that calculates, by interpolation processing, an unselected pixel signal based on the at least one pixel signal selected, and combines the at least one pixel signal selected and the unselected pixel signal calculated by interpolation processing (Johansson, [0061], ln. 8-13, "For some image pixels of the stitched output image, pixel values from a first image of the plurality of images may be used and for some other image pixels of the stitched output image, pixel values from a second image of the plurality of images may be used. Furthermore, for some further image pixels of the stitched output image, an interpolated pixel value between pixel values from image pixels of at least two images of the plurality of images may be used."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Sugawa and Johansson with those of Cho, Goma, and Okada to improve the dynamic range of the image. Additionally, it is well known in the art to use interpolation processing to combine multiple pixel signals.
Regarding Claim 4, Cho, Goma, Okada, Sugawa, and Johansson teach the limitations of dependent Claim 3 as noted above. Sugawa teaches the first reference value includes a value that corresponds to a level at a boundary immediately before a saturation level of the first pixel signal (Sugawa, [0083], ln. 1-2, "The reference voltage potential Vo is selected to have a preceding voltage potential prior to the saturation of the photodiode PD…).
Claims 6 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Sugawa.
Regarding Claim 6, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Sugawa teaches the sample and hold circuit includes two sample and hold capacitive elements (Sugawa, [0055], ln. 36-37, "…the row shift register SRH and the drivelines (ФS1 +N1, Ф№1; ФS1'+S2'+N2: PN2) using a CDS (correlation double sampling) circuit…), one for a reset component (Sugawa [0055], ln. 38, "…CFD noise [N₁]…") and one for a signal component (Sugawa [0055], ln. 37-38, "…pre-saturated charge signal [S₁] + CFD noise [N₁]…"), in correspondence with each of the plurality of pixel signals, and the detection and selection circuit compares a pixel signal level with the reference value, the pixel signal level calculated by subtracting the reset component from the signal component (Sugawa [0060], ln. 18-20, "…pre-saturated charge signal [S₁] + CED noise [N₁] and CED noise [N₁] are input to the differential amplifier DA1 to extract a differential component between these inputs for canceling CFD noise [N₁] and the pre-saturated charge signal [S₁] is obtained."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Sugawa with those of Cho, Goma, and Okada because it is well known in the art to design sample and hold circuits with multiple capacitive elements for reset and signal components. It is also well known in the art to use signal comparison.
Regarding Claim 10, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Sugawa teaches the detection and selection circuit includes: a detection circuit that generates the signal selection signal (Sugawa, [0066], ln. 5, "…a comparator CP…"); and a selection circuit that includes the sample and hold circuit and selects the at least one pixel signal among the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal (Sugawa [0066], ln. 6, "…a selector SE…"). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Sugawa with those of Cho, Goma, and Okada because it is well known in the art to generate a signal selection signal and use it to select at least one signal from a sample and hold circuit.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Tomita & Etou (WO 2020045373 A1, hereinafter, "Tomita").
Regarding Claim 7, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Tomita teaches the reference value is defined according to a gain of AD conversion by the AD conversion circuit (Tomita, Fig. 7, pg. 14, para. 6, ln. 8-9, "Note that the bias circuit that supplies the voltage V_AMP may be linked with the AD conversion gain."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Tomita with those of Cho, Goma, and Okada to reduce wiring and save on manufacturing costs.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Hashimoto et al (US 20130271633 A1, hereinafter, "Hashimoto").
Regarding Claim 8, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Hashimoto teaches a reference ramp signal generator that simultaneously generates a plurality of RAMP signals corresponding to the plurality of pixel signals (Hashimoto, [0067], ln. 8-9, "…a plurality of kinds of ramp signals in which the amplitudes are equal and the inclination ratios differ."); and a selection switch that selects and outputs one of the plurality of RAMP signals to the AD conversion circuit (Hashimoto [0067], ln. 5-7, "…it is also necessary to decrease the comparison threshold voltage VREF in proportion to the inclination ratios of the ramp signals."), wherein the selection switch selects the one of the plurality of RAMP signals according to the signal selection signal (Hashimoto [0069], ln. 1-2, "Since the signal level is small in a low illuminance environment, by raising the gain in the amplifier circuit, the signal level is increased or the inclination ratio of the ramp signal is decreased."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Hashimoto with those of Cho, Goma, and Okada to improve processing time.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Lim et al (US 20150249795 A1, hereinafter, "Lim").
Regarding Claim 9, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Lim teaches the detection and selection circuit generates a same signal selection signal for pixels included in a unit defined according to a color filter array (Lim, Fig. 1, [0053], ln. 4-9, "However, because, for example, color channel properties of color filters may be different, pixel data of pixels included in different color channels from among neighboring pixels (pixels associated with the same image location, for example) may be different and a color difference in image data may occur. The color shading correction unit 11 may correct the color difference of color channels of image data by applying correction gains having different values to each color channel."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Lim with those of Cho, Goma, and Okada to improve the dynamic range of the image.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Eto et al (JP 2019092143 A, hereinafter, "Eto").
Regarding Claim 13, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Eto teaches the signal selection signal generated by the detection and selection circuit instructs selection of two pixel signals among the plurality of pixel signals (Eto, Fig. 25, pg. 16, para. 7, ln. 1-3, "The multiplexer 247 selects two of the vertical signal lines VSL1 to VSL8 in accordance with the selection signal from the timing control circuit 250. The multiplexer 247 outputs the selected two pixel signals to the SAR ADC 300."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Eto with those of Cho, Goma, and Okada to improve processing speed.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Nishihara et al (WO 2018021053 A1, hereinafter, "Nishihara").
Regarding Claim 16, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Nishihara teaches the pixel circuit includes a first amplification transistor for outputting the plurality of pixel signals (Nishihara, Fig. 1, pg. 4, para. 4, ln. 2-3, "…a first amplification transistor as a first-stage detection unit."), the detection and selection circuit includes a second amplification transistor that outputs the pixel signal instructed by the signal selection signal (Nishihara Fig. 1, pg. 4, para. 5, ln 1-2, "…a second amplification transistor 33…"), and a gate area of the second amplification transistor is greater than a gate area of the first amplification transistor (Nishihara Fig. 1, pg. 6, para. 5, ln. 3-4, "Further, the gate area of the second amplification transistor is configured to be larger than the gate area of the first amplification transistor."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Nishihara with those of Cho, Goma, and Okada to improve processing performance.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Niwa et al (JP 2016012904 A, hereinafter, "Niwa").
Regarding Claim 17 Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Niwa teaches a vertical signal line from the detection and selection circuit (Niwa, Fig. 11, pg. 11, para. 2, ln. 1, "A first vertical signal line 23a and a second vertical signal line 23b…") is provided above a wiring layer of a power supply (pg. 10, para 8, ln. 3, "…VSS-a that supplies a source voltage…") or above a wiring layer of a ground electric potential (Niwa pg. 11, para. 2, ln. 3-4, "…and the signal line shield 101 includes the horizontal signal line VSS-a and the horizontal signal line VSS-.). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Niwa with those of Cho, Goma, and Okada because this method of electromagnetic shielding is well known in the art.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Yao & Shinohara (US 20180031808 A1, hereinafter, "Yao").
Regarding Claim 19, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Yao teaches the solid-state imaging apparatus according to claim 1 that captures an image of a subject (Yao, [0022], ln. 1-2, "Embodiments of a small form factor camera including a photosensor and a compact lens system are described."); an imaging optical system that guides incident light from the subject to the solid-state imaging apparatus (Yao [0034], ln. 1-2, "…includes at least a compact lens system 110…"); and a signal processor that processes an output signal from the solid-state imaging apparatus (Yao [0060], ln. 1, "…includes one or more processors 2010..."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Yao with those of Cho, Goma, and Okada because this is how virtually all digital cameras are made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, Yao, and Choi & Kim (US 20210112216 A1, hereinafter, "Choi").
Regarding Claim 20, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Choi teaches the solid-state imaging apparatus according to claim 1 that controls driving of a light source to emit pulsed light to a target and captures reflected light from the target (Choi [0028], ln. 1-2,"The driving signal CLK.sub.TX1,2 may be applied to the pixel array 10 in order to detect a light signal reflected from an object…"). Choi does not teach an imaging optical system that guides the reflected light from the target to the solid-state imaging apparatus; and a signal processor that processes an output signal from the solid-state imaging apparatus. However, Yao teaches an imaging optical system that guides the reflected light from the target to the solid-state imaging apparatus (Yao, [0034], ln. 1-2, "…includes at least a compact lens system 110…"); and a signal processor that processes an output signal from the solid-state imaging apparatus (Yao [0060], ln. 1, "…includes one or more processors 2010..."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi and Yao with those of Cho, Goma, and Okada because time-of-flight distance measurement (which is what this claim is describing) is well known in the art, as is how to make a digital camera (which this claim is also describing).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Goma, Okada, and Kuroda & Sugawa (CN 110679141 A, hereinafter, "Kuroda").
Regarding Claim 21, Cho, Goma, and Okada teach the limitations of dependent Claim 1 as noted above. Kuroda teaches the sample and hold circuit of the detection and selection circuit comprises: a plurality of sample and hold capacitive elements (Kuroda, Fig. 3A, pg. 9, last paragraph, ln. 2-3, "two sampling keeping capacitor element [CN] for 304N and the capacitance element [CS] 304S."); a plurality of associated sample and hold switching elements (Kuroda, Fig. 3A, pg. 9, last paragraph, ln. 3-5, "two write select switch unit for 305S, 305N, which is used for each capacitor element to two sample and hold write signal (charge accumulation) capacitor element [CN] for 304N and the capacitance element [CS] in the 304S."); and a plurality of associated readout selection switching elements (Kuroda, Fig. 3A, pg. 9, last paragraph, ln. 5-8, "switch unit 305S, 305N for two readout selection, it is used for each capacitor element from two sample-and-hold capacitor element [CN] for 304N and the capacitance element [CS] 304S in the read signal [the charge accumulation to the output side transmission downstream]."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Kuroda with those of Cho, Goma, and Okada because it is well known in the art to use these components to construct sample and hold circuits using pluralities of these components.
Allowable Subject Matter
Claims 5, 11, 12, 14, & 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 5, the prior art of record – taken alone or in combination – fails to teach or render obvious the sample and hold circuit includes a plurality of sample and hold elements that hold the plurality of pixel signals, when the pixel signal instructed by the signal selection signal is within a predetermined range including the reference value, the detection and selection circuit mixes the pixel signal instructed by the signal selection signal with another pixel signal at a composition ratio of a:(1-a) to generate a mixed pixel signal, and outputs the mixed pixel signal as the pixel signal instructed by the signal selection signal, a being a real number greater than or equal to zero and less than or equal to one, a is defined according to a difference between a level of the pixel signal instructed by the signal selection signal and the reference value, and a capacitance ratio of the plurality of sample and hold elements corresponding to the plurality of pixel signals is an inverse ratio of a gain that converts an original signal charge into a voltage value within the pixel circuit in the plurality of pixel signals.
Regarding Claim 11, the prior art of record – taken alone or in combination – fails to teach or render obvious a plurality of pairs of the selection circuit and the detection circuit are provided per pixel circuit, and the detection circuit included in one of the plurality of pairs and the selection circuit included in another of the plurality of pairs operate in parallel temporally.
Regarding Claim 12, the prior art of record – taken alone or in combination – fails to teach or render obvious the comparator subsequently receives, via the one of the input terminals, an input of a signal component of the second pixel signal from the pixel circuit, the comparator receives, via another of the input terminals, an input of the first reference value or the second reference value, and the detection and selection circuit implements a comparison of the second pixel signal and the first reference value and a comparison of the second pixel signal and the second reference value in parallel using a plurality of comparators each of which is the comparator or sequentially using a single comparator which is the comparator.
Regarding Claim 14, the prior art of record – taken alone or in combination – fails to teach or render obvious the detection and selection circuit outputs the at least one pixel signal selected to the AD conversion circuit via a vertical signal line, the detection and selection circuit generates a gain selection signal having a same effect as the signal selection signal, and the vertical signal line is shared in a time-division manner for transferring of the gain selection signal from the detection and selection circuit to the AD conversion circuit and transferring of the pixel signal from the detection and selection circuit to the AD conversion circuit.
Regarding Claim 15, the prior art of record – taken alone or in combination – fails to teach or render obvious the first reference value and the second reference value are adjusted according to the signal selection signal of a previous frame to imbue hysteresis which facilitates selection of a pixel signal for a current frame of a same gain or sensitivity as the pixel signal instructed by the signal selection signal of the previous frame.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN DANIEL BARRY whose telephone number is (571)270-0432. The examiner can normally be reached M-Th 0730-1630.
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/STEVEN DANIEL BARRY/Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638