DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 06/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 06/15/2026 in reply to the non-final rejection mailed on 03/06/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "one thermal routing" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 11, on which Claim 12 depends, establishes “one thermal routing” in line 3 and it is unclear whether Applicant intends to reference the same limitation.
Claim Rejections - 35 USC § 102 &103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 4, 6, & 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (US 20200118975).
Regarding Claim 1, Chen (see, e.g., figs. 17-18, fig. 33, para.0011, para.0119), shows a method comprising:
forming a dummy component 705 (see, e.g., para.0119), comprising:
forming a plurality of through-substrate vias (TSVs) 716 (see, e.g., para.0083) in a substrate 720 (see, e.g., para.0082),
wherein the plurality of TSVs 716 extend partially through the substrate 720 (716 may have a bottom surface between the top bottom surface of 720, see, e.g., para.0083);
after forming the plurality of TSVs 716 (the step of forming elements of the thermal structure take place after 716 & 720 are formed because the elements are “formed over” 716 & 720, see, e.g., para.0085-0088), forming a thermal structure 724 & 738 ( and the conductive elements inside them, provides a thermal connection, see, e.g., para.0085-0088, para.0091) over the plurality of TSVs 716 (see, e.g., fig. 17),
wherein the thermal structure comprises a plurality of metal lines 744 (plurality of 744 is omitted in fig. 17 but is stated to have the same configuration of 544 in fig. 13, see, e.g., fig. 13, fig. 17, para.0087) in a plurality of dielectric layers 724 & 738a-b (layers 738a-b are omitted in fig. 17 but has the configuration of 538a-b in fig. 13, see, e.g., para.0087);
forming a bonding layer 752 (see, para.0089) over the thermal structure;
and forming a plurality of bond pads 754 (see, e.g., para.0090) within the bonding layer 752;
bonding the dummy component 705 to a package component 105 (see, e.g., fig. 18, fig. 33, para.0092, para.0119);
and bonding a semiconductor die 205 to the package component 100 (see, para.0092, para.0119).
Regarding Claim 2, Chen shows the method of claim 1,
wherein bonding the dummy component 705 to the package component 105 comprises
bonding the bonding layer to the package component using dielectric-to-dielectric bonding (bonding between dielectric layers 752 & 152, see, e.g., para.0092)
and bonding the plurality of bond pads to the package component using metal-to-metal bonding (bonding between 154 & 754 which are both metal, see, e.g., para.0036, para.0090).
Regarding Claim 3, Chen shows the method of claim 1,
wherein forming the dummy component 705 further comprises
forming a plurality of metal vias 734, 746 & 757 (see, e.g., para.0087) in the plurality of dielectric layers 724 & 738a-b,
wherein metal vias of the plurality of metal vias 734, 746 & 757 physically contact metal lines of the plurality of metal lines 744 and TSVs of the plurality of TSVs 716 (see, e.g., fig. 17).
Chen refers to the conductive elements within the thermal structure as metal lines, metal vias, & metal features. All terms describe a metal conductive structure and therefore are interchangeable with one another.
Regarding Claim 4, Chen shows the method of claim 3,
wherein metal vias of the plurality of metal vias 734, 746 & 757 physically contact metal lines of the plurality of metal lines 744 and bond pads of the plurality of bond pads 754 .
Regarding Claim 6, Chen shows the method of claim 1,
wherein the plurality of TSVs 716 comprise
a third set of TSVs (leftmost and rightmost 716, hereinafter “716.3”) having a first pitch (hereinafter “P1”) and a fourth set of TSVs (center left and center right 716, hereinafter “716.4”) having a second pitch (hereinafter “P2”) that is different from the first pitch (P2 is smaller than P1, see, e.g., annotated figure 1).
The limitations “third” & “fourth” do not require or inherently provide a first set and a second set. The limitations are treated solely as distinguishing language for each set. In addition, the limitations broadly define a third set and a fourth set. Therefore, Examiner interprets the third set and fourth set as follows.
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Annotated Figure 1
Regarding Claim 7, Chen shows the method of claim 1,
wherein the plurality of TSVs comprise a fifth set of TSVs (716.3, see, e.g., annotated figure 1) having a first width (P1) and a sixth set of TSVs (716.4, see, e.g., annotated figure 1) having a second width (P2) that is different from the first width.
The limitations “fifth” & “sixth” do not require or inherently provide a first, second, third, or fourth set. The limitations are treated solely as distinguishing language for each set. Since Claim 7 does not depend on Claim 6, the elements shown in annotated figure 1 can be used to anticipate the limitations of Claim 7.
Claims 5 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20220262768) in view of Chen #2 (US 20200118975).
Regarding Claim 5, Chen shows the method of claim 1,
Chen, however, fails to show
wherein the plurality of TSVs comprise
a first set of TSVs having a first height
and a second set of TSVs having a second height that is different from the first height.
Chen #2 (see, e.g., fig. 1, para.0034, para.0043-0044, para.0048), in a method similar to Chen, shows a configuration of plurality of TSVs 103h of a dummy die configured with different heights would vary the functionality of the TSVs for different connections. Chen (see, e.g., fig. 18, fig. 33, para.0083-0084) states the TSVs 716 can extend all the way through the dummy die and foster a direct physical electrical connection, and the TSVs 716 can also have bottom surfaces within the top and bottom surface of the dummy die and provides structure to reduce the amount of warpage by providing heat dissipation.
The configuration of Chen #2 is incorporated into the method of Chen.
Chen, in view of Chen #2, shows
wherein the plurality of TSVs 716 comprise
a first set of TSVs (716 extending all the way through, see, e.g., fig. 33) having a first height (same height as substrate 720)
and a second set of TSVs (716 partially extending into 720, see, e.g., fig. 17) having a second height (less than the height of substrate 720) that is different from the first height (less than).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Chen #2 in the method of Chen to vary the functionality of the TSVs and to both foster a direct physical electrical connection and provide structure to reduce the amount of warpage.
Regarding Claim 8, Chen shows the method of claim 1,
Chen however, fails to show
wherein the dummy component is electrically connected to the semiconductor die by dummy routing within the package component.
Chen #2 (see, e.g., fig. 1, para.0034), in a similar device to Chen, shows a configuration
wherein the dummy component 103 is electrically connected to the semiconductor die 102 by dummy routing 101c (routing electrically connected to a dummy considered dummy routing) within the package component 101 & 101b.
Chen (see, e.g., para.0084, para.0091) states the dummy component 705 connected to the package component 105 through a dummy routing (electrical routing through elements 754, 134, 136, 154, & 156) would prevent warpage by providing heat dissipation.
The configuration of Chen #2 is incorporated in the method of Chen, as motivated by Chen, to prevent warpage of the semiconductor die 205.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Chen #2 in the method of Chen, as motivated by Chen, to prevent warpage of the semiconductor die.
Claims 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20200118975) in view of Lin (US 20190067157).
Regarding Claim 9, Chen (see, e.g., figs. 17-18, fig. 33, para.0011, para.0119) shows a method comprising:
forming a first bonding layer 152 on a first package component 105 (see, e.g., fig. 18, fig. 33, para.0092, para.0119);
forming a plurality of first bond pads 154 (right side beneath element 705, see, e.g., fig. 33, para.0092) in the first bonding layer;
forming a plurality of second bond pads 154 (left side beneath element 205 bonded to pads 254, see, e.g., fig. 33) in the first bonding layer;
bonding a thermal component 705 (see, e.g., para.0119) to the first bonding layer and to the plurality of first bond pads (bonded to 152, see, e.g., para.0092),
wherein the thermal component 705 comprises:
through-substrate vias (TSVs) 716 (see, e.g., para.0083) extending into a substrate 720 (see, e.g., para.0083);
a first dielectric layer 724 or 738 over the substrate and the TSVs 716 ;
a first layer of conductive features 734, 744, 746, 756, & 757 (see, e.g., para.0086-0088) over the first dielectric layer,
a second bonding layer 752 (see, e.g., para.0089) over the first layer of conductive features:
and a plurality of third bond pads 754 (see, e.g., para.0090) in the second bonding layer;
and bonding an active package component 205 (see, e.g., para.0048) to the first bonding layer 152 and to the plurality of second bond pads 154 (left side underneath 205), wherein the active package component comprises:
active devices (active device in 205 connected by 230, see, e.g., para.0040);
a third bonding layer 252 (see, e.g., para.0042) over the active devices;
and a plurality of fourth bond pads 254 (see, e.g., para.0042) in the third bonding layer.
Chen, however, fails to show
wherein the first layer of conductive features is isolated from the TSVs by the first dielectric layer:
Lin (see, e.g., fig. 1, fig. 8b, fig. 9, para.0015), in a similar method to Chen, shows a configuration wherein
wherein the first layer of conductive features 60 is isolated from the TSVs 116 (see, e.g., para.0042) by the first dielectric layer 58 (see, e.g., para.0020-0021):
Lin (see, e.g., para.0044, para.0057) states the configuration wherein the first layer of conductive features of a dummy die is isolated from the TSVs would allow for the dummy die to produce better thermal dissipation by decreasing the thermal resistance.
The configuration of Lin is incorporated into the method of Chen.
It would have been obvious to one at the time of filing the invention to one of ordinary skill in the art toe incorporate the configuration of Lin in the method of Chen, to allow for the dummy die to produce better thermal dissipation by decreasing the thermal resistance
Regarding Claim 10, Chen (see, e.g., para.0119), in view of Lin, shows the method of claim 9,
wherein the first bond pads of the plurality of first bond pads 154 are electrically isolated (154 is bonded to 705 which is a dummy structure, when bonded to a dummy structure, the bond pads are considered electrically isolated, see, e.g., para.0119).
Claims 11, 12, 14 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20200118975) in view of Lin (US 20190067157) and further in view of Chen #2 (US 20200118975).
Regarding Claim 11, Chen, in view of Lin, shows the method of claim 9 further comprising
forming one thermal routing (thermal routing formed by elements 154, 156 to 122 of the first package component) within the first bonding layer, wherein at least one third bond pad 754 is bonded to one thermal routing (this one routing connects to 122 of 105)
Chen, in view of Lin, however, fails to show
forming a plurality of thermal routing.
Chen (see, e.g., para.0084, para.0091) states the one thermal routing between 705 & 105 would prevent warpage by providing heat dissipation to the first package component 105. The active package component 205 of Chen produces heat as an electrical device and would also benefit from heat dissipation.
Chen #2 (see, e.g., fig. 1, para.0029, para.0034, para.0038), in a similar device to Chen, shows a configuration
forming a routing 101c within the first bonding layer 101b, connecting an active package component 102 to a component 103
Chen #2 shows the configuration of a routing between an active package component and a component both bonded to and connected through the first bonding layer 101b of the first package component 101
The configuration of Chen #2 is incorporated in the method of Chen, as motivated by Chen, to prevent warpage of the active package component 205.
Chen, in view of Chen #2, shows
forming a plurality of thermal routing (thermal routing formed by elements 154, 156 to 122 of the first package component, and now another thermal routing through 152 to active package component 205) within the first bonding layer, wherein at least one third bond pad 754 is bonded to one thermal routing (connecting 705 to 105)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Chen #2 in the method of Chen, as motivated by Chen, to prevent warpage of the active package component.
Regarding Claim 12, Chen, in view of Lin and further in view of Chen #2, shows the method of claim 11,
wherein at least one fourth bond pad (one of 254) is bonded to one thermal routing (as stated in the 103 rejection of claim 11).
Regarding Claim 14 Chen (see, e.g., para.0027, para.0043, para.0089), in view of Lin & Chen #2, shows the method of claim 11,
wherein a thickness of a layer of a first dielectric material (see, e.g., para.0027, para.0089) within the second bonding layer 752 is different from a thickness of a layer of the first dielectric material within the third bonding layer 252 (see, e.g., para.0043).
Chen states both the second bonding layer 752 and the third bonding layer 252 can be made of silicon oxide. Both 752 & 252 comprise the first dielectric material silicon oxide. Any portion within the surfaces of the bonding layers 252 & 752 can be interpreted as a layer of the first dielectric material within the bonding layer. The limitations do not claim distinguishing features from the first and second bonding layer. As such, any layer within the second bonding layer and the third bonding layer can be selected to render the claim obvious.
Regarding Claim 15 Chen (see, e.g., para.0089), in view of Lin & Chen #2, shows the method of claim 14,
wherein the first dielectric material is silicon oxide (see, e.g., para.0089).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20200118975) in view of Lin (US 20190067157) & Chen #2 (US 20200118975) and further in view of Shinkawa (JP 2005327967).
Regarding Claim 13, Chen, in view of Lin & Chen #2, shows the method of claim 11,
Chen, in view of Lin & Chen #2, however, fails to show
wherein the second bonding layer is thinner than the third bonding layer.
Chen (see, e.g., para.0042-0043, para.0056, para.0089, para.0099) states the thermal component 705 is a greater thickness than the active package component 205. The second bonding layer 752 and the third bonding layer 252 are made in a similar process. Chen states a grinding process is performed in order to level the heights of the thermal component and the active package component to reduce the aspect ratio of the gaps between the components and prepare the components for the top electrical component shown in fig. 27. Chen states, however, the grinding process is optional because TSVs 216 & 716, are not required to be exposed for the top electrical component to be incorporated.
Shinkawa (see, e.g., fig. 1), in a method similar to Chen, in view of Liu & Chen #2, shows a configuration
wherein the second bonding layer 18 is thinner than the third bonding layer 17
Shinkawa states a configuration for altering the heights of two die components by adjusting the thickness of their bonding layers that would facilitate a simpler and faster manufacturing process.
The configuration of Shinkawa is incorporated into the method of Chen, in view of Liu & Chen #2.
Therefore, in order to achieve the same heights for the active package component 205 and the thermal component 705, the thicknesses of the second bonding layer 752 and the third bonding layer 252 are altered as follows.
Chen, in view of Liu & Chen #2 and further in view of Shinkawa, shows
wherein the second bonding layer 752 is thinner than the third bonding layer 252.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Shinkawa in the method of Chen, in view of Liu & Chen #2, to facilitate a simpler and faster manufacturing process.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (US 20220262768).
Regarding Claim 16, Chen (see, e.g., fig. 17, fig. 33, para.0011, para.0119) shows a package comprising:
a dummy die 705 bonded to a package component 100,
wherein the dummy die comprises:
a substrate 720;
first metal features 716 (same metals as 156, see, e.g., para.0032, para.0041, para.0083) extending into the substrate;
second metal features 756 (same metals as 156, see, e.g., para.0032, para.0088) over the first metal features and separated from the first metal features by a first dielectric layer 724 (each of the first metal features vertically in line with each of the second metal features but across any diagonal direction the first dielectric layer is in between them and separates the first and second features, see, e.g., para.0085-0087);
a second dielectric layer 752 (see, e.g., para.0089) over the second metal features;
and bond pads 754 (see, e.g., para.0089) within the second dielectric layer,
wherein the second metal features are between the first metal features and the bond pads (756 vertically in between 716 & 754);
and a semiconductor die 205 (see, e.g., para.0014) bonded to the package component adjacent the dummy die 705 (see, e.g., fig. 33).
Regarding Claim 17, Chen shows the package of claim 16,
wherein the dummy die 705 is electrically isolated from the semiconductor die 105 (see, e.g., para.0119).
Regarding Claim 18, Chen shows the package of claim 16,
wherein the dummy die 705 comprises at least two layers of second metal features 756 (the two leftmost 756 features can be grouped as a first layer and the two rightmost 756 features can be a second layer, see, e.g., fig. 17).
Regarding Claim 19, Chen shows the package of claim 16,
wherein the package component comprises bond pads 154 (see, e.g., para.0038),
wherein the bond pads of the dummy die 754 are directly bonded to the bond pads of the package component 154 (see, e.g., fig. 33, para.0092).
Regarding Claim 20, Chen shows the package of claim 16,
wherein at least one first metal feature (one element 716 of the plurality) is electrically connected to at least one metal pad 154 (an electrical connection from 105 through 705 and their corresponding bonding/metal features, see, e.g., fig. 33, para.0091-0092) of the package component.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
