DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a second high resistance region disposed in the first nitride semiconductor layer and the second nitride semiconductor layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda et al. (US 20180145166 A1: hereinafter “Umeda), and further in view of Yamazaki (US 2017/0263782 A1).
In regard to claim 1, Umeda teaches a field effect transistor (a nitride semiconductor device), comprising:
a substrate (a substrate 101) (Fig. 8 and paragraph 104);
a first nitride semiconductor layer (a undoped GaN layer 103) (Fig. 8 and paragraph 74), disposed over the substrate (the undoped GaN layer 103 is shown over the substrate 101 in Fig. 8);
a second nitride semiconductor layer (undoped AlGaN layer 104) (Fig. 8 and paragraph 74), disposed on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer (the AlGan layer 104 is shown above the undoped GaN layer 103 and would have a larger bandgap due to containing aluminum) (Fig. 2 and paragraph 74);
a plurality of source electrodes (a plurality of source electrodes 107) on the second nitride semiconductor layer (the plurality of source electrodes are shown on the AlGan layer 104 in Fig. 8) (Fig. 8 and paragraph 77), respectively extending along a first direction (the source electrodes are shown extending in the lateral direction in Fig. 7), and arranged in parallel with each other along the first direction and a second direction perpendicular to the first direction in a plan view (the source electrodes are shown arranged parallel to one another in the lateral direction and vertical direction in Fig. 7);
a plurality of drain electrodes (a plurality of drain electrodes 108), on the second nitride semiconductor layer (the drain electrodes 108 are shown on the AlGan layer 104 in Fig. 8), respectively extending along the first direction, arranged in parallel with each other along the first direction and the second direction (the drain electrodes 108 are shown extending in the lateral direction and arranged parallel to one another in the vertical and parallel direction in Fig. 7), and alternately arranged with the plurality of source electrodes along the second direction (the source electrodes 107 and drain electrodes 108 are shown alternately arranged in the vertical direction in Fig. 7);
a plurality of gate structures, on the second nitride semiconductor layer (a gate electrode 106 and p-type semiconductor layer 105 functions as a gate structure) (Fig. 8 and paragraph 92), respectively extending along the first direction (the gate electrode 106 and p-type semiconductor layer 105 are shown extending in the lateral direction in Fig. 8), arranged in parallel with each other along the first direction and the second direction, and respectively surrounding one of the plurality of source electrodes in the plan view (the plurality of the gate electrodes 106 and p-type semiconductor layers 105 are shown to be arranged parallel in the vertical and lateral directions while surrounding the source electrodes 107 in Fig. 7), wherein each of the plurality of gate structures includes:
a third nitride semiconductor layer (the p-type semiconductor layer 105) disposed on the second nitride semiconductor layer (the p-type semiconductor layer 105 is shown on the undoped AlGaN layer 104 in Fig. 8); and
a gate electrode disposed on the third nitride semiconductor layer, (the gate electrode 106 is shown on the p-type semiconductor layer 105 in Fig. 8)
a first high resistance region (an upper portion of a high resistance region 112 annotated as FHR) (annotated Fig. 8 and paragraph 74), disposed in the first nitride semiconductor layer and the second nitride semiconductor layer and between the adjacent drain electrodes along the first direction (the high resistance region 112 is shown within GaN layer 103, and undoped AlGaN layer 104 and in between adjacent gate electrodes 106 in Fig. 8);
a plurality of gate connection portions (the portions of the p-type semiconductor layer 105 and a gate wire 110 annotated as GP in Fig. 8) (annotated Fig. 8 and paragraph 91), respectively electrically connecting the adjacent gate structures along the first direction (the portions of the p-type semiconductor layer 105 and a gate wire 110 annotated as GP are shown connecting adjacent gate structures in the lateral direction in Fig. 7);
a gate wiring (the gate wire 110) (Fig. 7 and paragraph 91), located above the first high resistance region, electrically connected to the plurality of gate connection portions and extending along the second direction (the gate wire 110 is shown above the high resistance region 112 and connecting the portions of the p-type semiconductor layer 105 and a gate wire 110 annotated as GP in annotated Fig. 8 below); and
an insulating layer, covering the plurality of source electrodes, the plurality of drain electrodes, the plurality of gate structures and the plurality of gate connection portions (although not illustrated, an insulating layer is formed on gate electrode 106, source electrode 107 and drain electrode 108, the insulating layer is provided with holes (via holes) that reach source electrode 107 and drain electrode 108) (paragraph 81).
However, Umeda doesn’t explicitly teach wherein the insulating layer is disposed between the gate wiring and the first high resistance region.
Yamazaki teaches (a high-electron-mobility transistor) (paragraph 147), wherein an insulating layer (an insulating layer 114) is disposed between a gate wiring (an electrode 117_2 functions as gate wiring to the gate electrode 112_2) and first high resistance region (an insulating layer 106) (Fig. 4A, Fig. 4B and paragraphs 114, 122 and 135).
It would have been obvious to one skilled in the art to combine the teachings of Umeda with the teachings of Yamazaki to have the insulating layer disposed between the gate wiring and the first high resistance region since this layout is well known to separate components and to avoid unwanted shorts within the device.
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In regard to claim 3, Umeda in view of Yamazaki doesn’t explicitly teach a second high resistance region (the upper portion of the high resistance region 112 annotated as SHR in Fig. 8 above is, shown on the far right and left in Fig. 9), surrounding the plurality of source electrodes, the plurality of drain electrodes and the plurality of gate structures in the plan view (the high resistance region 112 shown on the far right and left in Fig. 9 are also shown surrounding the gate electrodes 106, s source electrodes 107 and drain electrodes 108 in Fig. 9), and disposed in the first nitride semiconductor layer and the second nitride semiconductor layer (the high resistance region 112 is shown within GaN layer 103, and undoped AlGaN layer 104 and in between adjacent gate electrodes 106 in Fig. 8).
In regard to claim 4, Umeda teaches wherein each of the plurality of drain electrodes is surrounded by the first high resistance region adjacent to one side along the first direction, the second high resistance region adjacent to the other side along the first direction and the gate structure adjacent to both sides along the second direction (the drain electrodes 108 are show surrounded in the lateral direction by the high resistance region 112 and surrounded in the vertical direction by the gate structure formed of the p-type semiconductor layer 105 and gate electrode 106) (Fig. 9), or surrounded by the first high resistance region adjacent to both sides along the first direction and the gate structure adjacent to both sides along the second direction.
In regard to claim 5, Umeda teaches wherein a distance between the drain electrode and the first high resistance region along the first direction is greater than a distance between the drain electrode and the gate structure along the second direction (an inter-electrode distance between gate electrode 106 and drain electrode 108 is 10µm and the distance between the drain electrode 108 and the high resistance region 112 would be 12µm) (paragraphs 77-78).
In regard to claim 15, Umeda teaches wherein the first high resistance region includes an impurity that forms a region having a higher resistance than a two-dimensional electron gas channel region formed in the first nitride semiconductor layer (ion implantation can be performed for formation of high resistance region 112 and would have a higher resistance than a two-dimensional electron gas channel region formed at an interface between undoped GaN layer 103 and undoped AlGaN layer 104) (paragraphs 129-130).
In regard to claim 16, Umeda teaches wherein the first high resistance region includes the impurity introduced by ion implantation (ion implantation can be performed for formation of high resistance region 112) (paragraph 29).
In regard to claim 17, Umeda teaches wherein the impurity is at least one of He, B, N, O, F, and Ar (the high resistance region 112resistance is increased by Ar ion implantation) (paragraph 74).
In regard to claim 18, Umeda teaches wherein the third nitride semiconductor layer includes acceptor type impurities (p-type semiconductor layer 105 is a Mg-doped p-type GaN layer) (paragraph 91).
In regard to claim 19, Umeda teaches wherein the gate electrode is formed of a metal that forms a Schottky junction with the third nitride semiconductor layer (gate electrode 106 is in Schottky contact with the p-type semiconductor layer 105) (paragraph 91).
Claims 2, 6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Yamazaki, and further in view of Umeda as taught in Fig. 6.
In regard to claim 2, Umeda as taught in Fig. 7 and Fig. 8 in view of Yamazaki doesn’t explicitly teach a wiring width of the gate wiring along the first direction is less than or equal to a width of the first high resistance region along the first direction.
Umeda as taught in Fig. 6 teaches, a wiring width of a gate wiring (a gate wire 110) along the first direction is less than or equal to a width of a first high resistance region (an insulating film 111 and high resistance region 112 form a high resistance region) along the first direction (the insulating film 111 is shown to be the same width as the gate wire 110 in the first direction in Fig. 6) (Fig. 6 and paragraphs 99-101).
It would have been obvious to one skilled in the art to combine the teachings of Umeda as taught in Fig. 7 and Fig. 8 in view of Yamazaki with the teachings of Umeda as taught in Fig. 6 to have a wiring width of the gate wiring along the first direction is less than or equal to a width of the first high resistance region along the first direction since this allows for reduced parasitic capacitance and a leak current within the device as taught by Umeda (paragraph 100).
In regard to claim 6, Umeda as taught in Fig. 7 and Fig. 8 in view of Yamazaki doesn’t explicitly teach the insulating layer includes a first insulating layer disposed on the second nitride semiconductor layer, each of the plurality of source electrodes includes a source electrode contact portion embedded in a source opening of the first insulating layer and in contact with the second nitride semiconductor layer, and each of the plurality of drain electrodes includes a drain electrode contact portion embedded in a drain opening of the first insulating layer and in contact with the second nitride semiconductor layer.
Umeda as taught in Fig. 6 teaches, the insulating layer includes a first insulating layer (an insulating film 111) disposed on a second nitride semiconductor layer (the insulating film 111 is held between undoped AlGaN layer 104 and gate electrode 106) (Fig. 6 and paragraph 98), each of the plurality of source electrodes includes a source electrode contact portion (the bottom surface of a source electrode 107) embedded in a source opening of the first insulating layer (an surrounding source electrode 107 as shown in Fig. 6) and in contact with the second nitride semiconductor layer (the bottom surface of the source electrode 107 is shown contacting the undoped AlGaN layer 104 in Fig. 6) (Fig. 6 and paragraph 72), and each of the plurality of drain electrodes includes a drain electrode contact portion (a bottom surface of the drain electrode 108) embedded in a drain opening of the first insulating layer and in contact with the second nitride semiconductor layer (as the insulating layer 111 is only under the gate electrode 106 and the gate electrode surrounds the drain electrode 108, the bottom surface of the drain electrode would be in contact with the undoped AlGaN layer 104 in an opening formed in the insulating layer 111).
It would have been obvious to one skilled in the art to combine the teachings of Umeda as taught in Fig. 7 and Fig. 8 in view of Yamazaki with the teachings of Umeda as taught in Fig. 6 to have the insulating layer include a first insulating layer disposed on the second nitride semiconductor layer, where each of the plurality of source electrodes includes a source electrode contact portion embedded in a source opening of the first insulating layer and in contact with the second nitride semiconductor layer, and each of the plurality of drain electrodes includes a drain electrode contact portion embedded in a drain opening of the first insulating layer and in contact with the second nitride semiconductor layer since this allows for reduced parasitic capacitance and a leak current within the device as taught by Umeda (paragraph 100).
In regard to claim 11, Umeda as taught in Figs. 6-8 in view of Yamazaki teaches wherein a distance between the drain opening and the first high resistance region along the first direction is greater than a distance between the drain opening and the gate structure along the second direction (an inter-electrode distance between gate electrode 106 and drain electrode 108 is 10µm and the distance between the drain electrode 108 and the high resistance region 112 would be 12µm. Further as the drain opening contains the drain electrode the separation distances are smaller but the distance between the drain opening in the insulation layer 111 and the high resistance region 112 would be greater the distance between the gate electrode 106 and drain electrode 108) (paragraphs 74-77).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Yamazaki as applied to claim 1, and further in view of Hwang et al. (US 2022/0013659 A1; hereinafter “Hwang”).
In regard to claim 7, Umeda in view of Yamazaki don’t explicitly teach a source electrode extension portion, integrally formed with the plurality of source electrodes, covering the plurality of gate structures and extending toward the plurality of drain electrodes.
Hwang teaches a field effect transistor (a HEMT 100) (Fig. 1 and paragraph 50), comprising:
a source electrode extension portion (a source electrode 145 on a source contact 140) (Fig. 1 and paragraph 59), integrally formed with the plurality of source electrodes (a plurality of source contacts containing source electrodes 145 are shown in Fig. 3), covering the plurality of gate structures and extending toward the plurality of drain electrodes (a source electrode 145 provided on the source contact 140 and may extend over (and/or on) gate electrode 130 and extend towards the drain contact 143 as shown in Fig. 1) (Fig. 1 and paragraphs 59 and 64).
It would have been obvious to one skilled in the art to combine the teachings of Umeda in view of Yamazaki with the teachings of Hwang to have a source electrode extension portion, integrally formed with the plurality of source electrodes, covering the plurality of gate structures and extending toward the plurality of drain electrodes since this allows for gate leakage current to be reduced while maintaining high frequency performance as taught by Hwang (paragraph 69).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Yamazaki as applied to claim 1, and further in view of Shono (US 2012/0098038 A1).
In regard to claim 12, Umeda in view of Yamazaki doesn’t explicitly teach a source wiring, extending along the second direction and electrically connected to the plurality of source electrodes; and a drain wiring, extending along the second direction and electrically connected to the plurality of drain electrodes, wherein the gate wiring, the source wiring and the drain wiring are arranged on the insulating layer.
Shono teaches a field effect transistor (high-electron-mobility transistors (HEMT) (paragraph 3), comprising:
a source wiring (two ground wirings 25a and 25b) (Fig. 4 and paragraph 59), extending along a second direction (a vertical direction) and electrically connected to the plurality of source electrodes (the two ground wirings 25a and 25b are connected to the low-side source electrodes 15a to 15c) (Fig. 4 and paragraph 59); and a drain wiring (two output wirings 24a and 24b) (Fig. 4 and paragraph 59), extending along the second direction and electrically connected to the plurality of drain electrodes (the two output wirings 24a and 24b are connected to the low-side drain electrode 16a and 16b) (Fig. 4 and paragraph 59), wherein a gate wiring (a low-side gate wiring 18) (Fig. 4 and paragraph 58), the source wiring and the drain wiring are arranged on the insulating layer (the low low-side gate wiring 18, two output wirings 24a and 24b and two ground wirings 25a and 25b would all be located above the dielectric layer 5) (Fig. 4 and paragraph 26).
It would have been obvious to one skilled in the art at the time to combine the teachings of Umeda in view of Yamazaki with the teachings of Shono to have a source wiring, extending along the second direction and electrically connected to the plurality of source electrodes; and a drain wiring, extending along the second direction and electrically connected to the plurality of drain electrodes, wherein the gate wiring, the source wiring and the drain wiring are arranged on the insulating layer, since these wirings are known to increase device functionality and prevent characteristic degradation as taught by Shono (paragraph 64).
In regard to claim 13, Umeda in view of Yamazaki and Shono teaches the gate wiring is adjacent to the source wiring along the first direction (the low-side gate wiring 18 and 25a and 25b are shown adjacent to one another in the lateral direction in Fig. 4).
In regard to claim 14, Umeda in view of Yamazaki and Shono teach wherein a wiring width of the gate wiring along the first direction is less than a wiring width of the source wiring along the first direction, and less than a wiring width of the drain wiring along the first direction (the low low-side gate wiring 18 is shown with a smaller width than the two output wirings 24a and 24b and two ground wirings 25a and 25b in Fig. 4).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Yamazaki as applied to claim 1, and further in view of Miura et al. (US 2018/0097070 A1; hereinafter “Miura”).
In regard to claim 20, Umeda in view of Yamazaki doesn’t explicitly teach wherein the metal is at least one of TiN, WSi, and WSiN.
Miura teaches a field effect transistor (a JEFT (junction gate field-effect transistor) (Fig. 33 and paragraph 193), teach wherein a metal is at least one of TiN, WSi, and WSiN (a metal of the gate electrode GE is TiN) (Fig. 33 and paragraph 203).
It would have been obvious to one skilled in the art to combine the teachings of Umeda in view of Miura to have the metal be at least one of TiN since TiN is a well-known material to use in gate electrodes since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim Objections
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to claim 8, Hwang is considered a close prior art of reference. However, Hwang fails to teach each of the plurality of drain electrodes is surrounded by the source electrode extension portion in the plan view. The source electrodes are not shown surrounding the drain electrodes.
Claim 9 is objected to due to depending on claim 8.
In regard to claim 10, Hwang is considered a close prior art of record. However, Hwang fails to teach wherein the source electrode extension portion includes an inter-drain extension region located above the first high resistance region and between the adjacent drain electrodes along the first direction. Hwang is silent to the regard of a high resistance region within the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893