DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 3 in the reply filed on 6/9/2026 is acknowledged.
Claims 5, 8-10, and 12-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/9/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20200343236 A1 (Bhagavat et al hereinafter Bhagavat).
Regarding claim 1, Bhagavat discloses a semiconductor package comprising: a first redistribution structure (FIG. 4, metallization stack 145 ¶ [0029]) including a first redistribution insulating layer (FIG. 4, dielectric layers 157 ¶ [0029]) and a first redistribution pattern (FIG. 4, conductor traces 150 and conductive vias 155 ¶ [0029]); a first lower semiconductor device (FIGS. 3-4, processor chip 25 mounted on metallization stack 145 ¶ [0027]) mounted on the first redistribution structure; a molding layer (FIG. 4, dielectric layer 165 on metallization stack 145 surrounds chip 25 ¶ [0031]) surrounding the first lower semiconductor device on the first redistribution structure; a plurality of vertical connection conductors (FIG. 4, through dielectric vias 170 are in dielectric 165 ¶ [0031]) in the molding layer, the plurality of vertical connection conductors being electrically connected to the first redistribution pattern (FIG. 4, through dielectric vias 170 connect to conductor traces 150 ¶ [0037]); a heat dissipation plate (FIGS. 3-4, dummy component 110 can serve in a heat-dissipating capacity and is above an upper surface of chip 25 ¶ [0031]) on an upper surface of the first lower semiconductor device; and
a plurality of upper semiconductor devices (FIGS. 3-4, memory chips 30, 35, 40, and 45 are on dielectric 165 and chip 25 ¶ [0027]) on the molding layer and on the first lower semiconductor device, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the first lower semiconductor device (FIG. 3, memory chips 30, 35, 40, and 45 overlap different corners of chip 25), wherein the plurality of upper semiconductor devices are laterally spaced apart from the heat dissipation plate such that a gap is formed between each of the plurality of upper semiconductor devices and the heat dissipation plate (FIG. 3, there are gaps between each of memory chips 30, 35, 40, and 45 to dummy component 110), and wherein each of the plurality of upper semiconductor devices vertically overlaps a corresponding vertex among vertices of the upper surface of the first lower semiconductor device (FIG. 3, memory chips 30, 35, 40, and 45 overlap different corners/vertices of chip 25).
Regarding claim 3, Bhagavat discloses the limitations of claim 1 as detailed above, and further discloses a second redistribution structure (FIGS. 4 and 6, rectangle sub-section 200 includes an RDL structure on dielectric 165 formed of layers 175, 185, 225, and 230 ¶ [0031, 0035]) on the molding layer, the second redistribution structure including a second redistribution insulating layer (FIG. 6, dielectric film 230 and underfill 185 form a redistribution insulating layer ¶ [0031, 0035]) and a second redistribution pattern (FIG. 6, conductive pillar 225 and I/O 175 form a redistribution pattern ¶ [0031, 0035]), wherein the plurality of vertical connection conductors electrically connect the first redistribution pattern to the second redistribution pattern (FIGS. 4 and 6, through dielectric via 170 connects conductive pillar of second redistribution to a conductive via 155 of the first redistribution 145), and wherein the plurality of upper semiconductor devices are each mounted on the second redistribution structure (FIGS. 3-4, memory chips 30, 35, 40, and 45 are mounted on layers 175, 185, 225, and 230).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20200343236 A1 (Bhagavat et al hereinafter Bhagavat) as applied to claim 3 above, and further in view of US 20200395335 A1 (Chen et al hereinafter Chen).
Regarding claim 6, Bhagavat discloses the limitations of claim 3 as detailed above, but does not further disclose a second lower semiconductor device mounted on the first redistribution structure to be laterally spaced apart from the first lower semiconductor device, wherein the second lower semiconductor device vertically overlaps any one of the plurality of upper semiconductor devices.
However, Chen discloses a semiconductor package (FIG. 4, package 4) which includes a second lower semiconductor device (FIG. 4, semiconductor chip 101 ¶ [0039]) mounted on a first redistribution structure (FIG. 4, redistribution layer RDL1 ¶ [0015]) to be laterally spaced apart from a first lower semiconductor device (FIG. 4, semiconductor chip 201 ¶ [0039]), wherein the second lower semiconductor device vertically overlaps any one of a plurality of upper semiconductor devices (FIG. 4, chip 300 ¶ [0025]); the device of Chen also includes vertical connection conductors (FIG. 4, through integrated fan-out vias TIV ¶ [0017]) in a molding layer (FIG. 4, first encapsulation layer E1 ¶ [0022]), much like the device of Bhagavat.
Bhagavat and Chen both pertain to the field of semiconductor packaging, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the structure of Bhagavat in view of Chen to include a second lower semiconductor device mounted on the first redistribution structure to be laterally spaced apart from the first lower semiconductor device, wherein the second lower semiconductor device vertically overlaps any one of the plurality of upper semiconductor devices as was demonstrated by Chen, as the device of Bhagavat discloses analogous structures which could be adjusted in view of Chen based on adding functionality to the device and managing space and device density by incorporating a second chip on the same lower layer as the first lower chip, according to the configuration taught by Chen, depending on the intended applications of the semiconductor package.
Regarding claim 7, Bhagavat in view of Chen discloses the limitations of claim 6 as detailed above, and Chen further discloses that the second redistribution pattern (Chen FIG. 4, redistribution layer RDL2 includes redistribution layers 108, some of which connect to chip 101 ¶ [0023]) comprises a conductive via pattern connected to a pad (Chen FIG. 4, connector pad 100d ¶ [0019]) of the second lower semiconductor device provided at an upper surface of the second lower semiconductor device and extending in the molding layer (Chen FIG. 4, connector pad 100d is provided at an upper surface of chip 101 and extends through encapsulation E1).
Claims 1-4, 11, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20210066279 A1 (Yu et al hereinafter Yu) in view of Bhagavat.
Regarding claim 1, Yu discloses a semiconductor package (semiconductor package 10’s FIG. 19 embodiment ¶ [0088-0089]) comprising: a first redistribution structure (FIG. 19, redistribution layer structure 130A ¶ [0076]) including a first redistribution insulating layer (FIG. 19, dielectric layer 132 ¶ [0034]) and a first redistribution pattern (FIG. 19, conductive features 134 ¶ [0034]); a first lower semiconductor device (FIG. 19, first logic die LD1 ¶ [0030]) mounted on the first redistribution structure; a molding layer (FIG. 19, encapsulant 120A surrounds logic die LD1 and is on redistribution layer 130A ¶ [0047]) surrounding the first lower semiconductor device on the first redistribution structure; a plurality of vertical connection conductors (FIG. 19, conductive pillars 206A are in encapsulant 120A ¶ [0067]) in the molding layer, the plurality of vertical connection conductors being electrically connected to the first redistribution pattern (FIG. 19, conductive pillars 206A electrically connect to redistribution layer 130A ¶ [0069]); a heat dissipation plate (FIG. 19, heat conduction block HC is on an upper surface of logic die LD1 ¶ [0039]) on an upper surface of the first lower semiconductor device; and
a plurality of upper semiconductor devices (FIG. 19, memory dies MD are on encapsulant 120A and logic die LD1 ¶ [0038]) on the molding layer and on the first lower semiconductor device, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the first lower semiconductor device (FIG. 19, memory dies MD overlap logic die LD1 at different areas), wherein the plurality of upper semiconductor devices are laterally spaced apart from the heat dissipation plate such that a gap is formed between each of the plurality of upper semiconductor devices and the heat dissipation plate (FIG. 19, there are gaps between heat conduction block HC and memory dies MD).
Yu does not further disclose that each of the plurality of upper semiconductor devices vertically overlaps a corresponding vertex among vertices of the upper surface of the first lower semiconductor device. However, Bhagavat discloses a semiconductor package (the package of FIGS. 3-4 ¶ [0008-0009]) where a plurality of upper semiconductor devices (FIGS. 3-4, memory chips 30, 35, 40, and 45 ¶ [0027]) vertically overlaps a corresponding vertex (FIG. 3, four vertices/corners of processing chip 25 are overlapped by memory chips 30, 35, 40, and 45) among vertices of the upper surface of a first lower semiconductor device (FIGS. 3-4, processing chip 25 ¶ [0027]); in the context of the claimed limitations, the packages of Yu and Bhagavat differ in the position and number of upper semiconductor devices. A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Yu in view of Bhagavat to use a set of four upper memory chips overlapping vertices of a lower logic chip, as Bhagavat has demonstrated such a configuration to be known in the art, and a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Yu and Bhagavat both pertain to the field of semiconductor packaging, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the structure of Yu in view of Bhagavat such that each of the plurality of upper semiconductor devices vertically overlaps a corresponding vertex among vertices of the upper surface of the first lower semiconductor device, as a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Regarding claim 2, Yu in view of Bhagavat disclose the limitations of claim 1 as detailed above, and they further disclose that the upper surface of the first lower semiconductor device comprises four vertices (Yu FIG. 18, lower device LD1 has four vertices/corners; this structure is also present in Bhagavat FIG. 3’s processing chip 25), and wherein the plurality of upper semiconductor devices include four semiconductor devices (Bhagavat FIG. 3, memory chips 30, 35, 40, and 45) vertically overlapping four vertices, respectively, of the upper surface of the first lower semiconductor device.
Regarding claim 3, Yu in view of Bhagavat disclose the limitations of claim 1 as detailed above, and they further disclose a second redistribution structure (Yu FIG. 19, redistribution layer structure 150, located on encapsulant 120A ¶ [0037]) on the molding layer, the second redistribution structure including a second redistribution insulating layer (FIG. 19, dielectric layer 152 ¶ [0037]) and a second redistribution pattern (FIG. 19, conductive features 154 ¶ [0037]), wherein the plurality of vertical connection conductors electrically connect the first redistribution pattern to the second redistribution pattern (FIG. 19, conductive pillars 206A electrically connect redistribution structures 130A and 150 ¶ [0073]), and wherein the plurality of upper semiconductor devices are each mounted on the second redistribution structure (FIG. 19, memory dies MD are mounted on redistribution structure 150 ¶ [0038]).
Regarding claim 4, Yu in view of Bhagavat disclose the limitations of claim 3 as detailed above, and they further disclose a heat plate contact (Yu FIG. 19, a lower half of thermally conductive adhesive 168 functions in the capacity of a heat plate contact ¶ [0040]) disposed between the heat dissipation plate and the upper surface of the first lower semiconductor device (FIG. 19, thermally conductive adhesive 168 is between heat conduction block HC and lower die LD1), the heat plate contact vertically penetrating the second redistribution insulating layer (FIG. 19, thermally conductive adhesive 168 passes through dielectric layer 152 along a vertical direction).
Regarding claim 11, Yu in view of Bhagavat discloses the limitations of claim 1 as detailed above. Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to further modify the structure of Yu in view of Bhagavat in the context of the disposition of the heat dissipation plate. Specifically, Bhagavat FIG.3 illustrates that a heat dissipation plate (FIG. 3, dummy component 110 can serve the function of dissipating heat ¶ [0031]) comprises a first segment between two upper semiconductor devices adjacent to each other in a first lateral direction among the plurality of upper semiconductor devices (FIG. 3, dummy component 110 has a segment located between upper memory chips 40 and 45). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to incorporate that configuration of the heat dissipation plate into the device of Yu in view of Bhagavat as Bhagavat has demonstrated such a configuration to be known in the art, and a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure and optimization of the utilization of space in the device.
Regarding claim 14, Yu in view of Bhagavat discloses the limitations of claim 1 as detailed above, and as considered regarding claim 1 above they further disclose that the first lower semiconductor device comprises a logic chip (Yu ¶ [0031] logic dies LD1 and LD2 may include CPU/GPU chiplets), and wherein each of the plurality of upper semiconductor devices comprises a memory chip (Bhagavat ¶ [0027], the upper chips 30, 35, 40, and 45 are memory chips).
Regarding claim 15, Yu in view of Bhagavat discloses the limitations of claim 1 as detailed above. Additionally, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to further modify the structure of Yu in view of Bhagavat in the context of the disposition of the heat dissipation plate. Specifically, Bhagavat FIG.3 illustrates that a first upper semiconductor device (FIG. 3, memory chip 40 ¶ [0027]) of the plurality of upper semiconductor devices is spaced apart from a second upper semiconductor device (FIG. 3, memory chip 45 ¶ [0027]) of the plurality of upper semiconductor devices in a first lateral direction with the heat dissipation plate therebetween (FIG. 3, dummy component 110 can serve the function of dissipating heat ¶ [0031]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to incorporate that configuration of the heat dissipation plate into the device of Yu in view of Bhagavat as Bhagavat has demonstrated such a configuration to be known in the art, and a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure and optimization of the utilization of space in the device.
Regarding the limitations “wherein a ratio between a first length of the first lower semiconductor device and a second length of an overlapping region of the first lower semiconductor device vertically overlapping one of the plurality of upper semiconductor devices is between about 20% and about 40%, and wherein the first length and the second length are lengths in the first lateral direction”, Yu FIG. 19 illustrates that the first lower semiconductor device (logic die LD1) has a first length along a first (horizontal) lateral direction, and a second length that vertically overlaps the left instance of an upper semiconductor device (memory device MD), and that there is a ratio between the first length and the second length. The ratio itself is not quantified in the disclosure of Yu, as that was not a feature of particular importance to the disclosure of their invention.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would recognize that when allocating space for the heat dissipation plate in the device of Yu, the overlapping length ratio between the lower semiconductor device and overlying upper semiconductor devices is directly affected by such space allocation. A person of ordinary skill in the art would also recognize that the amount of space allocated for the heat dissipation plate is a result-effective variable that affects the capability of the heat dissipation plate to transfer heat and the density of the device, with the size of the heat dissipation plate increasing its capability to remove heat while simultaneously increasing the device’s scale. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the amount of space allocated for the heat dissipation plate, as it has been identified as a result-effective variable. Consequently, the claimed ratio of lengths will also be varied along with the amount of space allocated for the heat dissipation plate, and one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein the ratio between the first length and the second length is between about 20% and about 40%, in order to arrive at a configuration wherein a favorable balance of heat dissipation capacity and device density has been reached. (see also MPEP 2144.05).
Furthermore, the applicant has not presented persuasive evidence that the claimed ratio of lengths is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 16, Yu discloses a semiconductor package (semiconductor package 10’s FIG. 19 embodiment ¶ [0088-0089]) comprising: a lower package (FIG. 19, a portion of the package including encapsulants 120A, 120B, the elements disposed within them, and redistribution layer 150 ¶ [0037, 0047, 0050]) including a lower semiconductor device (FIG. 19, first logic die LD1 ¶ [0030]) and a molding layer (FIG. 19, encapsulant 120A surrounds logic die LD1 ¶ [0047]) surrounding the lower semiconductor device; a plurality of upper semiconductor devices (FIG. 19, memory dies MD are on encapsulant 120A and logic die LD1 ¶ [0038]) on the lower package, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the lower semiconductor device (FIG. 19, memory devices MD overlap different regions of logic die LD1);
and a heat dissipation plate (FIG. 19, heat conduction block HC is on an upper surface of logic die LD1 ¶ [0039]) on an upper surface of the lower semiconductor device, the heat dissipation plate laterally spaced apart from each of the plurality of upper semiconductor devices with a gap therebetween (FIG. 19, there are gaps between heat conduction block HC and memory dies MD), wherein the lower semiconductor device comprises at least one logic chip (logic dies LD1 and LD2 may include CPU/GPU chiplets ¶ [0031]).
Yu does not further disclose that the plurality of upper semiconductor devices comprise four memory chips vertically overlapping four vertices of the upper surface of the lower semiconductor device, respectively.
However, Bhagavat discloses a semiconductor package (the package of FIGS. 3-4 ¶ [0008-0009]) where a plurality of upper semiconductor devices (FIGS. 3-4, memory chips 30, 35, 40, and 45 ¶ [0027]) vertically overlaps a corresponding vertex (FIG. 3, four vertices/corners of processing chip 25 are overlapped by memory chips 30, 35, 40, and 45) among vertices of the upper surface of a first lower semiconductor device (FIGS. 3-4, processing chip 25 ¶ [0027]); the packages of Yu and Bhagavat differ in the position and number of upper semiconductor devices. A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Yu in view of Bhagavat to use a set of four upper memory chips overlapping vertices of a lower logic chip, as Bhagavat has demonstrated such a configuration to be known in the art, and a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Yu and Bhagavat both pertain to the field of semiconductor packaging, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the structure of Yu in view of Bhagavat such that the plurality of upper semiconductor devices comprise four memory chips vertically overlapping four vertices of the upper surface of the lower semiconductor device, respectively, as a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Regarding claim 17, Yu in view of Bhagavat discloses the limitations of claim 16 as detailed above, and Yu further discloses a first redistribution structure (Yu FIG. 19, redistribution layer structure 130A under encapsulant 120A and logic die LD1 ¶ [0076]) under the molding layer and under the lower semiconductor device, the first redistribution structure including a first redistribution insulating layer (FIG. 19, dielectric layer 132 ¶ [0034]) and a first redistribution pattern (FIG. 19, conductive features 134 ¶ [0034]); a second redistribution structure (FIG. 19, redistribution layer structure 150, located on encapsulant 120A and logic die LD1 ¶ [0037]) on the molding layer and on the lower semiconductor device, the second redistribution structure including a second redistribution insulating layer (FIG. 19, dielectric layer 152 ¶ [0037]) and a second redistribution pattern (FIG. 19, conductive features 154 ¶ [0037]); and a plurality of vertical connection conductors (FIG. 19, conductive pillars 206A electrically connect redistribution structures 120A and 150 ¶ [0073]) in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern.
Regarding claim 19, Yu in view of Bhagavat discloses the limitations of claim 17 as detailed above, and Yu further discloses a first region (Yu FIG. 19, a region which includes first logic die LD1) and a second region (FIG. 19, a region which includes conductive pillars 206A, and which surrounds logic die LD1) surrounding the first region, and wherein, when viewed in plan view, the lower semiconductor device is in the first region (first region includes first logic die LD1), and the plurality of vertical connection conductors are in the second region (second region includes conductive pillars 206A).
Regarding claim 20, Yu discloses a semiconductor package (semiconductor package 10’s FIG. 19 embodiment ¶ [0088-0089]) comprising: a first redistribution structure (FIG. 19, redistribution layer structure 130A ¶ [0076]) including a first redistribution insulating layer (FIG. 19, dielectric layer 132 ¶ [0034]) and a first redistribution pattern (FIG. 19, conductive features 134 ¶ [0034]); a lower semiconductor device (FIG. 19, first logic die LD1 is mounted on a region of redistribution layer 130A ¶ [0030]) mounted on a first region of the first redistribution structure; a plurality of vertical connection conductors (FIG. 19, conductive pillars 206A are on another region of redistribution layer 130A ¶ [0067]) on a second region of the first redistribution structure, the plurality of vertical connection conductors being connected to the first redistribution pattern (FIG. 19, conductive pillars 206A electrically connect to redistribution layer 130A ¶ [0069]); a molding layer (FIG. 19, encapsulant 120A surrounds logic die LD1 and conductive pillars 206A, and is on redistribution layer 130A ¶ [0047]) on the first redistribution structure and surrounding the lower semiconductor device and the plurality of vertical connection conductors; a second redistribution structure (FIG. 19, redistribution layer structure 150, located on encapsulant 120A and logic die LD1 ¶ [0037]) on the molding layer and the lower semiconductor device, the second redistribution structure including a second redistribution insulating layer (FIG. 19, dielectric layer 152 ¶ [0037]) and a second redistribution pattern (FIG. 19, conductive features 154 ¶ [0037]), wherein the second redistribution pattern is electrically connected to the first redistribution pattern through the plurality of vertical connection conductors (FIG. 19, conductive pillars 206A electrically connect redistribution structures 130A and 150 ¶ [0073]);
a heat plate contact (FIG. 19, a lower half of thermally conductive adhesive 168 functions in the capacity of a heat plate contact ¶ [0040]) within the second redistribution insulating layer (FIG. 19, thermally conductive adhesive 168 passes through dielectric layer 152 along a vertical direction in an opening in the dielectric layer “A plurality of heat conduction blocks HC are disposed between the memory dies MD over the first logic die LD1” ¶ [0086]) and in contact with an upper surface of the lower semiconductor device (FIG. 19, thermally conductive adhesive 168 is in contact with an upper surface of logic die LD1); a plurality of upper semiconductor devices (FIG. 19, memory dies MD are mounted on redistribution layer 150 and vertically overlap different regions of first logic die LD1 ¶ [0038]) mounted on the second redistribution structure and each vertically overlapping a different respective region of the lower semiconductor device; and a heat dissipation plate (FIG. 19, heat conduction block HC is attached to thermally conductive adhesive 168 and spaced apart from each of memory dies MD with a gap between them ¶ [0039]) attached on the heat plate contact and spaced apart from each of the plurality of upper semiconductor devices in a lateral direction with a gap therebetween, wherein the upper surface of the lower semiconductor device comprises four vertices (FIG. 18, which provides a general plan view of the embodiment of FIG. 19, illustrates that first logic die LD1 has four vertices/corners ¶ [0088, 0082]).
Yu does not further disclose that the plurality of upper semiconductor devices comprise four semiconductor devices vertically overlapping the four vertices, respectively, of the upper surface of the lower semiconductor device, wherein the lower semiconductor device comprises a logic chip, and wherein the plurality of upper semiconductor devices comprise memory chips.
However, Bhagavat discloses a semiconductor package (the package of FIGS. 3-4 ¶ [0008-0009]) where a plurality having four upper semiconductor devices (FIGS. 3-4, memory chips 30, 35, 40, and 45 ¶ [0027]) vertically overlap four corresponding vertices (FIG. 3, four vertices/corners of processing chip 25 are overlapped by memory chips 30, 35, 40, and 45) of the upper surface of a lower semiconductor device (FIGS. 3-4, processing chip 25 ¶ [0027]); the packages of Yu and Bhagavat differ in the position and number of upper semiconductor devices. A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Yu in view of Bhagavat to use a set of four upper memory chips overlapping vertices of a lower logic chip, as Bhagavat has demonstrated such a configuration to be known in the art, and a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Yu and Bhagavat both pertain to the field of semiconductor packaging, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the structure of Yu in view of Bhagavat such that the plurality of upper semiconductor devices comprise four semiconductor devices vertically overlapping the four vertices, respectively, of the upper surface of the lower semiconductor device, wherein the lower semiconductor device comprises a logic chip, and wherein the plurality of upper semiconductor devices comprise memory chips, as a person of ordinary skill in the art may find such a configuration beneficial depending on the intended application of the package structure.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Bhagavat as applied to claim 17 above, and further in view of U patent publication US 20200395263 A1 (Kim et al hereinafter Kim).
Yu in view of Bhagavat discloses the limitations of claim 17 as detailed above, and they further disclose a heat plate contact (Yu FIG. 19, a lower half of thermally conductive adhesive 168 functions in the capacity of a heat plate contact ¶ [0040]) between the heat dissipation plate and the upper surface of the lower semiconductor device (FIG. 19, thermally conductive adhesive 168 is between heat conduction block HC and lower die LD1), the heat plate contact being in a through hole of the second redistribution insulating layer (FIG. 19, thermally conductive adhesive 168 passes through dielectric layer 152 along a vertical direction in an opening in the dielectric layer “A plurality of heat conduction blocks HC are disposed between the memory dies MD over the first logic die LD1 and the second logic dies LD2” ¶ [0086]), and wherein the heat dissipation plate is thermally coupled to the lower semiconductor device through the heat plate contact (FIG. 19, heat conducting block HC is couple to logic die LD1 through thermally conductive adhesive 168).
Regarding the limitation “wherein the thermal conductivity of the heat plate contact is greater than that of silicon”, Yu teaches that thermally conductive adhesive 168 has high thermal conductivity, and may be a graphite film, among other materials (¶ [0040]), but did not compare the thermal conductivity to a thermal conductivity of silicon.
However, Kim discloses a package wherein a heat dissipation feature (FIG. 9, heat dissipation member 170) may be formed of a graphite material with higher thermal conductivity than silicon in order to secure heat dissipation characteristics. Additionally, the present application’s specification mentions that graphite is an appropriate material for a feature which is intended to have higher thermal conductivity than silicon (¶ [0064]).
Yu, Bhagavat, and Kim all, pertain to the field of semiconductor packaging, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the structure of Yu in view of Bhagavat and Kim to use a graphite material for the heat plate contact wherein the thermal conductivity of the heat plate contact is greater than that of silicon, in order to secure heat dissipation characteristics as taught by Kim.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20210272929 A1, US 20210225804 A1, US 20210111156 A1, US 20190333893 A1, and US 20170365587 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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