DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of Claims 1-9, drawn to a method, has been acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Structure that Includes Deep Trench Capacitors and Method for Fabricating the Same.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Briend et al (US 2016/0181249) in view of Yu et al (US 2015/0380316) and Cote et al (US 2014/0151772), and in further view of Weis et al (US 7635893).
Regarding Claim 1, Briend et al discloses a method (method [0018]) for fabricating a semiconductor structure (FinFET device [0018] Fig 1-2), comprising:
providing a semiconductor substrate (SOI substrate 21 [0021] Fig 1-2),
wherein the semiconductor substrate (12 Fig 1-2) comprises:
a buried oxide (BOX) layer (buried oxide layer 16 [0021] Fig 1-2);
at least one fin structure (fin structure 18 [0027] Fig 1-2) located on a portion of the BOX layer (16 Fig 1-2);
a deep trench capacitor (DTC) (deep trenches 34, dielectric layer 36, and TiN and poly fill 38 [0026] Fig 2) extending through the BOX layer (16 Fig 1-2);
an isolation layer (thin oxide material 24 and nitride material 26 [0024] Fig 1) located on the fin structure (18 Fig 1-2), the DTC (34, 36, 38 Fig 2) and the BOX layer (16 Fig 1-2); and
an oxide material layer (oxide material 28 [0024] Fig 1-2) located on the isolation layer (24 and 26 Fig 1),
wherein the semiconductor substrate (12 Fig 1-2) is divided into a fin structure region (shown in annotated Fig 2) and a deep trench (DT) region (shown in annotated Fig 2) adjacent to and connected with the fin structure region (shown in annotated Fig 2),
wherein the fin structure region (shown in annotated Fig 2) comprises the fin structure (18 Fig 1-2), and wherein the DT region (shown in annotated Fig 2) comprises the DTC (34, 36, 38 Fig 2).
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Briend et al does not disclose
a high aspect ratio process (HARP) layer located on the isolation layer,
thinning the HARP layer, with a remaining portion of the HARP layer being retained above the BOX layer;
removing the isolation layer and the HARP layer from the fin structure region;
forming a first oxide layer over the semiconductor substrate;
forming layer-stacked structures on the first oxide layer; and
forming a sidewall spacer on each sidewall of the layer-stacked structure.
Yu et al, in the related art of semiconductor devices that include FinFET devices, discloses
a high aspect ratio process (HARP) layer (HARP oxide may be included in dielectric material 112 [0020] Fig 1) located on the isolation layer (isolation material 106 [0020] Fig 1),
thinning the HARP layer (annealing and planarizing using chemical-mechanical polishing CMP [0021]), with a remaining portion of the HARP layer (112 shown in Fig 2) being retained (shown in Fig 2);
removing the isolation layer (106) and the HARP layer (112) from the fin structure region (isolation material and the dielectric material (which includes a HARP oxide) are recessed with one or more etching processes [0025]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Briend et al to include using a HARP layer which is then thinned and removed along with the isolation layer from the fin structure region as taught by Yu et al in order to have a more uniform profile of exposed portions of the raised structures/fins and avoid device performance and other downstream fabrication problems [0004]. Further, a person of ordinary skill in the art would have recognized that a more uniform surface would be advantageous in that other structures necessary for the device are typically included on the same bulk substrate [0021], and the more uniform surface would improve the reliability and functioning of the device (see MPEP 2143.I(D)).
The combination of Briend et al and Yu et al now discloses
thinning the HARP layer (112 Fig 1-2 Yu et al), with a remaining portion of the HARP layer (112 Fig 1-2 Yu et al) being retained above the BOX layer (16 Fig 1-2 Briend et al).
The combination of Briend et al and Yu et al does not disclose
forming a first oxide layer over the semiconductor substrate;
forming layer-stacked structures on the first oxide layer; and
forming a sidewall spacer on each sidewall of the layer-stacked structure.
Cote et al, in the related art of semiconductor devices that include FinFET devices, discloses
forming a first oxide layer (node dielectric (silicon oxide) 102c [0074] Fig 6) over the semiconductor substrate (base substrate 102 [0057]);
forming layer-stacked structures (inner electrode 138 [0077], conductive fill material 140, dielectric cap 142 [0078] Fig 7) on the first oxide layer (102c Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Briend et al and Yu et al to include forming a first oxide layer over the semiconductor substrate as taught by Cote et al in order to have an insulator between conductors [0070]. Further, a person of ordinary skill in the art would have recognized that having an insulator between two conductors would be advantageous in avoiding unwanted electrical effects which would avoid unwanted damage and improve the reliability and durability of the device while preserving electrical functioning (see MPEP 2143.I(D)).
The combination of Briend et al, Yu et al, and Cote et al does not disclose
forming a sidewall spacer on each sidewall of the layer-stacked structure.
Weis et al, in the related art of semiconductor devices that include FinFET devices, discloses
forming a sidewall spacer (silicon oxide layer/isolation collar 32 [column 10, lines 16-23] Fig 2U) on each sidewall of the layer-stacked structure (polysilicon filling 31 [column 8, lines 60-67], polysilicon fill 36 [column 12, lines 9-25], and metal strap 38 [column 11, lines 25-35] Fig 2U).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Briend et al, Yu et al, and Cote et al to include forming a sidewall spacer on each sidewall of the layer-stacked structure as taught by Weis et al in order to suppress a parasitic transistor [column 8, lines 60-67]. Further, a person of ordinary skill in the art would have recognized that having sidewall spacers would be advantageous in protecting the device from unwanted electrical effects which would avoid unwanted damage and improve the reliability and durability of the device while preserving electrical functioning (see MPEP 2143.I(D)).
Regarding Claim 8, the combination of Briend et al, Yu et al, Cote et al, and Weis et al discloses the limitations of claim 1 as explained above. The combination of Briend et al, Yu et al, Cote et al, and Weis et al further discloses
wherein at least one of the layer-stacked structures (polysilicon filling 31 [column 8, lines 60-67], polysilicon fill 36 [column 12, lines 9-25], and metal strap 38 [column 11, lines 25-35] Fig 2U Weis et al) intersects the fin structure (fin structure 18 [0027] Fig 1-2 Briend et al), and
at least one of the layer-stacked structures (polysilicon filling 31 [column 8, lines 60-67], polysilicon fill 36 [column 12, lines 9-25], and metal strap 38 [column 11, lines 25-35] Fig 2U Weis et al) is located on the first oxide layer (node dielectric (silicon oxide) 102c [0074] Fig 6 Cote et al) above the DTC (34, 36, 38 Fig 2 Briend et al).
Regarding Claim 9, the combination of Briend et al, Yu et al, Cote et al, and Weis et al discloses the limitations of claim 8 as explained above. The combination of Briend et al, Yu et al, Cote et al, and Weis et al further discloses
further comprising, after forming the sidewall spacer (silicon oxide layer/isolation collar 32 [column 10, lines 16-23] Fig 2U Weis et al) on each sidewall of the layer-stacked structure (polysilicon filling 31 [column 8, lines 60-67], polysilicon fill 36 [column 12, lines 9-25], and metal strap 38 [column 11, lines 25-35] Fig 2U Weis et al), forming a source EPI structure and a drain EPI structure (source/drain epitaxial growth 60 [0035] Fig 8b Briend et al) in a surface portion of the fin structure (fin structure 18 [0027] Fig 1-2 Briend et al) on opposite sides of the layer-stacked structure (polysilicon filling 31 [column 8, lines 60-67], polysilicon fill 36 [column 12, lines 9-25], and metal strap 38 [column 11, lines 25-35] Fig 2U Weis et al).
Allowable Subject Matter
Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2:
Regarding Claim 2, the combination of Briend et al, Yu et al, Cote et al, and Weis et al discloses the limitations of claim 1 as explained above. The combination of Briend et al, Yu et al, Cote et al, and Weis et al further discloses
wherein thinning the HARP layer (HARP oxide may be included in dielectric material 112 [0020] Fig 1 Yu et al) comprises: performing a chemical mechanical polishing (CMP) process (annealing and planarizing using chemical-mechanical polishing CMP [0021] Yu et al) on the HARP layer (112 Yu et al);
wherein the CMP process stops at the isolation layer (isolation material 106 [0020] Fig 1 Yu et al).
The reason for the indication of allowability of Claim 2 is the inclusion of
performing a wet etching process on the HARP layer resulting from the CMP process, wherein the wet etching process stops upon the remaining portion of the HARP layer reaching a predetermined thickness.
Specifically, should another reference be found that discloses a wet etching process on the HARP layer resulting from the CMP process, it would not be obvious to a person of ordinary skill in the art to make this modification to the combination of Briend et al, Yu et al, Cote et al, and Weis et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 3 would be allowable based on its dependency on Claim 2.
Claim 4:
Regarding Claim 4, the combination of Briend et al, Yu et al, Cote et al, and Weis et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 4 is the inclusion of
wherein the isolation layer comprises an oxide pad layer and a nitride pad layer, which are sequentially stacked one above the other, wherein removing the isolation layer and the HARP layer from the fin structure region comprises: forming a second oxide layer over the semiconductor substrate which has undergone the thinning of the HARP layer; forming a mask layer on the second oxide layer over the DT region; with the mask layer serving as a mask, successively etching the second oxide layer and the HARP layer, thereby exposing the nitride pad layer; with a remaining portion of the second oxide layer serving as a mask, etching the nitride pad layer, thereby exposing the oxide pad layer; and removing an exposed portion of oxide pad layer and the remaining portion of the second oxide layer by performing a wet etching process.
Specifically, the combination of Briend et al, Yu et al, Cote et al, and Weis et al does not disclose these features. Further, should another reference or references be found that includes these features, it would not be obvious to a person of ordinary skill in the art to make this modification to the combination.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 5-7 would be allowable based on their dependency on Claim 4.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ho et al (US 2015/0214244) which discloses deep trench capacitors and isolation structures [0013], and Chou et al (US 2014/0264719) which discloses isolation trench structures [0008].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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