Prosecution Insights
Last updated: April 19, 2026
Application No. 18/531,022

INSERTION OF TRAPS FOR IMPROVED ATTACK DETECTION IN ROUND TRIP TIMING ESTIMATION

Non-Final OA §103
Filed
Dec 06, 2023
Examiner
ACOLATSE, KODZOVI
Art Unit
2478
Tech Center
2400 — Computer Networks
Assignee
Cypress Semiconductor Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
761 granted / 913 resolved
+25.4% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
63 currently pending
Career history
976
Total Applications
across all art units

Statute-Specific Performance

§101
5.0%
-35.0% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 913 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is responsive to Application 18/531,022 filed 12/06/2023 in which claims 1-20 are presented for examination. Allowable Subject Matter Claims 5-8, 13-16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 9-12, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kuchler et al (US 2018/0138993 A1) in view of Yu (US 2004/0028227 A1). Regarding claim 1, Kuchler teaches a wireless device comprising: a transmitter; and logic at least one of coupled to or integrated within the transmitter, the logic to: generate a artifact within a portion of a packet to be transmitted during a round trip timing estimation of an enclosure having a receiver (Kuchler: Fig. 1; [0003]-[0004], [0099]-[0100], generating a validation sequence/artifact, in a packet during a RTT; see also [0025]-[0028]); and cause a frequency of samples of bit patterns of the portion of the packet to be modified based on the artifact before the transmitter transmits the packet to the receiver (Kuchler: Fig. 8; [0098]-[0099], the validation sequence is modify through spreading and interleaving as shown on Fig. 8). Kuchler does not explicitly disclose the artifact is in a frequency domain. Yu discloses frequency domain artifact (Yu: Fig. 1; [0011]; [0037] partial encryption done in the frequency domain). It would have been obvious to a person having an ordinary skill in the art before the effective filling date of the claimed invention to modify the system of Kuchler wherein the artifact is in a frequency domain as disclosed by Yu to provide a system for partial encryption of streamed-formatted media (Yu: Abstract). Regarding claim 9, Kuchler teaches a method comprising: generating, by logic of a transmitter, a artifact within a portion of a packet to be transmitted during a round trip timing estimation of an enclosure having a receiver (Kuchler: Fig. 1; [0003]-[0004], [0099]-[0100], generating a validation sequence/artifact, in a packet during a RTT; see also [0025]-[0028]); and causing a frequency of samples of bit patterns of the portion of the packet to be modified based on the artifact before the transmitter transmits the packet to the receiver (Kuchler: Fig. 8; [0098]-[0099], the validation sequence is modify through spreading and interleaving as shown on Fig. 8). Kuchler does not explicitly disclose the artifact is in a frequency domain. Yu discloses frequency domain artifact (Yu: Fig. 1; [0011]; [0037] partial encryption done in the frequency domain). It would have been obvious to a person having an ordinary skill in the art before the effective filling date of the claimed invention to modify the system of Kuchler wherein the artifact is in a frequency domain as disclosed by Yu to provide a system for partial encryption of streamed-formatted media (Yu: Abstract). Regarding claim 17, Kuchler teaches a system comprising: an antenna; a transmission device that is to transmit a packet; a receiving device to receive the pattern; and logic at least one of coupled to or integrated with the transmission device, the logic to: generate a artifact within a portion of the packet to be transmitted during a round trip timing estimation of an enclosure having the receiving device (Kuchler: Fig. 1; [0003]-[0004], [0099]-[0100], generating a validation sequence/artifact, in a packet during a RTT; see also [0025]-[0028]); and cause a frequency of samples of bit patterns of the portion of the packet to be modified based on the artifact before the transmission device transmits the packet to the receiving device (Kuchler: Fig. 8; [0098]-[0099], the validation sequence is modify through spreading and interleaving as shown on Fig. 8). Kuchler does not explicitly disclose the artifact is in a frequency domain. Yu discloses frequency domain artifact (Yu: Fig. 1; [0011]; [0037] partial encryption done in the frequency domain). It would have been obvious to a person having an ordinary skill in the art before the effective filling date of the claimed invention to modify the system of Kuchler wherein the artifact is in a frequency domain as disclosed by Yu to provide a system for partial encryption of streamed-formatted media (Yu: Abstract). Regarding claims 2, 10 and 18, Kuchler in view of Yu teaches wherein to generate the frequency domain artifact, the logic is to: identify one or more bit patterns within the portion of the packet; and modify one or more bit waveforms of the one or more identified bit patterns (Kuchler: Fig. 8; [0098]-[0099], the validation sequence is modify through spreading and interleaving as shown on Fig. 8). Regarding claims 3 and 11, Kuchler in view of Yu teaches wherein to identify the one or more bit patterns, the logic is further to: randomly perform a Boolean operation on the one or more bit patterns to change a value of a portion of a bit waveform of the one or more bit patterns (Yu: [0037], [0063], [0065]-[0066] XOR/Boolean operation). Regarding claims 4 and 12, Kuchler in view of Yu teaches wherein to modify the one or more bit waveforms, the logic is to: modify a portion of the one or more bit waveforms in a time domain associated with the portion of the packet (Kuchler: Fig. 8; [0098]-[0099], the validation sequence is modify through spreading and interleaving as shown on Fig. 8). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KODZOVI ACOLATSE whose telephone number is (571)270-1999. The examiner can normally be reached Monday to Friday 10 am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Avellino Joseph can be reached at (571) 272-3905. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KODZOVI ACOLATSE/Primary Examiner, Art Unit 2478
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Prosecution Timeline

Dec 06, 2023
Application Filed
Feb 17, 2026
Non-Final Rejection — §103
Apr 06, 2026
Interview Requested
Apr 16, 2026
Applicant Interview (Telephonic)
Apr 16, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+22.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 913 resolved cases by this examiner. Grant probability derived from career allow rate.

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