DETAILED ACTION
This action is responsive to the following: the amended claims and applicant arguments made in amendment filed on December 5, 2025.
Claims 1-4, 6-11, 13-18, and 20 are pending. Claims 1, 8, and 19 are independent. Claims 5, 12, and 19 are cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 5, 2025 was filed after the mailing date of the first office action on September 5, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendment filed on December 5, 2025 has been entered. Claims 1-4, 6-11, 13-18, and 20 remain pending. Claims 5, 12, and 19 are cancelled by applicant. Applicant’s amendment to claims overcome the objections set forth in the previous non-final office action mailed September 5, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-10, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inbar et al (US 20210389879).
Regarding Independent Claim 1, Inbar teaches a system comprising:
a memory device (Fig. 1: 104); and
a processing device (Fig. 1: 102), operatively coupled with the memory device (Fig. 1: 104), to perform operations comprising:
performing a first programming operation (Fig. 14: 2 programming both zones at different WL, WL1, Zone A) on a first set of cells (Fig 14: Plane 0, Plane 1) associated with a first wordline (Fig. 14: WL1) of a first die (Fig. 14: Zone A) of the memory device (Fig. 1: 104);
identifying, based on a first predefined value, a second wordline (Fig. 14: WL0) of a second die (Fig. 14: Zone B) of the memory device (Fig. 1: 104), wherein the first predefined value is a shift in an index value of the first wordline (Fig. 14: WL1) of the first die (Fig. 14: Zone A) of the memory device (Fig. 1: 104); and
performing a second programming operation (Fig. 14: 2 programming both zones at different WL, WL0, Zone B) on a second set of cells (Fig 14: Plane 2, Plane 3) associated with the second wordline (Fig. 14: WL0) of the second die (Fig. 14: Zone B), wherein the second wordline (Fig. 14: WL1) of the second die (Fig. 14: Zone B) is associated with a different index (Fig. 14: 0) value than the first wordline (Fig. 14: WL1) of the first die (Fig. 14: Zone A).
Regarding Claim 2, Inbar teaches the limitations of Claim 1. Inbar further teaches the limitations of claim 1 further comprising:
receiving a request to perform a third programming operation (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL);
identifying, based on a second predefined value, a third wordline of a third die of the memory device, wherein the second predefined value is a shift in an index value of the second wordline of the second die of the memory device; and (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL)
performing the third programming operation on a third set of cells associated with the third wordline of the third die, wherein the third wordline of the third die is associated with a different index value than the first wordline of the first die and the second wordline of the second die. (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL)
Inbar teaches a plurality of die (para 35) and that multiple parallel programming operations can occur in parallel (Fig. 14: programming both zones at different WL) and that this programming method can be used in multi-zone arrangements where each zone consists of two planes each (para 115-116). Thus, a third programming operation in a third die based on a second predefined value is anticipated.
Regarding Claim 3, Inbar teaches the limitations of Claim 1. Inbar further teaches wherein performing the first programming operation comprises performing a write operation (para 114-116; Fig. 14: programming both zones at different WL; the write operation and programming are used interchangeably to refer to the same thing. It is well understood in the art that a write operation and programming operation are the same for non-volatile memories).
Regarding Claim 7, Inbar teaches the limitations of Claim 1. Inbar further teaches wherein the first predefined value is computed using a hardware accelerator (para 34; “The XOR engines 224/254 and ECC engines 226/256 are dedicated hardware circuits, known as hardware accelerators.”) associated with the memory device (Fig. 1: 104).
Regarding Independent Claim 8, Inbar teaches a method comprising:
computing a predefined value associated with each die of a memory device (Fig. 1: 104), wherein the predefined value is a shift in an index value of each wordline associated with each die of the memory device (Fig. 1: 104);
receiving a request to perform a first programming operation (Fig. 14: 2 programming both zones at different WL, WL1, Zone A);
identifying, based on the predefined value, a first wordline (Fig. 14: WL1) of a first die (Fig. 14: Zone A) of the memory device (Fig. 1: 104);
performing the first programming operation (Fig. 14: 2 programming both zones at different WL, WL1, Zone A) on a first set of cells (Fig 14: Plane 0, Plane 1) associated with the first wordline (Fig. 14: WL1) of the first die of the memory device (Fig. 1: 104);
identifying, based on the predefined value, a second wordline (Fig. 14: WL0) of a second die (Fig. 14: Zone B) of the memory device (Fig. 1: 104); and
performing a second programming operation (Fig. 14: 2 programming both zones at different WL, WL0, Zone B) on a second set of cells (Fig 14: Plane 2, Plane 3) associated with the second wordline (Fig. 14: WL0) of the second die (Fig. 14: Zone B) , wherein the second wordline (Fig. 14: WL0) of the second die (Fig. 14: Zone B) is associated with a different index value (Fig. 14: 0) than the first wordline (Fig. 14: WL1) of the first die (Fig. 14: Zone B).
Regarding Claim 9, Inbar teaches the limitations of Claim 8. Inbar further teaches the method of claim 8, further comprising:
receiving a request to perform a third programming operation (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL);
identifying, based on the predefined value, a third wordline of a third die of the memory device (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL); and
performing the third programming operation on a third set of cells associated with the third wordline of the third die, wherein the third wordline of the third die is associated with a different index value than the first wordline of the first die and the second wordline of the second die. (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL)
Inbar teaches a plurality of die (para 35) and that multiple parallel programming operations can occur in parallel (Fig. 14: programming both zones at different WL) and that this is programming method can be used in multi-zone arrangements where each zone consists of two planes each (para 115-116). Thus, a third programming operation in a third die based on a second predefined value is anticipated.
Regarding Claim 10, Inbar teaches the limitations of Claim 8. Inbar further teaches wherein performing the first programming operation comprises performing a write operation (para 114-116; Fig. 14: programming both zones at different WL; the write operation and programming are used interchangeably to refer to the same thing. It is well understood in the art that a write operation and programming operation are the same for non-volatile memories).
Regarding Claim 14, Inbar teaches the limitations of Claim 8. Inbar further teaches wherein the predefined value is computed using a hardware accelerator (para 34; “The XOR engines 224/254 and ECC engines 226/256 are dedicated hardware circuits, known as hardware accelerators.”) associated with the memory device (Fig. 1: 104).
Regarding Independent Claim 15, Inbar teaches a non-transitory computer-readable storage medium (Fig. 1: 104) comprising instructions that, when executed by a processing device (Fig. 1: 102), cause the processing device (Fig. 1: 102) to perform operations comprising:
performing a first programming operation (Fig. 14: 2 programming both zones at different WL, WL1, Zone A) on a first set of cells (Fig 14: Plane 0, Plane 1) associated with a first wordline (Fig. 14: WL1) of a first die (Fig. 14: Zone A) of the memory device (Fig. 1: 104);
identifying, based on a first predefined value, a second wordline (Fig. 14: WL0) of a second die (Fig. 14: Zone B) of the memory device (Fig. 1: 104), wherein the first predefined value is a shift in an index value of the first wordline (Fig. 14: WL1) of the first die (Fig. 14: Zone A) of the memory device (Fig. 1: 104); and
performing a second programming operation (Fig. 14: 2 programming both zones at different WL, WL0, Zone B) on a second set of cells (Fig 14: Plane 2, Plane 3) associated with the second wordline (Fig. 14: WL0) of the second die (Fig. 14: Zone B), wherein the second wordline (Fig. 14: WL1) of the second die (Fig. 14: Zone B) is associated with a different index (Fig. 14: 0) value than the first wordline (Fig. 14: WL1) of the first die (Fig. 14: Zone A).
Regarding Claim 16, Inbar teaches the limitations of Claim 15. Inbar further teaches wherein the processing device (Fig. 1: 102) is to perform operations further comprising:
identifying, based on a second predefined value, a third wordline of a third die of the memory device, wherein the second predefined value is a shift in an index value of the second wordline of the second die of the memory device; and (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL)
performing the third programming operation on a third set of cells associated with the third wordline of the third die, wherein the third wordline of the third die is associated with a different index value than the first wordline of the first die and the second wordline of the second die. (para 116 “The embodiment of FIG. 14 illustrates an embodiment in which multiple zones can be assigned to a single die, and where each of the zones is assigned to multiple planes (two planes each).”; Fig. 14: 2 programming both zones at different WL)
Inbar teaches a plurality of die (para 35) and that multiple parallel programming operations can occur in parallel (Fig. 14: programming both zones at different WL) and that this programming method can be used in multi-zone arrangements where each zone consists of two planes each (para 115-116). Thus, a third programming operation in a third die based on a second predefined value is anticipated.
Regarding Claim 17, Inbar teaches the limitations of Claim 15. Inbar further teaches wherein performing the first programming operation comprises performing a write operation (para 114-116; Fig. 14: programming both zones at different WL; the write operation and programming are used interchangeably to refer to the same thing. It is well understood in the art that a write operation and programming operation are the same for non-volatile memories).
Regarding Claim 20, Inbar teaches the limitations of Claim 15. Inbar further teaches wherein the predefined value is computed using a hardware accelerator (para 34; “The XOR engines 224/254 and ECC engines 226/256 are dedicated hardware circuits, known as hardware accelerators.”) associated with the memory device (Fig. 1: 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6, 11, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Inbar et al (US 20210389879) in view of Krakulak et al (US 20160147582).
Regarding Claim 4, Inbar teaches the limitations of Claim 1.
Inbar teaches applying an index value to one wordline (Fig. 14: WL1) in one die (Fig. 14: Zone A) and a different index value (Fig. 14: WL2) in another die (Fig. 14: Zone B).
Inbar fails to teach a look-up table that can be used to identify word line index values and apply value to shift from one index value in one die to an index value in another.
However, Krakulak teaches a table of word line values for the purpose of performing operations on memory cells (para 39; “Each wordline of a block may be represented in the table.”).
Inbar states that “When programming memory cells to different word lines that are in different fingers of different blocks in different planes of a die, each of the word lines needs to receive a programming voltage Vpgm. Because the word lines are in different sub-blocks of different blocks (and are likely to be at different word line positions), it is likely that one of the word lines will program faster than the other word line due to the different word line positions.” Thus, it would be advantageous to have a table that stores word lines index values that can be used to identify the word line being programmed so a different word line in a different die can be programmed in order to speed up the programming operation.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Krakulak to the teachings of Inbar to produce a memory device that retrieves a predefined value from a table based on a current first word line selected in a first die and then applies the predefined value to the index value of the value of the first word line to select a second word line with a different index value in a second die.
Regarding Claim 6, Inbar teaches the limitations of Claim 1. Inbar Fails to teach wherein the first predefined value is computed based on an error count associated with each die of the memory device.
Krakulak teaches keeping an error count with in the memory (para 3).
It is well understood that correcting for errors in memory arrays often need to be accounted for by counting the number of errors in the cells of the array in order to prevent read errors. Thus, it would be obvious to apply the methodology of counting errors and correcting for it when shifting between word lines that are selected between the die of the memory device.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Krakulak to the teachings of Inbar in order to produce a predefined value used to shift the index value of a first word line in one die to a second value in another word line based on the error count associated with each die.
Regarding Claim 11, Inbar teaches the limitations of Claim 8. Claim 11 is rejected for the same reasons as claim 4.
Regarding Claim 13, Inbar teaches the limitations of Claim 8. Claim 13 is rejected for the same reasons as claim 6.
Regarding Claim 18, Inbar teaches the limitations of Claim 15. Claim 18 is rejected for the same reasons as claim 4.
Response to Arguments
Applicant's arguments filed December 5 2025 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to the rejection under 35 U.S.C. 102(a)(1) of claims is primarily about Inbar failing to anticipate the limitations of clause 5 of Claim 1 and similar limitations described in Claims 8 and 15. Specifically, failing to anticipate a first and second die are not anticipated by Zone A and Zone B in Fig. 14 of Inbar.
Applicant describes die as follows in specification paragraph 11 “A non-volatile memory device is a package of one or more dies. Each die includes one or more planes.” No other description of a die is found within the specification or claims. Since Inbar teaches that Zone A and Zone B contains one or more planes they are analogous to the die described by applicant. Therefore, the previous basis for rejection for these claims is maintained.
Applicant’s response the rejections under 35 U.S.C. 103 is entirely based on the argument that Inbar failing to anticipate the limitations of Independent claims 1, 8 and 15 on which claims 4, 6, 11, 13, and 18 are dependent, then these claims are allowabled. Therefore, since the anticipation rejection under Inbar is maintained for the Independent claims the obviousness rejection of Inbar in view of Krakulak is also maintained for these dependent claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825