Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The Office Action supersedes the Office Action dated 9/28/25. The response date will be reset from the day this new Office Action is mailed.
Claims 1--20 are pending in this application. Claims 1, 11 and 15 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 12/06/23 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14 and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In claim 1, the term “Multi-wire layer” is indefinite unless clearly defined (e.g., does it require three+ metal levels, or just two stacked wires?).
In claim 11, the term “Located at same level” is ambiguous — does “level” mean metallization layer, or planarized CMP surface?
Claims 2-10 and 12-14 are rejected because of their dependency of the rejected claims 1 and 11.
In claim 17, the term “certain minimum distance” is vague — suggest to specify numerical tolerance or process window..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20, as best understood (see the 112 rejection above), are rejected under 35 U.S.C. §103 as being unpatentable over Yu et al. (US 8,699,255) in view of Stansfield (US 9,406,351) and further in view of Miller (US 2011/0302354).
Examiner’s Note:
A reference must be considered in its entirety, not in isolation.”— In re Wesslau, 353 F.2d 238.
“The test for obviousness is what the combined teachings of the references would have suggested to those of ordinary skill in the art.”
— In re Keller, 642 F.2d 413 (CCPA 1981).
Key Note for the Applicant to consider:
There is no legal requirement that: all limitations appear in one figure, or all limitations be disclosed in one paragraph.
This Office Action properly relies on the teachings of the references as a whole, not on a rigid, element-by-element figure overlay.
Also, The examiner used “the cited references are relied upon for their combined teachings as understood by a person of ordinary skill in the art. The Office Action does not require a one-to-one correspondence between individual claim limitations and a single figure or paragraph of any reference. Rather, the rejection properly relies on the collective disclosures of the references, which, when combined, render the claimed subject matter obvious under 35 U.S.C. §103.”
Regarding Independent Claim 1:
Yu et al. disclose a nonvolatile memory device formed on a substrate having a cell area and a peripheral area, with memory cells arranged in a two-dimensional array within the cell area, and peripheral circuitry disposed adjacent to the array (see Yu, FIGS. 1, 2, and 3, and the accompanying description of the memory array and peripheral circuits). Yu further discloses a multi-layer metallization structure extending across both the cell area and the peripheral area, with upper metal layers used for dense cell-array routing and different metal layers used for peripheral routing (see Yu, FIGS. 3A–3C, which illustrate vertical cross-sections of metallization layers across array and peripheral regions).
Claim 1 further requires that a first metal wire arranged in an uppermost portion of the multi-wire layer of the peripheral area is located at a level lower than a second metal wire arranged in an uppermost portion of the multi-wire layer of the cell area.
Stansfield expressly teaches this concept. Stansfield discloses memory architectures in which peripheral routing, including reference and control lines, is intentionally placed at a lower vertical metal level than cell-array interconnects to address routing congestion, parasitic capacitance, and signal integrity (see Stansfield, FIGS. 4 and 5, which depict peripheral metal layers positioned below cell-area wiring, and the corresponding descriptive text explaining vertical metal separation between array and peripheral regions).
Miller further reinforces this arrangement by teaching edge and peripheral routing strategies in nonvolatile memory devices, including the use of lower-level metal layers in peripheral regions while maintaining higher-level metals over the memory array (see Miller, FIGS. 2 and 9, which illustrate metallization stacks and peripheral wiring structures offset vertically from the cell array). Miller explains that such vertical offsets are routinely employed to accommodate dummy structures, isolation layers, and process margins.
A person of ordinary skill in the art would have been motivated to combine Yu’s multi-wire memory array architecture with Stansfield’s vertically differentiated peripheral routing and Miller’s peripheral metal placement techniques in order to achieve predictable improvements in routine ability, manufacturability, and electrical performance. The combination merely applies known layout principles to a known memory structure. Accordingly, claim 1 is obvious.
As for dependent Claims 2–10:
Claims 2–10 depend from claim 1 and recite reference line usage, vertical via connections, MRAM structures, dummy MTJ placement, insulating layers, and transistor-level connectivity. Yu discloses reference line routing within multi-layer metallization stacks (see Yu, FIGS. 2–4).
Stansfield and Miller teach the use of dummy memory structures, vertical vias, insulating layers, and MRAM-specific edge treatments in peripheral regions (see Stansfield, FIG. 5; Miller, FIGS. 8–10).
These features are routine design refinements and would have been obvious to implement. Thus, claims 2–10 are obvious.
Regarding Independent Claim 11:
Claim 11 recites that the first metal wire in the peripheral area and the second metal wire in the cell area are located at the same vertical level, and that these wires are electrically connected by a connection metal wire located at a lower level.
Yu discloses multi-layer interconnect schemes in which same-level metal wires are interconnected through vias and lower-level redistribution layers, particularly when routing across different functional regions of a memory device (see Yu, FIGS. 3B and 4, illustrating same-level metals interconnected through underlying layers).
Stansfield further teaches that lower-level metal layers are routinely used as connection layers, even when the primary functional wires reside at the same vertical level, in order to provide layout flexibility and reduce congestion (see Stansfield, FIG. 6, showing lower-level interconnects linking same-level metals).
Miller explicitly discloses the use of lower-level connection metals to electrically couple functional wiring across cell-array and peripheral regions, particularly near array edges (see Miller, FIGS. 8 and 10, depicting lower-level routing used to connect higher-level metal lines).
A person of ordinary skill in the art would have found it obvious to electrically connect same-level cell-area and peripheral-area metal wires using a lower-level connection metal, as this represents a predictable and well-established routing technique.
As for dependent Claims 12–14:
Claims 12–14 depend from claim 11 and further specify reference line functionality, MRAM device details, vertical via placement, and spacing constraints.
Stansfield explicitly teaches reference line routing and spacing considerations (see Stansfield, FIGS. 5 and 6), while Miller discloses vertical via connections and MRAM edge structures (see Miller, FIGS. 9 and 10). These features represent predictable variations of the combined teachings.
Regarding Independent Claim 15:
Claim 15 recites alternative configurations in which the peripheral-area metal wire is located at the same level or a lower level than the cell-area metal wire, and where electrical coupling is achieved either by a separate connection metal wire or by a third metal wire arranged below the cell-area metal wire.
Yu teaches that memory devices may employ multiple routing topologies, including same-level routing, stepped routing, and routing through underlying metal layers, depending on layout constraints (see Yu, FIGS. 3A–3C).
Stansfield describes these configurations as functionally equivalent design alternatives, selected to optimize layout density and electrical performance (see Stansfield, FIGS. 4–6).
Miller further teaches that using either a dedicated lower-level connection metal or an underlying third metal layer to achieve electrical coupling is a routine design choice in advanced memory processes (see Miller, FIGS. 9 and 10).
A person of ordinary skill in the art would have recognized these alternatives as predictable variations of known routing techniques and would have implemented them without inventive skill.
As for dependent Claims 16–20:
Claims 16–20 depend from claim 15 and further recite alternative connection metal placements, reference line configurations, MRAM structures, dummy MTJ placement, and insulating layer arrangements.
Yu, Stansfield, and Miller collectively disclose these features as standard architectural options in nonvolatile memory devices (see Yu, FIGS. 3–4; Stansfield, FIGS. 4–6; Miller, FIGS. 8–10).
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEN N NGUYEN whose telephone number is (571)272-1879. The examiner can normally be reached Monday- Friday 9am-6pm EST.
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
January 12, 2026
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824