DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 21 January 2026 have been fully considered but they are not persuasive.
Applicant’s argument is that An does not teach or suggest, literally or inherently, " combination circuitry electrically connected to the delay elements and the output terminal, the combination circuitry to combine the delayed signals to generate the reduced slew rate signal, delays associated with the delay elements chosen to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal".
This is not persuasive because the structure of An is identical to the invention as claimed and therefore capable of performing the claimed function. Additionally, An discloses in Paragraph 0039 “The reduced slew rate eliminates higher-frequency components of the driver output 308, which have a tendency to result in EMI emissions”. The higher frequency components of the output driver 308 described in cited Paragraph 0039 were interpreted to be the claimed one or more predetermined frequencies of the reduced slew rate signal.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., frequency specific emissions, frequency response plots, notch depths, or algorithms for delay calculation for specific Hz/MHz values) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-12, and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 2021/0056060).
In regard to Claim 1:
An discloses, in Figure 3, an apparatus, comprising:
an input terminal (306) to receive a signal (310);
delay elements (302) electrically connected to the input terminal (306), the delay elements to provide delayed signals responsive to the received signal (310), respective delayed signals including delayed versions of the received signal (Paragraph 0037);
an output terminal (308) to provide a reduced slew rate signal (312, Paragraph 0039); and
combination circuitry (304) electrically connected to the delay elements (302) and the output terminal (308), the combination circuitry to combine the delayed signals (302 outputs) to generate the reduced slew rate signal (Paragraph 0039), delays associated with the delay elements chosen to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal (Paragraphs 0033 and 0039).
In regard to Claim 2:
An discloses, in Figure 3, the apparatus of claim 1, wherein the combination circuitry includes sub-drivers (sub-drivers of 304), at least some of the sub-drivers electrically connected to drive respective ones of the delayed signals to the output terminal (304 is connected between 310 and 312).
In regard to Claim 3:
An discloses, in Figure 3, the apparatus of claim 2, wherein one of the sub-drivers is electrically connected from the input terminal to the output terminal (304 is connected between 310 and 312).
In regard to Claim 4:
An discloses, in Figure 4, the apparatus of claim 2, wherein at least one of the sub-drivers includes:
a pull-up current source (416) electrically connected to a power supply high voltage potential node (Paragraph 0043);
a pull-down current source (414) electrically connected to a power supply low voltage potential node (Paragraph 0043); and
a complementary metal oxide semiconductor (CMOS) inverter (406) electrically connected from the pull-up current source (416) to the pull-down current source (414).
In regard to Claim 5:
An discloses, in Figure 3, the apparatus of claim 4, wherein a pull-up current supplied by the pull-up current source is substantially the same as a pull-down current supplied by the pull-down current source (Paragraph 0043).
In regard to Claim 6:
An discloses, in Figure 3, the apparatus of claim 1, wherein the combination circuitry includes summing circuitry to combine the delayed signals by adding the delayed signals (Paragraph 0038).
In regard to Claim 7:
An discloses, in Figure 3, the apparatus of claim 1, comprising delay control circuitry (314) electrically connected to the delay elements (302), the delay control circuitry to provide delay control signals to the delay elements to control the delays associated with the delay elements (Paragraph 0038).
In regard to Claim 9:
An discloses, in Figure 3, the apparatus of claim 1, wherein the delay elements are electrically connected in series (302 elements are connected in series).
In regard to Claim 10:
An discloses, in Figure 3, a method of generating a reduced slew rate signal, the method comprising:
delaying (302) a received signal (310) to generate delayed signals (302 output) using delays chosen to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal (Paragraph 0037); and
combining (304 outputs combined at 308) the delayed signals (302 outputs) to generate the reduced slew rate signal at (312, Paragraph 0037) an output terminal (308).
In regard to Claim 11:
An discloses, in Figure 3, the method of claim 10, wherein combining the delayed signals (302 outputs) comprises driving, with sub-drivers (304), the delayed signals to summing circuitry electrically connected to the output terminal (Paragraph 0038).
In regard to Claim 12:
An discloses, in Figure 3, the method of claim 10, comprising selecting the delays using delay control circuitry (314) electrically connected to delay elements associated with the delays (Paragraph 0038).
In regard to Claim 14:
An discloses, in Figure 3, a system, comprising:
a shared transmission medium of a wired local area network (Figure 2: 104);
an encoder (Figure 2: 202) to provide a signal to be transmitted to the wired local area network via the shared transmission medium (Figure 2: 104, Paragraph 0029); and
a variable delay driver (Figure 2: 300) comprising:
an input terminal (306) to receive the signal (310) from the encoder (Figure 2: 202);
delay elements (302) to generate delayed signals (302 outputs) responsive to the received signal (310), delays associated with respective ones of the delay elements chosen to reduce emissions of one or more predetermined frequencies of a reduced slew rate signal as compared to the received signal (Paragraph 0037);
combination circuitry (304) to combine the delayed signals to generate the reduced slew rate signal (312, Paragraph 0039); and
an output terminal (308) electrically connected to the shared transmission medium, the output terminal to deliver the reduced slew rate signal (312) to the shared transmission medium (Figure 2: 104, Paragraph 0029).
In regard to Claim 15:
An discloses, in Figure 3, the system of claim 14, comprising a vehicle including the shared transmission medium, the vehicle including endpoints electrically connected to the shared transmission medium, at least one of the endpoints including the encoder and the variable delay driver (Paragraph 0022).
In regard to Claim 16:
An discloses, in Figure 3, the system of claim 15, wherein the one or more predetermined frequencies include one or more operating frequencies of one or more devices operating in the vehicle (Paragraph 0022).
Allowable Subject Matter
Claims 8 and 13 are allowed.
In regard to Claim 8:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the one or more predetermined frequencies include three predetermined frequencies; and the delay control circuitry to: determine three different preliminary delays associated with the three predetermined frequencies for three hypothetical first-order notch filters; determine eight intermediate total delays associated with chaining the three hypothetical first-order notch filters together; sort the eight intermediate total delays in ascending order; determine seven delay differences by subtracting, for respective ones of the eight intermediate total delays except for a lowest intermediate delay, the intermediate total delays from immediately subsequent ones of the intermediate total delays; and select the delays associated with the delay elements to be the respective delay differences.
In regard to Claim 13:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein selecting the delays using delay control circuitry electrically connected to delay elements associated with the delays, comprises: determining three different preliminary delays associated with three predetermined frequencies for three hypothetical first-order notch filters; determining eight intermediate total delays associated with chaining the three hypothetical first-order notch filters together; sorting the eight intermediate total delays in ascending order; determining seven delay differences by subtracting, for respective ones of the eight intermediate total delays except for a lowest intermediate delay, the intermediate total delays from immediately subsequent ones of the intermediate total delays; and selecting the delays associated with the delay elements to be the delay differences.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2896