Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 2, 3, 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 104752571 A) hereafter referred to as Feng in view of Tanaka (JP 2002018830 A)
In regard to claim 1 Feng teaches a wafer singulating method [see Figs. 2a-2e] comprising:
providing a wafer product [“As shown in FIG. 2, a white light LED chip for wafer cutting method, comprising the silicon substrate 201 prepared on the GaN wafer with vertical structure”] having a front side [top] and a back side [bottom] opposite to each other, the front side of the wafer product having [“FIG. 1 is a chip through chip laser after cutting; transverse and vertical line is a cutting channel” see the scribe lines are the known path where the laser is pointed, i.e. the laser cutting is not random, it follows a known path i.e. the “scribe line”] a plurality of scribe lines;
deep scribing the wafer product with a laser [“gallium nitride LED 203 separated by slicing trails 204, 355nm ultraviolet laser emitted by focusing the laser cutting path 204 of the middle position to the upper surface of the silicon substrate 201, forming a groove having a depth of 30 + 5 microns, the width is 10 +/2 mu m of the groove 205”] along the scribe lines from the front side of the wafer product to form a plurality of intersecting trenches [“FIG. 1 is a chip through chip laser after cutting; transverse and vertical line is a cutting channel”, see groove 205] on the front side of the wafer product;
but does not state:
cleaving the back side of the wafer product along the trenches on the front side of the wafer product; wherein the cleaving proceeds in different directions each of which is directed to a center of the wafer product from a periphery of the wafer product, and the cleaving in each of the directions proceeds along the trenches one after the other from one of the trenches nearest to the periphery of the wafer product and ceases near or at the center of the wafer product.
See the entire dicing process “as shown in FIG. 2d; adopts the blade cutting process, cutting the back of the wafer, the position of cutting the groove 205 corresponding to form cutting groove connected with the groove 205 of 208, as shown in FIG. 2e; along the groove of the wafer front surface 205 for splitting. obtaining the single white light LED chip” i.e. all the intersecting scribe lines in Fig. 1 are cut all the way through to form the individual dies i.e. singulation of the wafer.
See Tanaka teaches an easy way to cleave a wafer, see Fig. 1, Fig. 2 “FIG. 1 is a cross-sectional view showing an example of an embodiment of a ceramic substrate dividing apparatus according to the present invention, wherein 1 is a lower endless belt, 2 is an upper endless belt, 3 is a support plate, 4 is a support roller, and 5 is a pressing roller” “When the ceramic substrate 11 passes between the transfer section 7 and the holding section 9 and reaches the support roller 4 as shown in FIG. While being supported by the support roller 4 via the belt 1, a pressing force is applied from the support roller 4 onto the first division groove 13 by the pressing roller 5, whereby the ceramic substrate 11 is divided along the division groove 13” “Thus, according to the ceramic substrate dividing apparatus of the present invention, the supply substrate 7a is provided with the ceramic substrate 11 in the dividing groove. 13 is supplied so as to be substantially perpendicular to the moving direction of the transfer unit 7, and the ceramic substrate 11 is passed between the transfer unit 7 and the pressing unit 9 as the transfer unit 7 moves, By applying the pressing force to the ceramic substrate 11, the ceramic substrate 11 is accurately and reliably divided along the dividing grooves 13. The ceramic substrate 11 shown in FIG. 1 has division grooves 13 formed vertically and horizontally. In this case, for example, the ceramic substrate 11 is first divided along the division grooves 13 in the vertical direction, and then divided. These may be divided along the dividing groove 13 in the horizontal direction” “Further, the dividing groove 13 does not need to be formed on both the upper and lower surfaces, and may be formed only on the lower surface” as can be seen, in Tanaka’s method the cleaving is starting from the outermost scribe line and moving toward the center of the wafer i.e. one after the other, and similarly in a perpendicular direction.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include the cleaving of Tanaka i.e. to modify Feng to include cleaving the back side of the wafer product along the trenches on the front side of the wafer product; wherein the cleaving proceeds in different directions each of which is directed to a center of the wafer product from a periphery of the wafer product, and the cleaving in each of the directions proceeds along the trenches one after the other from one of the trenches nearest to the periphery of the wafer product and ceases near or at the center of the wafer product.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the method of Tanaka is easy and gives an excellent clean cleaved edge for singulating the wafer into individual LED chips.
In regard to claim 4 Feng and Tanaka as combined teaches wherein a ratio of a depth of the trench to [see Feng “Preferably, the depth of the groove is after grinding and thinning the thickness of the substrate is 1/10 to 1/2, the width is 10 + 2 microns”] a thickness of the wafer product ranges from 1: 5 to 1: 2.
Claim(s) 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng and Tanaka as combined and further in view of Nagai (US 20060284195 A1)
In regard to claim 5 Feng and Tanaka as combined does not specifically teach wherein the front side of the wafer product further includes an epitaxial layer that has a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack.
See Feng teaches GaN LED.
See Nagai Fig. 14B see paragraph 0144 “white LED chip 2002” “multilayer epitaxial structure 2006 is made up of a p-AlGaN layer 2010 which is a conductive layer (having a thickness of 200 nm), a InGaN/AlGaN MQW light emitting layer 2012 (having a thickness of 40 nm), and an n-AlGaN layer 2014 which is a conductive layer (having a thickness of 2 .mu.m). The layer 2010 is the closest to the Si Substrate 2004, and then the layers 2012 and 2014 are formed in the stated order. The multilayer epitaxial structure 2006 has a diode structure” “An anode power supply terminal 2030 and a cathode power supply terminal 2032 which are made of Ti/Au are formed on a lower main surface of the Si substrate 2004 which is opposite to a main surface on which the multilayer epitaxial structure 2006 is formed” “extended portion 2018A is used to electrically connect the conductive film 2018 to the anode power supply terminal 2030 by a through hole 2034” “wiring 2036 is connected at its one end to a corner portion 2026A of the L-shaped electrode 2026, and extends, from the corner portion 2025A, to a periphery of the upper main surface of the n-AlGaN layer 2014” , see also Fig. 2B wherein “a Ti/Au electrode 24 of the LED 6a is a cathode electrode 32 of the LED array chip 2” “an Ni/Au thin film 20 and an ITO transparent electrode 22 of the LED 6d are an anode electrode 34 of the LED array chip 2”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include wherein the front side of the wafer product further includes an epitaxial layer that has a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that this is a standard LED structure known to give good results to emit light.
In regard to claim 6 Feng Tanaka and Nagai as combined does not specifically wherein the trenches formed by deep scribing the front side of the wafer product extend through the epitaxial layer.
However see that light emitted is based on the area of the LED.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include wherein the trenches formed by deep scribing the front side of the wafer product extend through the epitaxial layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use the entire available area to obtain more light.
Claim(s) 8, 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 104752571 A) hereafter referred to as Feng in view of Tanaka (JP 2002018830 A)
In regard to claim 8 Feng teaches an LED chip [see Figs. 2a-2e] comprising a singulated wafer product [“As shown in FIG. 2, a white light LED chip for wafer cutting method, comprising the silicon substrate 201 prepared on the GaN wafer with vertical structure” “FIG. 1 is a chip through chip laser after cutting; transverse and vertical line is a cutting channel”] having a front side [top] and a back side [bottom] disposed opposite to each other, and
a side wall [see the LED is singulated with sidewalls of “cutting the back of the wafer, the position of cutting the groove 205 corresponding to form cutting groove connected with the groove 205 of 208, as shown in FIG. 2e; along the groove of the wafer front surface 205 for splitting. obtaining the single white light LED chip” “combining blade back cutting and cleaving process, it can smoothly realize the separation of wafer white light LED chip to the front surface of the wafer”] extending transversely between said front and back sides;
wherein an end of said side wall proximate to said front side is formed with a recast [recast is due to laser melting and cutting “gallium nitride LED 203 separated by slicing trails 204, 355nm ultraviolet laser emitted by focusing the laser cutting path 204 of the middle position to the upper surface of the silicon substrate 201, forming a groove having a depth of 30 + 5 microns, the width is 10 +/2 mu m of the groove 205”] portion,
but even though Feng mentions “cleaving process”, Feng does not show in Fig. 2e that the side wall is cleaved and an end of said cleaved side wall proximate to said back side being a smooth side wall surface portion.
See Tanaka teaches an easy way to cleave a wafer, see Fig. 1, Fig. 2 “FIG. 1 is a cross-sectional view showing an example of an embodiment of a ceramic substrate dividing apparatus according to the present invention, wherein 1 is a lower endless belt, 2 is an upper endless belt, 3 is a support plate, 4 is a support roller, and 5 is a pressing roller” “When the ceramic substrate 11 passes between the transfer section 7 and the holding section 9 and reaches the support roller 4 as shown in FIG. While being supported by the support roller 4 via the belt 1, a pressing force is applied from the support roller 4 onto the first division groove 13 by the pressing roller 5, whereby the ceramic substrate 11 is divided along the division groove 13” “Thus, according to the ceramic substrate dividing apparatus of the present invention, the supply substrate 7a is provided with the ceramic substrate 11 in the dividing groove. 13 is supplied so as to be substantially perpendicular to the moving direction of the transfer unit 7, and the ceramic substrate 11 is passed between the transfer unit 7 and the pressing unit 9 as the transfer unit 7 moves, By applying the pressing force to the ceramic substrate 11, the ceramic substrate 11 is accurately and reliably divided along the dividing grooves 13. The ceramic substrate 11 shown in FIG. 1 has division grooves 13 formed vertically and horizontally. In this case, for example, the ceramic substrate 11 is first divided along the division grooves 13 in the vertical direction, and then divided. These may be divided along the dividing groove 13 in the horizontal direction” “Further, the dividing groove 13 does not need to be formed on both the upper and lower surfaces, and may be formed only on the lower surface” as can be seen, in Tanaka’s method the cleaving is starting from the outermost scribe line and moving toward the center of the wafer i.e. one after the other, and similarly in a perpendicular direction.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include the cleaving of Tanaka i.e. to modify Feng to include that the side wall is cleaved and an end of said cleaved side wall proximate to said back side being a smooth side wall surface portion.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the method of Tanaka is easy and gives an excellent clean cleaved edge for singulating the wafer into individual LED chips.
In regard to claim 9 Feng and Tanaka as combined teaches wherein a ratio of a thickness (D0) of said recast portion to [see Feng “Preferably, the depth of the groove is after grinding and thinning the thickness of the substrate is 1/10 to 1/2, the width is 10 + 2 microns”] a thickness (D) of said cleaved side wall ranges from 1: 5-1: 2.
In regard to claim 11 Feng and Tanaka as combined teaches wherein an angle [see it is 90 degrees] between said cleaved side wall (CS) and said back side ranges from 85° to 95°.
Claim(s) 10, 12, 13, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng and Tanaka as combined and further in view of Nagai (US 20060284195 A1)
In regard to claim 10 Feng and Tanaka as combined teaches wherein: said singulated wafer product [see Feng teaches GaN LED, see Fig. 1 see rectangular shape] has a rectangular cross section on a plane perpendicular to a thickness direction of said singulated wafer product; but does not specifically teach a ratio of a length (L) of said singulated wafer product to a thickness (D) of said cleaved sidewall is no less than 4; and a ratio of a width (W) of said singulated wafer product to said thickness (D) of said cleaved side wall is no less than 4.
See Nagai Fig. 14B see paragraph 0144 “white LED chip 2002” “multilayer epitaxial structure 2006 is made up of a p-AlGaN layer 2010 which is a conductive layer (having a thickness of 200 nm), a InGaN/AlGaN MQW light emitting layer 2012 (having a thickness of 40 nm), and an n-AlGaN layer 2014 which is a conductive layer (having a thickness of 2 .mu.m). The layer 2010 is the closest to the Si Substrate 2004, and then the layers 2012 and 2014 are formed in the stated order. The multilayer epitaxial structure 2006 has a diode structure” “The LED chip 2002 is a 500-.mu.m-square and has a thickness of 300 .mu.m (the Si substrate 2004 has a thickness of 100 .mu.m, and the phosphor film 2008 has a thickness of 200 .mu.m with respect to an upper main surface of the Si substrate 2004). The multilayer epitaxial structure 2006 has the above-mentioned thickness and is a 420-.mu.m-square”.
However see that light emitted is based on the area of the LED.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “a ratio of a length (L) of said singulated wafer product to a thickness (D) of said cleaved sidewall is no less than 4; and a ratio of a width (W) of said singulated wafer product to said thickness (D) of said cleaved side wall is no less than 4”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 12 Feng and Tanaka as combined does not specifically teach wherein: Said front side of said singulated wafer product further has an epitaxial layer wafer product which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said back side of said singulated wafer product and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.
See Feng teaches GaN LED.
See Nagai Fig. 14B see paragraph 0144 “white LED chip 2002” “multilayer epitaxial structure 2006 is made up of a p-AlGaN layer 2010 which is a conductive layer (having a thickness of 200 nm), a InGaN/AlGaN MQW light emitting layer 2012 (having a thickness of 40 nm), and an n-AlGaN layer 2014 which is a conductive layer (having a thickness of 2 .mu.m). The layer 2010 is the closest to the Si Substrate 2004, and then the layers 2012 and 2014 are formed in the stated order. The multilayer epitaxial structure 2006 has a diode structure” “An anode power supply terminal 2030 and a cathode power supply terminal 2032 which are made of Ti/Au are formed on a lower main surface of the Si substrate 2004 which is opposite to a main surface on which the multilayer epitaxial structure 2006 is formed” “extended portion 2018A is used to electrically connect the conductive film 2018 to the anode power supply terminal 2030 by a through hole 2034” “wiring 2036 is connected at its one end to a corner portion 2026A of the L-shaped electrode 2026, and extends, from the corner portion 2025A, to a periphery of the upper main surface of the n-AlGaN layer 2014”, see also Fig. 2B wherein “a Ti/Au electrode 24 of the LED 6a is a cathode electrode 32 of the LED array chip 2” “an Ni/Au thin film 20 and an ITO transparent electrode 22 of the LED 6d are an anode electrode 34 of the LED array chip 2”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include wherein: Said front side of said singulated wafer product further has an epitaxial layer wafer product which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said back side of said singulated wafer product and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that this is a standard LED structure known to give good results to emit light and to provide electrode connection with easy connectivity to an external circuit.
In regard to claim 13 Feng and Tanaka as combined does not specifically teach wherein: Said front side of said singulated wafer product further has an epitaxial layer which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said epitaxial layer and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.
See Feng teaches GaN LED.
See Nagai Fig. 14B see paragraph 0144 “white LED chip 2002” “multilayer epitaxial structure 2006 is made up of a p-AlGaN layer 2010 which is a conductive layer (having a thickness of 200 nm), a InGaN/AlGaN MQW light emitting layer 2012 (having a thickness of 40 nm), and an n-AlGaN layer 2014 which is a conductive layer (having a thickness of 2 .mu.m). The layer 2010 is the closest to the Si Substrate 2004, and then the layers 2012 and 2014 are formed in the stated order. The multilayer epitaxial structure 2006 has a diode structure” “An anode power supply terminal 2030 and a cathode power supply terminal 2032 which are made of Ti/Au are formed on a lower main surface of the Si substrate 2004 which is opposite to a main surface on which the multilayer epitaxial structure 2006 is formed” “extended portion 2018A is used to electrically connect the conductive film 2018 to the anode power supply terminal 2030 by a through hole 2034” “wiring 2036 is connected at its one end to a corner portion 2026A of the L-shaped electrode 2026, and extends, from the corner portion 2025A, to a periphery of the upper main surface of the n-AlGaN layer 2014”, see also Fig. 2B wherein “a Ti/Au electrode 24 of the LED 6a is a cathode electrode 32 of the LED array chip 2” “an Ni/Au thin film 20 and an ITO transparent electrode 22 of the LED 6d are an anode electrode 34 of the LED array chip 2”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include wherein: Said front side of said singulated wafer product further has an epitaxial layer which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said epitaxial layer and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that this is a standard LED structure known to give good results to emit light and to provide electrode connection with easy connectivity to an external circuit.
In regard to claim 14 Feng and Tanaka as combined does not specifically teach a light-emitting module comprising a printed circuit board (PCB), and a light-emitting device disposed on said PCB, said light-emitting device including the LED chip as claimed in claim 8.
See Feng teaches GaN LED.
See Nagai Fig. 14B see paragraph 0144 “white LED chip 2002” “multilayer epitaxial structure 2006 is made up of a p-AlGaN layer 2010 which is a conductive layer (having a thickness of 200 nm), a InGaN/AlGaN MQW light emitting layer 2012 (having a thickness of 40 nm), and an n-AlGaN layer 2014 which is a conductive layer (having a thickness of 2 .mu.m). The layer 2010 is the closest to the Si Substrate 2004, and then the layers 2012 and 2014 are formed in the stated order. The multilayer epitaxial structure 2006 has a diode structure” “An anode power supply terminal 2030 and a cathode power supply terminal 2032 which are made of Ti/Au are formed on a lower main surface of the Si substrate 2004 which is opposite to a main surface on which the multilayer epitaxial structure 2006 is formed” “extended portion 2018A is used to electrically connect the conductive film 2018 to the anode power supply terminal 2030 by a through hole 2034” “wiring 2036 is connected at its one end to a corner portion 2026A of the L-shaped electrode 2026, and extends, from the corner portion 2025A, to a periphery of the upper main surface of the n-AlGaN layer 2014”, see also paragraph 0005, 0113 “In the assembly process, the LED bare chip is mounted on a lead frame, a printed-wiring board or the like since the LED bare chip alone can not be put to use” “FIG. 8 is a perspective view illustrating an LED module relating to the first embodiment” “to attach the LED module 200 to the lighting unit 240 and terminals 212 and 214 to receive a power supply from the lighting unit 240 are provided in the ceramics substrate 202”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Feng to include a light-emitting module comprising a printed circuit board (PCB), and a light-emitting device disposed on said PCB, said light-emitting device including the LED chip as claimed in claim 8.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use the LED to emit light as lighting unit.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893