DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Responses to Amendments and Arguments
The amendments filed 07/01/2026 have been entered. Claims 1-3, 6-8 and 11-13 are amended. Claims 1-15 remain pending in the application.
Applicant’s amendments filed 07/01/2026 have been fully considered and overcome the claim objection previously set forth in the Non-Final Office Action mailed 04/02/2026.
Applicant's arguments filed 07/01/2026 with respect to the interpretation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph have been fully considered and are partially persuasive. As per Applicant’s arguments, “a logic test module” and “an analog test module” in claims 6 and 11 are interpreted as described in Fig. 1 and paragraphs 0005-0006, 0015 and 0019-0022. (See the updated action and Examiner’s notes set forth below).
Applicant's amendments filed 01/06/2025 with respect to the rejection of claims 6-15 under 35 U.S.C. 112(a) or 112 (pre-AIA ), first paragraph have been fully considered and are persuasive. Thus, the rejection of claims 6-15 under 35 U.S.C. 112(a) or 112 (pre-AIA ), first paragraph has been withdrawn.
Applicant’s amendments and arguments filed 07/01/2026, with respect to the rejection of claims 1-15 under 35 U.S.C. 102 have been fully considered but are not persuasive.
On pages 8-12 of the Remarks, Applicant alleges that SCHAT does not disclose several material limitations of claims 1, 6, and 11, and consequently does not anticipate any of claims 1-15. First, the pending claims require a safety detection circuit within the automotive IC to perform a self-test that determines whether an analog voltage of an analog circuit block of that same automotive IC falls within a predetermined safety range. On the other hand, SCHAT does not disclose such an arrangement. … SCHAT concerns board-level analog boundary testing of analog 1/0 paths, including the transfer, routing, or sampling of analog signals between ICs and a PCB-level analog test bus. SCHAT does not disclose that an analog boundary test circuit of analog circuit blocks 246, 250, or 254 monitors an analog voltage generated by its associated analog circuit block against a safety range. Nor does SCHAT disclose a safety detection circuit that determines whether such an internal analog voltage is within a safety range. SCHAT also does not disclose generating an analog test result from such a safety-range determination. … SCHAT does not disclose, in a factory-test operation involving an external tester, that the ET concurrently acts as a safety detection circuit which performs an analog-voltage self-test of an automotive IC. Third, the Office Action further relies on SCHAT's comparison of received test data with expected data. That comparison does not satisfy the claimed analog test result limitation. … Such a serial test-data comparison is not a determination that an analog voltage of an analog circuit block falls within a predetermined safety range. … SCHAT' s statement that analog circuit blocks may include an ADC does not disclose an ADC that forms part of a safety detection circuit, converts a monitored analog voltage for safety-range verification, and provides a resulting digital code to a controller for generation of an analog test result. … Fourth, the independent claims require that, while the automotive IC is generating one or more logic test output signals, a safety detection circuit within that automotive IC performs the analog-voltage self-test. SCHAT does not disclose that arrangement. SCHAT's factory-test operation involves a serial boundary-scan data stream supplied by an external tester and a resulting serial data stream returned from a scan chain (e.g., SCHAT's paragraphs [0009] and [0019]). … SCHAT does not disclose that a safety detection circuit performs such a safety-range determination during the generation of logic test output signals. Nor does SCHAT disclose that its analog boundary test functionality is performed concurrently with a logic test in the manner recited by the claims. … SCHAT does not disclose these separate result sources or the claimed combined determination. … SCHA T does not disclose an analog test result generated by a safety detection circuit based on a determination that an analog voltage lies within a predetermined safety range. SCHAT also does not disclose that an external testing machine receives such an analog test result separately from logic test output signals and determines a factory-test disposition according to both distinct results. … SCHAT does not disclose the required tester-side determination based on both claimed categories of results
Examiner respectfully disagrees.
At least Fig. 2 and paragraphs 0017 and 0019-0021, 0024 of SCHAT teach the claimed features related to “while the automotive IC is generating the one or more logic test output signals, utilizing a safety detection circuit (Fig. 1, 142; Fig. 2, 242 arranged in IC 210) within the automotive IC to perform a self-test to determine whether at least one analog voltage of an analog circuit block of the automotive IC falls within a predetermined safety range to generate an analog test result”, because the ET 242 (i.e., a safety detection circuit) in Fig. 2 is arranged within IC 210, and performs a test by detecting a mismatch between the received data stream TDOT and expected data to thereby generate an error indication. Under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-0021 teach providing test signals during the factory testing and outputs for providing test data, where the test signals send logic circuit blocks 212, 222 as well as analog circuit block 246, 250. Further, at least paragraphs 0019-0021 teach detecting an error by comparing the test resulting data with the reference (i.e., expected data) (“compares received data with expected data. When a mismatch occurs, an error may be detected”). Under the broadest reasonable interpretation, a predetermined safety range may be indicative of a reference, threshold, or value/data used to determine an error detection which is taught by the expected data at least at paragraphs 0019-0021 in SCHAT.
Furthermore, at least paragraph 0026 teaches that in a test mode, a voltage or current value of analog circuit blocks 246, 250, 254 used to detect an error (“In the test mode, the TAP controllers 214, 224, and 234 are configured to provide command signals to respective analog boundary test circuits of analog circuit blocks 246, 250, and 254 to control analog signals transferred between respective analog circuit blocks 246, 250, and 254 and bus 264. For example, a voltage or current value may be transferred from analog circuit block 246 and routed to analog circuit block 254 by way of bus 264 and respective connection lines 258 and 262”).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a logic test module” and “an analog test module” in claims 6 and 11, which are interpreted as described in Fig. 1 and paragraphs 0005-0006, 0015 and 0019-0022.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner Notes:
Examiner recommends amending the claim terms, “module” as “circuit” to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SCHAT (US 20200174070 A1, hereinafter referred to as “SCHAT” cited in IDS dated 06/23/2025).
Regarding Claim 1, SCHAT teaches a test method for performing a factory test on an automotive integrated circuit (IC) (Fig. 2; ICs 206-210) (Abstract and paragraph 0019 teaches providing a factory test on an IC), comprising:
performing a logic test on the automotive IC by sending one or more logic test input signals to the automotive IC to generate one or more logic test output signals (Fig. 2; under the broadest reasonable interpretation, at least paragraphs 0019-21 teach providing test signals during the factory testing and outputs for providing test data, where the test signals send logic circuit blocks 212, 222 as well as analog circuit block 246, 250);
while the automotive IC is generating the one or more logic test output signals, utilizing a safety detection circuit (Fig. 1, 142; Fig. 2, 242 arranged in IC 210) , paragraph 0017 teaches “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”; para 0024, “ET 242 is embedded within IC 210 and configured to provide test commands by way of test control signals”) within the automotive IC to perform a self-test to determine whether at least one analog voltage of an analog circuit block (Fig. 2, an analog circuit block 246, 250, 254) of the automotive IC falls within a predetermined safety range (expected data) to generate an analog test result (Fig. 2; under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-0021 teach providing test signals during the factory testing and outputs for providing test data, where the test signals send logic circuit blocks 212, 222 as well as analog circuit block 246, 250. Further, at least paragraphs 0019-21 teach detecting an error by comparing the test resulting data with the reference (i.e., expected data), “compares received data with expected data. When a mismatch occurs, an error may be detected”; Furthermore, at least paragraph 0026 teaches that in a test mode, a voltage or current value of analog circuit blocks 246, 250, 254 used to detect an error, “In the test mode, the TAP controllers 214, 224, and 234 are configured to provide command signals to respective analog boundary test circuits of analog circuit blocks 246, 250, and 254 to control analog signals transferred between respective analog circuit blocks 246, 250, and 254 and bus 264. For example, a voltage or current value may be transferred from analog circuit block 246 and routed to analog circuit block 254 by way of bus 264 and respective connection lines 258 and 262”); and
determining whether the automotive IC passes the factory test according to at least the logic test output signals and the analog test result (under the broadest reasonable interpretation, at least paragraphs 0017 and 0019 teaches detecting an error by comparing the test resulting data with the reference (i.e., expected data), “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated” and “compares received data with expected data. When a mismatch occurs, an error may be detected”).
Regarding Claim 2, SCHAT teaches wherein the safety detection circuit of the automotive IC comprises an analog-to-digital converter (ADC) (Para 0021, “may include any number or type of analog circuits such as analog-to-digital converter”), and the ADC is configured to convert the at least one analog voltage into a digital code, and the step of determining whether the at least one analog voltage falls within the predetermined safety range comprises:
utilizing a controller (Fig. 2, controller 214, 224, 234) within the automotive IC to determine whether the digital code falls within the predetermined safety range to generate the analog test result (Under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-21 teach converting analog values of I/O signals into digital signals (i.e., a digital code) and determine if the error is detected by comparing the test resulting data with the reference (i.e., expected data)).
Regarding Claim 3, SCHAT teaches wherein the safety detection circuit of the automotive IC comprises a comparator (Fig. 1, 142), and the comparator is configured compare the at least one analog voltage of one or more predetermined voltages, and the step of determining whether the at least one analog voltage falls within the predetermined safety range comprises:
utilizing the comparator to determine whether the at least one analog voltage falls within the predetermined safety range to generate comparison results (Fig. 1, 142, at least paragraphs 0017 and 0027 teach “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”); and
utilizing a controller (Fig. 2, controller 214, 224, 234) within the automotive IC to generate the analog test result (error indication) based on the comparison result (Under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-21 teach detecting the error by comparing the test resulting data with the reference (i.e., expected data) and generate error indication based on the comparison).
Regarding Claim 4, SCHAT teaches wherein the automotive IC comprises
one or more analog circuit blocks (Fig. 2, 246, 250, and 254) and the one or more analog circuit blocks comprises at least one of a voltage regulator, an oscillator, a driver circuit, an amplifier, a filter, a mixer, a comparator, a signal modulator, a phase-locked loop (PLL), a current mirror, a charge pump, a reference voltage/current generating circuit and/or an analog-to-digital or a digital-to-analog converter (at least paragraph 0021 teaches “Analog circuit blocks 246, 250, and 254 include analog boundary test circuits and may include any number or type of analog circuits such as analog-to-digital converter, digital-to-analog converter, PLL, bias circuit, voltage and/or current reference circuit, current mirror, amplifier, filter, and so on”).
Regarding Claim 5, SCHAT teaches wherein the safety detection circuit is further operated to generate the analog test result during a boot-up process or a normal operation of the automotive IC (Fig. 1, 142, under the broadest reasonable interpretation, at least paragraphs 0019-21 teach providing test signals during the factory testing and outputs for providing test data. And paragraphs 0009 and 0017 teach “While in a factory test mode, external tester 104 may provide a serial data stream by way of the TDI output signal to the first IC 106 of a scan chain formed by the daisy-chained interconnected ICs 106-110. In turn, external tester 104 receives a resulting data stream from the last IC of the scan chain by way of the TDO signal and compares received data with expected data. When a mismatch occurs, an error may be detected” and “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”).
Regarding Claim 6, it is a device type claim having similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above. The additional limitation of a testing machine is taught by SCHAT at least at Fig. 2, 204. The additional limitations of a logic test module and an analog test module are taught by taught by SCHAT at least at Fig. 2, tester 204, because, under the broadest reasonable interpretation, structure and features of the tester 204 teach both the logic test module and the analog test module, where external tester 204 includes outputs for providing test signals and receives a resulting data stream from the IC, and compares received data stream with expected data, when a mismatch occurs, an error may be detected (see paragraphs 0017-0021, especially paragraph 0019).
Regarding Claim 7, it is dependent on claim 6 and has similar limitations as of claim 2 above. Therefore, it is rejected under the same rationale as of claim 2 above.
Regarding Claim 8, it is dependent on claim 6 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 9, it is dependent on claim 6 and has similar limitations as of claim 4 above. Therefore, it is rejected under the same rationale as of claim 4 above.
Regarding Claim 10, it is dependent on claim 6 and has similar limitations as of claim 5 above. Therefore, it is rejected under the same rationale as of claim 5 above.
Regarding Claim 11, it is a system type claim and has similar limitations as of claims 1 and 6 above. Therefore, it is rejected under the same rationale as of claims 1 and 6 above.
Regarding Claim 12, it is dependent on claim 11 and has similar limitations as of claim 2 above. Therefore, it is rejected under the same rationale as of claim 2 above.
Regarding Claim 13, it is dependent on claim 11 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 14, it is dependent on claim 11 and has similar limitations as of claim 4 above. Therefore, it is rejected under the same rationale as of claim 4 above.
Regarding Claim 15, it is dependent on claim 11 and has similar limitations as of claim 5 above. Therefore, it is rejected under the same rationale as of claim 5 above.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abhishek et al. (US 10191110 B2) teaches an integrated circuit and a method of self-testing the integrated circuit are provided by: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage.
Shin et al. (US 20230280398 A1) teaches a temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BYUNG RO LEE whose telephone number is (571)272-3707. The examiner can normally be reached on Monday-Friday 8:30am-4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-2555.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BYUNG RO LEE/Examiner, Art Unit 2858
/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858
Prosecution Insights