DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) were submitted on 06/23/2025 and 09/19/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
In claim 3, line 10, “utilizing the utilizing a controller within” may have typo graphical error and it should respectively read “utilizing a controller within”. (Emphasis added).
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a logic test module” and “an analog test module” in claims 6 and 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections – 35 USC § 112(a)
The following is a quotation of the paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-10 and 11-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first Paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim terms, “a logic test module” and “an analog test module” in claims 6 and 11 render the claim indefinite, because it is lack of the written description requirement and the supporting disclosure does not clearly link or associate the disclosed structure, material, or acts to the claimed function of “a logic test module” and “an analog test module” in claims 6 and 11. Examiner notes that no descriptions related to the claim limitation related to the “a logic test module” and “an analog test module” in claims 6 and 11 in the specification clearly link or associate the disclosed structure, material, electrical circuit, or acts to the claimed function of “a logic test module” and “an analog test module” in claims 6 and 11. The disclosure of the structure (or material or acts) linked or associated with “a logic test module” and “an analog test module” in claims 6 and 11 may not be implicit or inherent in the specification because the instant application is not clear to those skilled in the art what structure (material or acts) corresponds to the means- (or step-) plus function claim limitation. (MPEP 2181(II)(A), 2181(II)(C) and 2181(III)).
Claims 7-10 and 12-15 are also rejected by virtue of each dependency on claim 6 or 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SCHAT (US 20200174070 A1, hereinafter referred to as “SCHAT” cited in IDS dated 06/23/2025).
Regarding Claim 1, SCHAT teaches a test method for performing a factory test on an automotive integrated circuit (IC) (Fig. 2; ICs 206-210) (Abstract and paragraph 0019 teaches providing a factory test on an IC), comprising:
performing a logic test on the automotive IC by sending one or more logic test input signals to the automotive IC to generate one or more logic test output signals (Fig. 2; under the broadest reasonable interpretation, at least paragraphs 0019-21 teach providing test signals during the factory testing and outputs for providing test data, where the test signals send logic circuit blocks 212, 222 as well as analog circuit block 246, 250);
while the automotive IC is generating the one or more logic test output signals, utilizing a safety detection circuit (Fig. 1, 142, paragraph 0017 teaches “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”) within the automotive IC to perform a self-test to determine whether at least one analog voltage of an analog circuit block (Fig. 2, an analog circuit block 246, 250, 254) of the automotive IC falls within a predetermined range (expected data) to generate an analog test result (Fig. 2; under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-21 teach providing test signals during the factory testing and outputs for providing test data, where the test signals send logic circuit blocks 212, 222 as well as analog circuit block 246, 250. Further, at least paragraphs 0019-21 teach detecting an error by comparing the test resulting data with the reference (i.e., expected data), “compares received data with expected data. When a mismatch occurs, an error may be detected”); and
determining whether the automotive IC passes the factory test according to at least the logic test output signals and the analog test result (under the broadest reasonable interpretation, at least paragraphs 0017 and 0019 teaches detecting an error by comparing the test resulting data with the reference (i.e., expected data), “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated” and “compares received data with expected data. When a mismatch occurs, an error may be detected”).
Regarding Claim 2, SCHAT teaches wherein the safety detection circuit of the automotive IC comprises an analog-to-digital converter (ADC) (Para 0021, “may include any number or type of analog circuits such as analog-to-digital converter”), and the ADC is configured to convert the at least one analog voltage into a digital code, and the step of determining whether the at least one analog voltage falls within the predetermined range comprises:
utilizing a controller (Fig. 2, controller 214, 224, 234) within the automotive IC to determine whether the digital code falls within the predetermined range to generate the analog test result (Under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-21 teach converting analog values of I/O signals into digital signals (i.e., a digital code) and determine if the error is detected by comparing the test resulting data with the reference (i.e., expected data)).
Regarding Claim 3, SCHAT teaches wherein the safety detection circuit of the automotive IC comprises a comparator (Fig. 1, 142), and the comparator is configured compare the at least one analog voltage of one or more predetermined voltages, and the step of determining whether the at least one analog voltage falls within the predetermined range comprises:
utilizing the comparator to determine whether the at least one analog voltage falls within the predetermined range to generate comparison results (Fig. 1, 142, at least paragraphs 0017 and 0027 teach “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”); and
utilizing a controller (Fig. 2, controller 214, 224, 234) within the automotive IC to generate the analog test result (error indication) based on the comparison result (Under the broadest reasonable interpretation, at least paragraphs 0017 and 0019-21 teach detecting the error by comparing the test resulting data with the reference (i.e., expected data) and generate error indication based on the comparison).
Regarding Claim 4, SCHAT teaches wherein the automotive IC comprises
one or more analog circuit blocks (Fig. 2, 246, 250, and 254) and the one or more analog circuit blocks comprises at least one of a voltage regulator, an oscillator, a driver circuit, an amplifier, a filter, a mixer, a comparator, a signal modulator, a phase-locked loop (PLL), a current mirror, a charge pump, a reference voltage/current generating circuit and/or an analog-to-digital or a digital-to-analog converter (at least paragraph 0021 teaches “Analog circuit blocks 246, 250, and 254 include analog boundary test circuits and may include any number or type of analog circuits such as analog-to-digital converter, digital-to-analog converter, PLL, bias circuit, voltage and/or current reference circuit, current mirror, amplifier, filter, and so on”).
Regarding Claim 5, SCHAT teaches wherein the safety detection circuit is further operated to generate the analog test result during a boot-up process or a normal operation of the automotive IC (Fig. 1, 142, under the broadest reasonable interpretation, at least paragraphs 0019-21 teach providing test signals during the factory testing and outputs for providing test data. And paragraphs 0009 and 0017 teach “While in a factory test mode, external tester 104 may provide a serial data stream by way of the TDI output signal to the first IC 106 of a scan chain formed by the daisy-chained interconnected ICs 106-110. In turn, external tester 104 receives a resulting data stream from the last IC of the scan chain by way of the TDO signal and compares received data with expected data. When a mismatch occurs, an error may be detected” and “When the ET 142 detects a mismatch between the received data stream TDOT and expected data, an error indication is generated”).
Regarding Claim 6, it is a device type claim having similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above. The additional limitation of a testing machine is taught by SCHAT at least at Fig. 2, 204. The additional limitations of a logic test module and an analog test module are taught by taught by SCHAT at least at Fig. 2, tester 204, because, under the broadest reasonable interpretation, structure and features of the tester 204 teach both the logic test module and the analog test module, where external tester 204 includes outputs for providing test signals and receives a resulting data stream from the IC, and compares received data stream with expected data, when a mismatch occurs, an error may be detected (see paragraphs 0017-0021, especially paragraph 0019).
Regarding Claim 7, it is dependent on claim 6 and has similar limitations as of claim 2 above. Therefore, it is rejected under the same rationale as of claim 2 above.
Regarding Claim 8, it is dependent on claim 6 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 9, it is dependent on claim 6 and has similar limitations as of claim 4 above. Therefore, it is rejected under the same rationale as of claim 4 above.
Regarding Claim 10, it is dependent on claim 6 and has similar limitations as of claim 5 above. Therefore, it is rejected under the same rationale as of claim 5 above.
Regarding Claim 11, it is a system type claim and has similar limitations as of claims 1 and 6 above. Therefore, it is rejected under the same rationale as of claims 1 and 6 above.
Regarding Claim 12, it is dependent on claim 11 and has similar limitations as of claim 2 above. Therefore, it is rejected under the same rationale as of claim 2 above.
Regarding Claim 13, it is dependent on claim 11 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 14, it is dependent on claim 11 and has similar limitations as of claim 4 above. Therefore, it is rejected under the same rationale as of claim 4 above.
Regarding Claim 15, it is dependent on claim 11 and has similar limitations as of claim 5 above. Therefore, it is rejected under the same rationale as of claim 5 above.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abhishek et al. (US 10191110 B2) teaches an integrated circuit and a method of self-testing the integrated circuit are provided by: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage.
Shin et al. (US 20230280398 A1) teaches a temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BYUNG RO LEE whose telephone number is (571)272-3707. The examiner can normally be reached on Monday-Friday 8:30am-4:00pm.
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/BYUNG RO LEE/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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