Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter Claim 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , 2, 7 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oda et al. ( US 20090159884 A1 ) hereafter referred to as Oda In regard to claim 1 Oda teaches a display panel [see Fig. 1 “ The present invention relates to a thin-film transistor and a method of manufacturing the same. Further, the present invention relates to a display device including the thin-film transistor ”] , wherein the display panel comprises a substrate [“ insulating substrate 1 ”] and a thin film transistor layer [see Fig. 1 ] disposed on the substrate, and the thin film transistor layer comprises: a gate [“ gate electrode 2 ”] disposed on the substrate; a gate insulating layer [ “ gate insulator 3 according to the first exemplary embodiment of the present invention is formed of a silicon nitride film ” ] disposed on the substrate and covering the gate; an active layer [“ hydrogenated amorphous silicon film 4 ”] disposed on a side of the gate insulating layer away from the gate; wherein the gate insulating layer comprises an electron suppressing layer [“ a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0 ”] at least covering a side of the gate away from the substrate and an electron blocking layer [“ A composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the first region 11 of the gate insulator 3 is set in a range from 1.3 to 1.5 ”] disposed on a side of the electron suppressing layer away from the gate, and a ratio of nitrogen to silicon in the electron suppressing layer is [“ a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0 ”] greater than 0.95. In regard to claim 2 Oda teaches wherein the ratio of nitrogen to silicon in the electron suppressing layer is [see equal to 1, “ a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0 ”] greater than or equal to 1. In regard to claim 7 Oda teaches wherein a material of the gate insulating layer [“gate insulator 3 according to the first exemplary embodiment of the present invention is formed of a silicon nitride film”] comprises silicon nitride material. Claim(s) 8 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oda et al. ( US 20090159884 A1 ) hereafter referred to as Oda In regard to claim 8 Oda teaches a method of manufacturing [see Fig. 1 “The present invention relates to a thin-film transistor and a method of manufacturing the same. Further, the present invention relates to a display device including the thin-film transistor” “ Next, a description is given of a method of manufacturing the TFT 50 having the above-mentioned structure, with reference to FIG. 6 ” ] a display panel, comprising: forming a gate [“ As the insulating substrate 1, a substrate with permeability, such as a glass substrate or a quartz substrate, is used. The gate electrode 2 is formed on the insulating substrate 1 ”] on a substrate; forming an electron suppressing layer [“ The gate insulator 3 is formed on the gate electrode 2 to cover the gate electrode 2 ” “ The gate insulator 3 according to the first exemplary embodiment of the present invention is formed of a silicon nitride film. Note that the silicon nitride film is divided into two regions in a film thickness direction, and the two regions are formed of silicon nitride films having different compositions ” “ a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0 ” “ The second region 12 of the gate insulator 3 is deposited with a film thickness ...” “ As described above, the first region 11 and the second region 12 are sequentially deposited without opening to the atmosphere ” “ The first region 11 is deposited with a film thickness in a range ...” ] at least on a side of the gate away from the substrate, and a ratio of nitrogen to silicon in the electron suppressing layer is [“ a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0 ”] greater than 0.95; forming an electron blocking layer [“ A composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the first region 11 of the gate insulator 3 is set in a range from 1.3 to 1.5 ”] on a side of the electron suppressing layer away from the gate to form a gate insulating layer; forming an active layer [“ The hydrogenated amorphous silicon film 4 is formed immediately above the gate insulator 3 ”] on a side of the electron blocking layer away from the electron suppressing layer. Claim(s) 1 4 , 15 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oda et al. ( US 20090159884 A1 ) hereafter referred to as Oda In regard to claim 1 4 Oda teaches a display device [see Fig. 1 “The present invention relates to a thin-film transistor and a method of manufacturing the same. Further, the present invention relates to a display device including the thin-film transistor”] , wherein the display device comprises a display panel, the display panel comprises a substrate [“insulating substrate 1”] and a thin film transistor layer [see Fig. 1] disposed on the substrate, and the thin film transistor layer comprises: a gate [“gate electrode 2”] disposed on the substrate; a gate insulating layer [“gate insulator 3 according to the first exemplary embodiment of the present invention is formed of a silicon nitride film”] disposed on the substrate and covering the gate; an active layer [“hydrogenated amorphous silicon film 4”] disposed on a side of the gate insulating layer away from the gate; wherein the gate insulating layer comprises an electron suppressing layer [“a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0”] at least covering a side of the gate away from the substrate and an electron blocking layer [“A composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the first region 11 of the gate insulator 3 is set in a range from 1.3 to 1.5”] disposed on a side of the electron suppressing layer away from the gate, and a ratio of nitrogen to silicon in the [“a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0”] electron suppressing layer is greater than 0.95. In regard to claim 15 Oda teaches wherein the ratio of nitrogen to silicon in the electron suppressing layer is greater than or [ see equal to 1, “a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0”] equal to 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim (s) 3 -6, 10 , 12, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda in view of Dellas et al. ( US 9741557 B1 ) hereafter referred to as Dellas . Czarnacka et al. (see PTO-892, "AC measurements and dielectric properties of nitrogen-rich silicon nitride thin films," ), and Sahu et al. ( see PTO-892, “ Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films ”) are provided as evidence. In regard to claim 3 Oda teaches the ratio of nitrogen to silicon in the electron suppressing layer is less than [see claim 1 “a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0” “A composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the first region 11 of the gate insulator 3 is set in a range from 1.3 to 1.5” ] a ratio of nitrogen to silicon in the electron blocking layer but does not teach wherein the gate insulating layer further comprises a spacer layer disposed between the electron suppressing layer and the electron blocking layer, and a ratio of nitrogen to silicon in the spacer layer is less than the ratio of nitrogen to silicon in the electron suppressing layer. See Dellas teaches see “ FIG. 2A through FIG. 2E are cross sections of the semiconductor device of FIG. 1, depicting stages of an exemplary method of formation ” “ Other semiconductor materials, such as other group III-V semiconductors, group II-VI semiconductors or possibly Group IV semiconductors, are within the scope of the instant example ” “ the gate dielectric layer 110 includes a nitrogen-rich layer of silicon nitride 120, herein after referred to as the N-rich layer 120 disposed immediately over the substrate 102 in the area over the channel 114. A silicon-to-nitrogen atomic ratio of a silicon nitride layer may be characterized by an index of refraction. The index of refraction may be measured at a wavelength of 630 nanometers to 635 nanometers. Stoichiometric silicon nitride may have a silicon-to-nitrogen atomic ratio of about, 0.75, for example within a margin of less than 1 percent. The N-rich layer 120 may have an index of refraction that is 0.015 to 0.030 less than an index of refraction of stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional silicon rich layer of silicon nitride 122, hereinafter referred to as the Si-rich layer 122, disposed over the N-rich layer 120. The Si-rich layer 122 may have an index of refraction that is 0.025 to 0.040 more than the index of refraction of the stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional threshold adjust dielectric layer 124 disposed over the N-rich layer 120 and over the Si-rich layer 122 if present, to provide a desired threshold potential for the FET 106. The threshold adjust dielectric layer 124 may include stoichiometric silicon nitride ”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Oda to include a stoichiometric silicon nitride layer between “ second region 12 ” and the gate, such that “ second region 12 ” is the “ spacer layer ” i.e. to modify Oda to include wherein the gate insulating layer further comprises a spacer layer disposed between the electron suppressing layer and the electron blocking layer, and a ratio of nitrogen to silicon in the spacer layer is less than the ratio of nitrogen to silicon in the electron suppressing layer, and the ratio of nitrogen to silicon in the electron suppressing layer is less than a ratio of nitrogen to silicon in the electron blocking layer. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is better threshold adjust ment. In regard to claim 4 Oda and Dellas as combined does not specifically teach wherein a thickness of the electron suppressing layer is less than a thickness of the spacer layer, and the thickness of the electron suppressing layer is greater than or equal to a thickness of the electron blocking layer. However the roles of the three layers are different namely threshold adjustment, electron blocking and an intermediate spacer, thus the choice is based on energy of electrons in the chann e l, and amount of threshold adjustment desired. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “ wherein a thickness of the electron suppressing layer is less than a thickness of the spacer layer, and the thickness of the electron suppressing layer is greater than or equal to a thickness of the electron blocking layer ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 5 Oda and Dellas as combined does not specifically teach wherein an optical band gap of the electron suppressing layer is greater than an optical band gap of the spacer layer, and is less than an optical band gap of the electron blocking layer. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “ wherein an optical band gap of the electron suppressing layer is greater than an optical band gap of the spacer layer, and is less than an optical band gap of the electron blocking layer ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 6 Oda and Dellas as combined does not specifically teach wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.3. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “ wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.3 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 10 Oda and Dellas as combined does not specifically teach wherein the optical band gap of the electron suppressing layer is greater than or equal to 4.3. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “ wherein the optical band gap of the electron suppressing layer is greater than or equal to 4.3 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 1 2 Oda and Dellas as combined does not specifically teach wherein the ratio of nitrogen to silicon in the spacer layer is less than or equal to 0.95 and greater than or equal to 0.8, and an optical band gap of the spacer layer is 4. However see combination, see that “second region 12” is the “spacer layer” , see Oda “a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0” , see that the stoichiometry affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “ wherein the ratio of nitrogen to silicon in the spacer layer is less than or equal to 0.95 and greater than or equal to 0.8, and an optical band gap of the spacer layer is 4 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 1 3 Oda and Dellas as combined does not specifically teach wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.7. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.7”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 Claim (s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda in view of Dellas et al. ( US 9741557 B1 ) hereafter referred to as Dellas . In regard to claim 9 Oda does not teach wherein forming an electron suppressing layer at least on a side of the gate away from the substrate further comprises: depositing a spacer layer on the side of the electron suppressing layer away from the gate, and the ratio of nitrogen to silicon in the electron suppressing layer is greater than a ratio of nitrogen to silicon in the spacer layer; wherein the electron suppressing layer is at least deposited on the side of the gate away from the substrate, and a deposition rate of the electron suppressing layer is lower than a deposition rate of the spacer layer. See Dellas teaches see “ FIG. 2A through FIG. 2E are cross sections of the semiconductor device of FIG. 1, depicting stages of an exemplary method of formation ” “ Other semiconductor materials, such as other group III-V semiconductors, group II-VI semiconductors or possibly Group IV semiconductors, are within the scope of the instant example ” “ the gate dielectric layer 110 includes a nitrogen-rich layer of silicon nitride 120, herein after referred to as the N-rich layer 120 disposed immediately over the substrate 102 in the area over the channel 114. A silicon-to-nitrogen atomic ratio of a silicon nitride layer may be characterized by an index of refraction. The index of refraction may be measured at a wavelength of 630 nanometers to 635 nanometers. Stoichiometric silicon nitride may have a silicon-to-nitrogen atomic ratio of about, 0.75, for example within a margin of less than 1 percent. The N-rich layer 120 may have an index of refraction that is 0.015 to 0.030 less than an index of refraction of stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional silicon rich layer of silicon nitride 122, hereinafter referred to as the Si-rich layer 122, disposed over the N-rich layer 120. The Si-rich layer 122 may have an index of refraction that is 0.025 to 0.040 more than the index of refraction of the stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional threshold adjust dielectric layer 124 disposed over the N-rich layer 120 and over the Si-rich layer 122 if present, to provide a desired threshold potential for the FET 106. The threshold adjust dielectric layer 124 may include stoichiometric silicon nitride ” , see adjustment of pressure and flow rates “ Dichlorosilane is flowed into the first LPCVD chamber 126 at a flow rate of 10 standard cubic centimeters per minute (sccm) to 80 sccm ” “ Ammonia is flowed into the first LPCVD chamber 126 at a flow rate of 6 to 12 times the flow rate of the dichlorosilane ” “ Dichlorosilane is flowed into the second LPCVD chamber 132 at a flow rate of 40 sccm to 100 sccm ” “ Ammonia is flowed into the second LPCVD chamber 132 at a flow rate of 3 to 6 times the flow rate of the dichlorosilane ” “ Dichlorosilane is flowed into the third LPCVD chamber 138 at a flow rate of 30 sccm to 120 sccm ” “ Ammonia is flowed into the third LPCVD chamber 138 at a flow rate of 8 to 12 times the flow rate of the dichlorosilane ” , see the temperatures used during deposition. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Oda to include a stoichiometric silicon nitride layer between “ second region 12 ” and the gate, such that “ second region 12 ” is the “spacer layer” i.e. to modify Oda to include wherein forming an electron suppressing layer at least on a side of the gate away from the substrate further comprises: depositing a spacer layer on the side of the electron suppressing layer away from the gate, and the ratio of nitrogen to silicon in the electron suppressing layer is greater than a ratio of nitrogen to silicon in the spacer layer; wherein the electron suppressing layer is at least deposited on the side of the gate away from the substrate, and a deposition rate of the electron suppressing layer is lower than a deposition rate of the spacer layer. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is better threshold adjust ment and that the deposition rate is based on the flow rates , pressures and temperatures. Claim (s) 1 6 -20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda in view of Dellas et al. ( US 9741557 B1 ) hereafter referred to as Dellas . Czarnacka et al. (see PTO-892, "AC measurements and dielectric properties of nitrogen-rich silicon nitride thin films," ), and Sahu et al. (see PTO-892, “ Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films ”) are provided as evidence. In regard to claim 16 Oda teaches the ratio of nitrogen to silicon in the electron suppressing layer is less than [see claim 1 4 “a composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the second region 12 of the gate insulator 3 is preferably set to be equal to or less than 1.0” “A composition ratio between nitrogen and silicon (N/Si) of the silicon nitride which forms the first region 11 of the gate insulator 3 is set in a range from 1.3 to 1.5”] a ratio of nitrogen to silicon in the electron blocking layer but does not teach wherein the gate insulating layer further comprises a spacer layer disposed between the electron suppressing layer and the electron blocking layer, and a ratio of nitrogen to silicon in the spacer layer is less than the ratio of nitrogen to silicon in the electron suppressing layer. See Dellas teaches see “ FIG. 2A through FIG. 2E are cross sections of the semiconductor device of FIG. 1, depicting stages of an exemplary method of formation ” “ Other semiconductor materials, such as other group III-V semiconductors, group II-VI semiconductors or possibly Group IV semiconductors, are within the scope of the instant example ” “ the gate dielectric layer 110 includes a nitrogen-rich layer of silicon nitride 120, herein after referred to as the N-rich layer 120 disposed immediately over the substrate 102 in the area over the channel 114. A silicon-to-nitrogen atomic ratio of a silicon nitride layer may be characterized by an index of refraction. The index of refraction may be measured at a wavelength of 630 nanometers to 635 nanometers. Stoichiometric silicon nitride may have a silicon-to-nitrogen atomic ratio of about, 0.75, for example within a margin of less than 1 percent. The N-rich layer 120 may have an index of refraction that is 0.015 to 0.030 less than an index of refraction of stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional silicon rich layer of silicon nitride 122, hereinafter referred to as the Si-rich layer 122, disposed over the N-rich layer 120. The Si-rich layer 122 may have an index of refraction that is 0.025 to 0.040 more than the index of refraction of the stoichiometric silicon nitride material ” “ gate dielectric layer 110 may further include an optional threshold adjust dielectric layer 124 disposed over the N-rich layer 120 and over the Si-rich layer 122 if present, to provide a desired threshold potential for the FET 106. The threshold adjust dielectric layer 124 may include stoichiometric silicon nitride ”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Oda to include a stoichiometric silicon nitride layer between “ second region 12 ” and the gate, such that “ second region 12 ” is the “spacer layer” i.e. to modify Oda to include wherein the gate insulating layer further comprises a spacer layer disposed between the electron suppressing layer and the electron blocking layer, and a ratio of nitrogen to silicon in the spacer layer is less than the ratio of nitrogen to silicon in the electron suppressing layer, and the ratio of nitrogen to silicon in the electron suppressing layer is less than a ratio of nitrogen to silicon in the electron blocking layer. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is better threshold adjust ment. In regard to claim 17 Oda and Dellas as combined does not specifically teach wherein a thickness of the electron suppressing layer is less than a thickness of the spacer layer, and the thickness of the electron suppressing layer is greater than or equal to a thickness of the electron blocking layer. However the roles of the three layers are different namely threshold adjustment, electron blocking and an intermediate spacer, thus the choice is based on energy of electrons in the channel, and amount of threshold adjustment desired. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a thickness of the electron suppressing layer is less than a thickness of the spacer layer, and the thickness of the electron suppressing layer is greater than or equal to a thickness of the electron blocking layer”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 18 Oda and Dellas as combined does not specifically teach wherein an optical band gap of the electron suppressing layer is greater than an optical band gap of the spacer layer, and is less than an optical band gap of the electron blocking layer. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein an optical band gap of the electron suppressing layer is greater than an optical band gap of the spacer layer, and is less than an optical band gap of the electron blocking layer”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 19 Oda and Dellas as combined does not specifically teach wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.3. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein an optical band gap of the electron suppressing layer is greater than or equal to 4.3”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 In regard to claim 20 Oda and Dellas as combined does not specifically teach wherein the optical band gap of the electron suppressing layer is greater than or equal to 4.3. However see that the three layers in question are all silicon nitride and the difference is the stoichiometry which affects the band gap, see Czarnacka et al. and Sahu et al. are provided as evidence of photoluminescence behavior in SiN. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the optical band gap of the electron suppressing layer is greater than or equal to 4.3”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SITARAMARAO S YECHURI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8764 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8:00-4:30 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Britt D Hanley can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-3042 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893