DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsuch et al., US 2022/0098290 (corresponding to US 11,343,272).
In re Claim 1, Hsuch discloses a method for forming a metal interconnection structure of a semiconductor device, comprising: providing a substrate 202; forming a first dielectric layer 208 on the substrate 202; forming a first conductive structure 210 in the first dielectric layer 208; etching back part of the first conductive structure 210; forming an etch stop layer 220 on the first conductive structure 210; forming a second dielectric layer 222 on the etch stop layer 220 and performing chemical mechanical polishing ([0020]); and forming a second conductive structure (226, 228) in the second dielectric layer 222, wherein the second conductive structure (226, 228) is electrically connected to the first conductive structure 210 (Fig. 1-15; [0014 – 0040]).
In re Claim 2, Hsuch discloses the method according to claim 1, wherein the forming a first conductive structure 210 in the first dielectric layer 208 comprises: etching a trench (wherein 210 is formed) in the first dielectric layer 208; forming a first diffusion barrier layer 212 in the trench (wherein 210 is formed); and filling the trench (wherein 210 is formed) with a metal 210 ([0020]) (Fig. 2; [0014 -0018]).
In re Claim 3, Hsuch discloses the method according to claim 1, wherein the forming a second conductive structure (226, 228) (Fig. 8) in the second dielectric layer 222 comprises: forming a through hole 224 in the second dielectric layer 208 by using a single damascene etching process ([0026]); forming a second diffusion barrier layer 230 on a surface of the through hole 224; and filling the through hole 224 with a metal material 226 ([0020- 0030]).
In re Claim 4, Hsuch discloses the method according to claim 1, the forming a second conductive structure (226, 228) in the second dielectric layer 222 comprises: forming a trench (wherein 228 is formed) and a through hole 226-1 corresponding to the trench (wherein 228 is formed) in the second dielectric layer 222 by using a double damascene etching process; forming a second diffusion barrier layer 230 on a surface of the trench (wherein 228 is formed) and a surface of the through hole 224; and filling the trench (wherein 228 is formed) and the through hole 224 with a metal material (Fig. 8; [0030]).
In re Claim 5, Hsuch discloses the method according to claim 3, wherein the metal material is any one of W, Co, Cu, Ru, or Al ([0028]).
In re Claim 6, Hsuch discloses the method according to claim 4, wherein the metal material is any one of W, Co, Cu, Ru, or Al ([0028]).
In re Claim 8, Hsuch discloses the method according to claim 1, wherein a material of the etch stop layer 206 is one of SiNx or NSiC ([0018]; [0023]).
Claims 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., US 2019/0214296 (corresponding to US 11,011,413).
In re Claim 9, Wang discloses a metal interconnection structure of a semiconductor device (Fig. 10), comprising: a substrate 20; a first dielectric layer 22 on the substrate 20; a first conductive structure 24 in the first dielectric layer 22, wherein a (lower) surface of the first conductive structure 24 is lower than a (upper) surface of the first dielectric layer 22; an etch stop layer 26 on the first conductive structure 24 and the first dielectric layer 22; a second dielectric layer 28 on the etch stop layer 26; and a second conductive structure 60 in the second dielectric layer 28, wherein the second conductive structure 60 is electrically connected to the first conductive structure 24 (Figs. 1-10; [0016 – 0061]).
In re Claim 10, Wang discloses the metal interconnection structure of the semiconductor device according to claim 9, wherein the second conductive structure 60 is a metal through hole or a combination of a metal through hole and a metal interconnection line (Figs. 5 and 10; [0040-0042].
In re Claim 11, Wang discloses the metal interconnection structure of the semiconductor device according to claim 9, wherein the first conductive structure 24 comprises a metal layer formed in the first dielectric layer 22 and a first diffusion barrier layer between the metal layer 24 and the first dielectric layer 22 ([0014], [0020]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hsuch as applied to claim 1 above.
In re Claim 7, Hsu discloses all limitations of Claim 7 including that the first dielectric layer 208 is made of a low-k material ([0019]), except for that and the second dielectric layer 222 is made of a low-k material. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use for the second dielectric layer also a low-k material since simplifies the production.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893