Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5-8, 11, 14, 17, 19, and 20 is rejected under 35 U.S.C 103 as being unpatentable over Hu et al. (US 20180364785 A1, hereinafter Hu) in view of Buchanan (US20170220526A1, hereinafter Buchanan-1).
Regarding Claim 1
Hu teaches:
A method of training a pattern recognition system, the method comprising:
Hu [0038] “As mentioned above, in one example, crossbar array 302 may include a comparator 380 to determine whether a particular pattern is detected in the output vector at vector output register 314. For instance, it may desired to have a first of the output analog voltage signals in the output vector to be high, e.g., above a certain threshold for an analog voltage signal, when a particular pattern is detected. The particular pattern may vary depending upon the particular application and the programming of the crossbar array 302. For example, the pattern may be indicative of such things as: a person slipping and falling, a hazardous environmental condition, a hazardous condition in a lab, a manufacturing facility, a power plant, and so forth. In general, a set of training data may be utilized where, based upon an input vector that is indicative of an event or condition (such as a person falling down) a predicted output vector should result.”
Examiner’s Note (EN): this paragraph denotes a method pattern training
inputting a voltage based on a pattern to a first set of rows in a memristor crossbar;
Hu [0041] “In block 410, the crossbar array may receive an input vector of a first set of analog voltage signals.”
EN: analog voltage signal reads on “pattern”
grounding a first column of a column pair of memristors from the crossbar via a resistor; and
Hu [0032] The crossbar array 302 may further include a vector input register 310 for applying an input vector comprising a first set of analog voltage signals to the row electrodes 304 and a vector output register 314 for receiving an output vector (e.g., a second set of analog voltage signals), resulting from current flows in the column electrodes 306. In one example, the sense circuits 316 are to convert an electrical current in a column electrode 306 to one of the second set of analog voltage signals in the output vector. For instance, the sense circuits 316 may each include an operational amplifier 318 and a resistor 320, which can be arranged to represent a virtual ground for read operations.
Hu [0034] For example, all unselected row electrodes 304 and column electrodes 306 may be floated (or alternatively, grounded). Other schemes may involve grounding unselected column electrodes 306 or grounding portions of unselected column electrodes 306.
EN: this passage denotes using a resistor to ground a selected column
applying a first … voltage to a second column of the column pair, a second … voltage to remaining columns, and a third … voltage to a second set of rows different from the first set of rows.
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
However, Hu does not teach:
scaled voltage
Buchanan-1 teaches:
scaled voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on the scaling of the input voltages for rows and columns
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with method of applying scaled voltage from Buchanan-1 in order to prevent state shifts of the memristor and decrease noise-to-signal ratio.
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
Regarding Claim 5
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu teaches:
applying the second … voltage to the remaining columns comprising: applying … voltage to the remaining columns.
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
Hu does not distinctly disclose:
scaled voltage … comprising: applying three-fourths of the voltage
However, Buchanan-1 teaches:
scaled voltage … comprising: applying three-fourths of the voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on that different scaled voltages can be applied to different columns and rows of the crossbar as long its less than the maximum possible voltage
At the time the invention was made, it would have been an obvious matter of design choice to a person of ordinary skill in the art to scale the voltage input to ¾ because Applicant has not disclosed that ¾ voltage provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Buchanan-1’s method and the applicant’s method to perform equally well with either the scaling down of voltage taught by Buchanan-1 or the claimed application of three-fourths of the voltage because both scaling methods are equally capable of reducing the voltage. Accordingly, it would have been obvious one of ordinary skill in the art at the effective filing date of the claimed invention to modify Buchanan-1 to obtain the invention as specified in claim 5 because such a modification would have been considered a mere design consideration which fails to patentably distinguish over the prior art of Buchanan-1.
Regarding Claim 6
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu teaches
applying the third … voltage to the second set of rows comprising: applying … voltage to the second set of rows.
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
Hu does not distinctly disclose:
scaled voltage … comprising: … one-half of the voltage
However, Buchanan-1 teaches:
scaled voltage … comprising: applying one-half of the voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on that different scaled voltages can be applied to different columns and rows of the crossbar as long its less than the maximum possible voltage
½ of the voltage can be applied to the remaining columns because it is a voltage drop.
At the time the invention was made, it would have been an obvious matter of design choice to a person of ordinary skill in the art to scale the voltage input to ½ because Applicant has not disclosed that ½ voltage provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Buchanan-1’s method and the applicant’s method to perform equally well with either the scaling down of voltage taught by Buchanan-1 or the claimed application of ½ of the voltage because both scaling methods are equally capable of reducing the voltage. Accordingly, it would have been obvious one of ordinary skill in the art at the effective filing date of the claimed invention to modify Buchanan-1 to obtain the invention as specified in claim 5 because such a modification would have been considered a mere design consideration which fails to patentably distinguish over the prior art of Buchanan-1.
Regarding Claim 7
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu further teaches:
training the pattern recognition system to recognize a second pattern on a second column pair.
Hu [0026] Programming unit 170 may then utilize the feedback information to train the matrix that models the neural network for improved accuracy.
[0029] However, it should be noted that a device of the present disclosure may also include multiple DPEs to detect different patterns. [0038] In general, a set of training data may be utilized where, based upon an input vector that is indicative of an event or condition (such as a person falling down) a predicted output vector should result. In one example, the conductance matrix G of the crossbar array 302 is programmed such that the predicted output vector may include a first analog voltage signal being high when the pattern is detected.;
[00011] In examples of the present disclosure, a memristor-based crossbar array, also referred to herein as a dot product engine (DPE), is utilized as a pre-processor for sensor data that is input to a processor. The processor may comprise a digital processor, such as a CPU, a microprocessor embedded in a sensor device, and so forth. In one example, the crossbar array comprises a passive analog processor that functions as an efficient neural network to recognize patterns in analog sensor data.
[0023] In various examples, detecting patterns of human activity (as well as other pattern matching applications) may involve processing sensor data from sensor(s) 110 over successive time periods.
[0024] The output of the DPE 130 may comprise an output vector of a second set of analog voltage signals that is derived from a vector dot product multiplication of the input vector of the first set of analog voltage signals (from sensor(s) 110 and/or analog buffer(s) 120) with a matrix comprising the resistance (or conductance) values of the memristors of the DPE 130. In one example, all or a portion of the second set of analog voltage signals in the output vector may be used for pattern matching/pattern detection.
EN: this paragraph denotes the detection of more than one pattern using a second set of analog voltage signals which reads on second column pair
Regarding Claim 8
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu further teaches:
the memristor crossbar comprising memristors of different resistances.
Hu [0032] “For example, a driver for a selected row electrode 304 can drive the selected row electrode 304 with different voltages for performing a vector-matrix multiplication or with voltages for setting resistance values of the memristors 308 of the crossbar array 302.”
Regarding Claim 11
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu teaches:
A pattern recognition system comprising: a memristor crossbar comprising a plurality of columns and a plurality of rows
Hu [0008] “In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.”
[0018] “an input analog voltage signal from each row of the crossbar array may be weighted by the conductance of the memristors in each column and accumulated as the current output from each column.;”
EN: this paragraph denotes a system that detects a pattern which reads on “pattern recognition system”
a first column and a second column of the plurality of columns forming a column pair
Hu [0033-34] “In one example, values in an N×M matrix are mapped to the memristors 308 in the crossbar array 302. For instance, a programming operation may be performed on the crossbar array 302 where one memristor 308 at a time is programmed. In one example, the matrix comprises a linear transform that may be determined by a programming unit to model a neural network for pattern detection. The values of the matrix may then be converted to programming signals, where a third set of analog voltage signals may be generated from the programming signals to program the respective memristors 308 to selected resistance (or conductance) values. The programming signals may be determined by the programming unit, or the matrix values may be provided to the processor 390 and mapped to the programming signals by the processor 390. In one example, the programming signals may be converted to the third set of analog voltage signals via one or more digital-to-analog converters (not shown), which may be components of the processor 390, or which may be deployed between the processor 390 and the crossbar array 302. In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302.”
EN: column pair reads on 2 columns next to each other
the column pair being trained to recognize a pattern by:
Hu [0026] Programming unit 170 may then utilize the feedback information to train the matrix that models the neural network for improved accuracy.
[0029] However, it should be noted that a device of the present disclosure may also include multiple DPEs to detect different patterns. [0038] In general, a set of training data may be utilized where, based upon an input vector that is indicative of an event or condition (such as a person falling down) a predicted output vector should result. In one example, the conductance matrix G of the crossbar array 302 is programmed such that the predicted output vector may include a first analog voltage signal being high when the pattern is detected.;
[00011] In examples of the present disclosure, a memristor-based crossbar array, also referred to herein as a dot product engine (DPE), is utilized as a pre-processor for sensor data that is input to a processor. The processor may comprise a digital processor, such as a CPU, a microprocessor embedded in a sensor device, and so forth. In one example, the crossbar array comprises a passive analog processor that functions as an efficient neural network to recognize patterns in analog sensor data.
[0023] “In various examples, detecting patterns of human activity (as well as other pattern matching applications) may involve processing sensor data from sensor(s) 110 over successive time periods.”
[0024] “The output of the DPE 130 may comprise an output vector of a second set of analog voltage signals that is derived from a vector dot product multiplication of the input vector of the first set of analog voltage signals (from sensor(s) 110 and/or analog buffer(s) 120) with a matrix comprising the resistance (or conductance) values of the memristors of the DPE 130. In one example, all or a portion of the second set of analog voltage signals in the output vector may be used for pattern matching/pattern detection.”
EN: this paragraph reads on using some of the memristors of the DPE (crossbar array) to detect a pattern which reads on using a column pair
inputting a voltage based on the pattern to a first set of rows of the plurality of rows,
Hu [0041] “In block 410, the crossbar array may receive an input vector of a first set of analog voltage signals.”
EN: analog voltage signal reads on “pattern”
the first column being grounded via a resistor; and
Hu [0032] “The crossbar array 302 may further include a vector input register 310 for applying an input vector comprising a first set of analog voltage signals to the row electrodes 304 and a vector output register 314 for receiving an output vector (e.g., a second set of analog voltage signals), resulting from current flows in the column electrodes 306. In one example, the sense circuits 316 are to convert an electrical current in a column electrode 306 to one of the second set of analog voltage signals in the output vector. For instance, the sense circuits 316 may each include an operational amplifier 318 and a resistor 320, which can be arranged to represent a virtual ground for read operations.”
Hu [0034] “For example, all unselected row electrodes 304 and column electrodes 306 may be floated (or alternatively, grounded). Other schemes may involve grounding unselected column electrodes 306 or grounding portions of unselected column electrodes 306.”
EN: this passage denotes using a resistor to ground a selected column
applying a first … voltage to the second column, a second … voltage to remaining columns, and a third … voltage to a second set of rows of the plurality of columns and different from the first set of rows.
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
However, Hu does not teach:
scaled voltage
Buchanan-1 teaches:
scaled voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on the scaling of the input voltages for rows and columns
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with method of applying scaled voltage from Buchanan-1 in order to prevent state shifts of the memristor and decrease noise-to-signal ratio.
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
Regarding Claim 14
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 11 as cited above and Hu further teaches:
further comprising additional column pairs trained to recognize corresponding additional patterns.
Hu [0029] However, it should be noted that a device of the present disclosure may also include multiple DPEs to detect different patterns.
[00011] In examples of the present disclosure, a memristor-based crossbar array, also referred to herein as a dot product engine (DPE)”
Regarding Claim 17
Claim 17 recites substantially similar limitations for claim 8 and is therefore rejected on the same basis.
Regarding Claim 19
Hu teaches:
A hardware based neural network comprising:
Hu [0013] “…crossbar array includes memristors functioning as resistors within an operational range and which are utilized as a linear transform representing a neural network. For instance, a crossbar array may be used to perform a vector matrix multiplication on an input vector of analog voltage signals to generate an output vector of analog voltage signals.”
one or more neural network layers formed by a plurality of memristors as network weights organized in a memristor crossbar having a plurality of columns and a plurality of rows, the neural network being trained to adjust one or more network weights to recognize a pattern, the training comprising:
Hu [0041] “In one example, the resistances (or conductances) of the memristors may have been programmed for the crossbar array to function as a linear transform representing a neural network for detecting a pattern in the sensor data. The pattern may be indicative of a particular condition or event, or a set of conditions or events.”
EN: crossbar array reads on multiple rows and columns of memristors; this paragraph reads on using resistance values of memristors to detect a pattern and use for training a neural network; changing the resistances reads on changing the weights as cited above
inputting a voltage based on a pattern to a first set of rows of the memristor crossbar;
Hu [0041] “In block 410, the crossbar array may receive an input vector of a first set of analog voltage signals.”
EN: analog voltage signal reads on “pattern”
grounding a first column of a column pair via a resistor; and
Hu [0032] The crossbar array 302 may further include a vector input register 310 for applying an input vector comprising a first set of analog voltage signals to the row electrodes 304 and a vector output register 314 for receiving an output vector (e.g., a second set of analog voltage signals), resulting from current flows in the column electrodes 306. In one example, the sense circuits 316 are to convert an electrical current in a column electrode 306 to one of the second set of analog voltage signals in the output vector. For instance, the sense circuits 316 may each include an operational amplifier 318 and a resistor 320, which can be arranged to represent a virtual ground for read operations.
Hu [0034] For example, all unselected row electrodes 304 and column electrodes 306 may be floated (or alternatively, grounded). Other schemes may involve grounding unselected column electrodes 306 or grounding portions of unselected column electrodes 306.
EN: this passage denotes using a resistor to ground a column pair; column pair reads on 2 columns near each other in a crossbar array to PHOSTIA
applying a first … voltage to a second column of the column pair, a second … voltage to remaining columns, and a third … voltage value to a second set of rows different from the first set of rows,\
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
such that the first voltage, the first … voltage, the second … voltage, and the third … voltage adjust network weights corresponding to memristor states of the column pair.
Hu [0041] “In one example, the resistances (or conductances) of the memristors may have been programmed for the crossbar array to function as a linear transform representing a neural network for detecting a pattern in the sensor data. The pattern may be indicative of a particular condition or event, or a set of conditions or events.”
EN: this paragraph reads on using resistance values of memristors to detect a pattern and use for training a neural network; changing the resistances reads on changing the weights as cited above
However, Hu does not distinctly teach:
scaled voltage
Buchanan-1 teaches:
scaled voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on the scaling of the input voltages for rows and columns
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with method of applying scaled voltage from Buchanan-1 in order to prevent state shifts of the memristor and decrease noise-to-signal ratio.
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
Regarding Claim 20
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 19 as cited above and Hu further teaches:
the neural network being trained to recognize more patterns by adjusting network weights corresponding to memristors of more column pairs of the memristor crossbar.
Hu [0038] “As mentioned above, in one example, crossbar array 302 may include a comparator 380 to determine whether a particular pattern is detected in the output vector at vector output register 314. For instance, it may desired to have a first of the output analog voltage signals in the output vector to be high, e.g., above a certain threshold for an analog voltage signal, when a particular pattern is detected. The particular pattern may vary depending upon the particular application and the programming of the crossbar array 302. For example, the pattern may be indicative of such things as: a person slipping and falling, a hazardous environmental condition, a hazardous condition in a lab, a manufacturing facility, a power plant, and so forth. In general, a set of training data may be utilized where, based upon an input vector that is indicative of an event or condition (such as a person falling down) a predicted output vector should result.”
EN: this paragraph denotes a method pattern training
[0026] “Programming unit 170 may then utilize the feedback information to train the matrix that models the neural network for improved accuracy.”
[0029] “However, it should be noted that a device of the present disclosure may also include multiple DPEs to detect different patterns. [0038] In general, a set of training data may be utilized where, based upon an input vector that is indicative of an event or condition (such as a person falling down) a predicted output vector should result. In one example, the conductance matrix G of the crossbar array 302 is programmed such that the predicted output vector may include a first analog voltage signal being high when the pattern is detected.;”
[00011] “In examples of the present disclosure, a memristor-based crossbar array, also referred to herein as a dot product engine (DPE), is utilized as a pre-processor for sensor data that is input to a processor. The processor may comprise a digital processor, such as a CPU, a microprocessor embedded in a sensor device, and so forth. In one example, the crossbar array comprises a passive analog processor that functions as an efficient neural network to recognize patterns in analog sensor data.”
[0023] “In various examples, detecting patterns of human activity (as well as other pattern matching applications) may involve processing sensor data from sensor(s) 110 over successive time periods.”
[0024] “The output of the DPE 130 may comprise an output vector of a second set of analog voltage signals that is derived from a vector dot product multiplication of the input vector of the first set of analog voltage signals (from sensor(s) 110 and/or analog buffer(s) 120) with a matrix comprising the resistance (or conductance) values of the memristors of the DPE 130. In one example, all or a portion of the second set of analog voltage signals in the output vector may be used for pattern matching/pattern detection.”
EN: this paragraph denotes the detection of more than one pattern using a second set of analog voltage signals which reads on second column pair
Claim 2, 3, 10, 12, and 13 is rejected under 35 U.S.C 103 as being unpatentable over Hu in view of Buchanan-1 in further view of Buchanan et al. (US20180253643A1, hereinafter Buchanan-2)
Regarding Claim 2
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and further teaches:
the inputting of the voltage causing memristors in the first column to change resistances according to the pattern, and
Hu [0012] For example, one or more sensors may generate analog sensor data, e.g., analog voltage signals, that are fed to a crossbar array as an input vector. In one example, the analog sensor data is sampled by analog buffers to collect sensor data over a period of time, or from several time intervals. The crossbar array may function as a neural network for pre-processing the input vector to generate an output vector of analog voltage signals. For instance, resistance values of the memristors of the crossbar array may be programmed to represent a matrix, where the matrix may represent a linear transfer function of a neural network. A resistance value of a memristor may also be referred to as a memristance.
EN: this paragraph reads on resistances of memristors changing to match a pattern
the applying of the first scaled voltage causing memristors in the second column to change resistances according to the negative of the pattern.
the applying of the first … voltage causing memristors in the second column to change resistances
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
However, Hu does not distinctly disclose:
the applying of … scaled voltage … to change resistances according to the negative of the pattern.
Buchanan-1 teaches:
scaled voltage
Buchanan-1 [0016] “Using the single read signal value to perform a MAC operation may allow for flexibility in selecting a read signal to 1) increase the signal-to-noise ratio to result in a more deterministic MAC result and 2) maintain the state, i.e., not change the state, of the resistive memory elements, which change in state may invalidate any obtained MAC result. For example, resistive memory elements such as memristors may change state as a received voltage is greater than a switching voltage of the memristor. In other words, if a received voltage is greater than the switching voltage of the memristor, the memristor may change state, thus changing the coefficients of the matrix and invalidating the matrix used in the dot product. Accordingly, if an input vector is passed directly to a memristor array, the input vector's largest entry cannot exceed the memristor switching voltage, and input vector entries may be scaled down accordingly. In other words, all but the largest of the input voltages are scaled, and are therefore smaller than the maximum possible voltage. In some instances the scaling results in input voltages that are much smaller than they could be. As such, some memristors in a MAC unit may receive less than the largest possible input signal, which may increase a noise-to-signal ratio and otherwise complicate output detection.”
EN: this paragraph reads on the scaling of the input voltages for rows and columns
The combination of Hu and Buchanan-1 does not teach the changing of resistances according to the negative of the pattern:
the applying of … voltage … to change resistances according to the negative of the pattern.
However, Buchanan-2 teaches:
the applying of … voltage … to change resistances according to the negative of the pattern.
Buchanan-2 [0046] “Accordingly, FIG. 5 illustrates another example of the electronic device 10 in which both positive and negative weights may be assigned to the inputs of the same individual MAC.;
[0049] “Each of the column output circuits 310 corresponds to a pair of column lines comprising one of the positive-weight column lines CL+ and its corresponding negative-weight column line CL−. Moreover, an individual MAC may comprise a column output circuit 310, the positive-weight column line CL+ and its corresponding negative-weight column line CL− that are connected to the column output circuit 310, and the memristors 101 that are connected to the pair of column lines CL+/CL−. An individual MAC may have N inputs, each corresponding to one of the row lines RLn. Specifically, an individual input of a given MAC may comprise the positive memristor 101 and the negative memristor 101 that are connected to the corresponding row line RLn.”
EN: this paragraph reads on a corresponding column of resistors with the negative weight
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu and Buchanan-1 with the corresponding negative column, which is in a column pair with the positive column, of the multiplier-accumulator (MAC) from Buchanan-2 in order to improve computational efficiency.
Buchanan-2 [0001] A multiplier-accumulator (MAC) is a device that performs a multiply-accumulate operation. For example, the multiply-accumulate operation may include multiplying various values and adding the products together.
[0002] An artificial neuron may include circuitry that receives one or more input signals and performs operations on the inputs to generate an output signal. The input signals and output signals may be, for example voltages, currents, digital values, etc. In certain examples, the operations performed by an artificial neuron on the inputs may include multiply-accumulate operations, in which case the artificial neuron may include a MAC. In such examples, the input signals of the neuron may be fed to the MAC for multiplication with other values (e.g., weightings that are set for each input) and the output signal of the neuron may be based on the output signal of the MAC. Artificial neural networks are collections of artificial neurons in which the output signals of some neurons are used as the input signals of other neurons.
Regarding Claim 3
The combination of Hu, Buchanan-1, and Buchanan-2 teaches all of the limitations of claim 2 as cited above and Hu further teaches:
the changing of the resistances of the memristors of the first column being simultaneous with the changing of the resistances of the memristors of the second column.
Hu [0050] “In block 540, the processor may provide a second set of voltage signals to reprogram the plurality of memristors to improve the accuracy of the crossbar array in detecting the pattern in the sensor data. For instance, as mentioned above, due to variations of the memristors physical properties, wire resistances, input resistance, output resistance, shot noise, Johnson noise, and other factors, the memristors may not actually take on the target values. In addition, the matrix representing the neural network as a linear transform or transfer function may be imperfectly trained due to a variety of factors, such as a limited training data set, an insufficient number of training runs to optimize the matrix, a natural variation in the types of physical parameters that may comprise the pattern, and so on. Accordingly, any deviations from a target representation of the neural network determined at block 530 or any negative feedback information received at block 530 may be used to reprogram the memristor resistances to better match the target resistances and/or to recalculate target resistances and then reprogram the memristor resistances accordingly. For example, adjusting the resistance values of the memristors of the crossbar array may be to minimize a miss ratio and/or maximize a hit ratio of the crossbar array in detecting the pattern.”
EN: this paragraph denotes the changing of multiple memristors of the array which reads on changing of resistances simultaneously of columns.
Regarding Claim 10
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu does not distinctly disclose:
configuring an artificial neuron connected to the column pair to trigger when the pattern is recognized by the column pair.
However, Buchanan-2 teaches:
configuring an artificial neuron connected to the column pair to trigger when the pattern is recognized by the column pair.
Buchanan-2 [0037] In certain examples, the electronic device 10 may include an artificial neural network (“ANN”). For example, the crossbar array 100, the row driver circuitry 200, and the column output circuits 300, may correspond to a first layer of the ANN. In such an example, each MAC of the crossbar array 100 may correspond to an induvial neuron. Specifically, each column may correspond to an individual neuron, and the neuron may include each of the memristors 101 in the corresponding column together with the column output circuit 300 of the corresponding column. In certain examples, each column of the crossbar array 100 corresponds to exactly one neuron (e.g., there is a one-to-one correspondence between columns and neurons), while in other examples (e.g., see FIG. 5) more than one column may correspond to multiple neurons (e.g., there is a many-to-one correspondence between columns and neurons).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu and Buchanan-1 with method of memristor columns corresponding to artificial neurons from Buchanan-2 in order to improve computational efficiency.
Buchanan-2 [0001] A multiplier-accumulator (MAC) is a device that performs a multiply-accumulate operation. For example, the multiply-accumulate operation may include multiplying various values and adding the products together.
[0002] An artificial neuron may include circuitry that receives one or more input signals and performs operations on the inputs to generate an output signal. The input signals and output signals may be, for example voltages, currents, digital values, etc. In certain examples, the operations performed by an artificial neuron on the inputs may include multiply-accumulate operations, in which case the artificial neuron may include a MAC. In such examples, the input signals of the neuron may be fed to the MAC for multiplication with other values (e.g., weightings that are set for each input) and the output signal of the neuron may be based on the output signal of the MAC. Artificial neural networks are collections of artificial neurons in which the output signals of some neurons are used as the input signals of other neurons.
Regarding Claim 12
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 11 as cited above but Hu does not distinctly disclose:
an artificial neuron connected to the column pair and configured to be triggered when the pattern is recognized by the column pair.
However, Buchanan-2 teaches:
an artificial neuron connected to the column pair and configured to be triggered when the pattern is recognized by the column pair.
Buchanan-2 [0037] In certain examples, the electronic device 10 may include an artificial neural network (“ANN”). For example, the crossbar array 100, the row driver circuitry 200, and the column output circuits 300, may correspond to a first layer of the ANN. In such an example, each MAC of the crossbar array 100 may correspond to an induvial neuron. Specifically, each column may correspond to an individual neuron, and the neuron may include each of the memristors 101 in the corresponding column together with the column output circuit 300 of the corresponding column. In certain examples, each column of the crossbar array 100 corresponds to exactly one neuron (e.g., there is a one-to-one correspondence between columns and neurons), while in other examples (e.g., see FIG. 5) more than one column may correspond to multiple neurons (e.g., there is a many-to-one correspondence between columns and neurons).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with method of memristor columns corresponding to artificial neurons from Buchanan in order to improve computational efficiency.
Buchanan-2 [0001] A multiplier-accumulator (MAC) is a device that performs a multiply-accumulate operation. For example, the multiply-accumulate operation may include multiplying various values and adding the products together.
[0002] An artificial neuron may include circuitry that receives one or more input signals and performs operations on the inputs to generate an output signal. The input signals and output signals may be, for example voltages, currents, digital values, etc. In certain examples, the operations performed by an artificial neuron on the inputs may include multiply-accumulate operations, in which case the artificial neuron may include a MAC. In such examples, the input signals of the neuron may be fed to the MAC for multiplication with other values (e.g., weightings that are set for each input) and the output signal of the neuron may be based on the output signal of the MAC. Artificial neural networks are collections of artificial neurons in which the output signals of some neurons are used as the input signals of other neurons.
Regarding Claim 13
The combination of Hu, Buchanan-1, and Buchanan-2 teach all of the limitations of claim 12 as cited above and Hu further teaches:
an excitatory component configured to trigger
Hu [0024] “The output of the DPE 130 may comprise an output vector of a second set of analog voltage signals that is derived from a vector dot product multiplication of the input vector of the first set of analog voltage signals (from sensor(s) 110 and/or analog buffer(s) 120) with a matrix comprising the resistance (or conductance) values of the memristors of the DPE 130. In one example, all or a portion of the second set of analog voltage signals in the output vector may be used for pattern matching/pattern detection. For instance, in one example the eight most significant bits (analog voltage signals) may be relevant for detecting a slip-and-fall pattern. In one example, one or more of the second set of analog voltage signals of the output vector of DPE 130 may be used as an activation signal to activate processor 140. For instance, processor 140 may be kept powered off or in a low power state until an activation signal is received. Thus, in one example, the processor 140 is activated upon a detection of a pattern by the DPE 130. Otherwise, power is conserved by maintaining the processor in the off state or a low power/power saving state.”
EN: excitatory component reads on activation signal
when a current output of one column of the column pair has a minimum value established during the training; and
Hu [0010] “In another example, the present disclosure describes a device to program a memristor-based crossbar array for processing analog sensor data. The device may include a processor and a non-transitory computer-readable medium storing instructions which, when executed by the processor, cause the processor to determine target resistance values for memristors of a crossbar array to represent a neural network for processing analog sensor data to detect a pattern, provide a first set of voltage signals to program the plurality of memristors of the crossbar array, the first set of voltage signals based upon the target resistance values, determine an accuracy of the crossbar array in detecting the pattern in the analog sensor data, and provide a second set of voltage signals to reprogram the plurality of memristors to improve the accuracy of the crossbar array in detecting the pattern in the analog sensor data.
[0050] “In block 540, the processor may provide a second set of voltage signals to reprogram the plurality of memristors to improve the accuracy of the crossbar array in detecting the pattern in the sensor data. For instance, as mentioned above, due to variations of the memristors physical properties, wire resistances, input resistance, output resistance, shot noise, Johnson noise, and other factors, the memristors may not actually take on the target values. In addition, the matrix representing the neural network as a linear transform or transfer function may be imperfectly trained due to a variety of factors, such as a limited training data set, an insufficient number of training runs to optimize the matrix, a natural variation in the types of physical parameters that may comprise the pattern, and so on. Accordingly, any deviations from a target representation of the neural network determined at block 530 or any negative feedback information received at block 530 may be used to reprogram the memristor resistances to better match the target resistances and/or to recalculate target resistances and then reprogram the memristor resistances accordingly. For example, adjusting the resistance values of the memristors of the crossbar array may be to minimize a miss ratio and/or maximize a hit ratio of the crossbar array in detecting the pattern.”
EN: “the first set of voltage signals based upon the target resistance values” reads on having a maximum and min value for the output voltage for the target resistances;
an inhibitory component configured to stop the triggering
Hu [0038] “As mentioned above, in one example, crossbar array 302 may include a comparator 380 to determine whether a particular pattern is detected in the output vector at vector output register 314. For instance, it may desired to have a first of the output analog voltage signals in the output vector to be high, e.g., above a certain threshold for an analog voltage signal, when a particular pattern is detected.;”
[0041] “In one example, the resistances (or conductances) of the memristors may have been programmed for the crossbar array to function as a linear transform representing a neural network for detecting a pattern in the sensor data. The pattern may be indicative of a particular condition or event, or a set of conditions or events.”
when a current output of the other column of the column pair has a maximum value established during the training.
Hu [0010] “In another example, the present disclosure describes a device to program a memristor-based crossbar array for processing analog sensor data. The device may include a processor and a non-transitory computer-readable medium storing instructions which, when executed by the processor, cause the processor to determine target resistance values for memristors of a crossbar array to represent a neural network for processing analog sensor data to detect a pattern, provide a first set of voltage signals to program the plurality of memristors of the crossbar array, the first set of voltage signals based upon the target resistance values, determine an accuracy of the crossbar array in detecting the pattern in the analog sensor data, and provide a second set of voltage signals to reprogram the plurality of memristors to improve the accuracy of the crossbar array in detecting the pattern in the analog sensor data.
[0050] “In block 540, the processor may provide a second set of voltage signals to reprogram the plurality of memristors to improve the accuracy of the crossbar array in detecting the pattern in the sensor data. For instance, as mentioned above, due to variations of the memristors physical properties, wire resistances, input resistance, output resistance, shot noise, Johnson noise, and other factors, the memristors may not actually take on the target values. In addition, the matrix representing the neural network as a linear transform or transfer function may be imperfectly trained due to a variety of factors, such as a limited training data set, an insufficient number of training runs to optimize the matrix, a natural variation in the types of physical parameters that may comprise the pattern, and so on. Accordingly, any deviations from a target representation of the neural network determined at block 530 or any negative feedback information received at block 530 may be used to reprogram the memristor resistances to better match the target resistances and/or to recalculate target resistances and then reprogram the memristor resistances accordingly. For example, adjusting the resistance values of the memristors of the crossbar array may be to minimize a miss ratio and/or maximize a hit ratio of the crossbar array in detecting the pattern.”
EN: “the first set of voltage signals based upon the target resistance values” reads on having a maximum and min value for the output voltage for the target resistances
However, Hu does not distinctly disclose:
the artificial neuron comprising: an excitatory component configured to trigger the artificial neuron.
Buchanan-2 teaches:
the artificial neuron comprising:
Buchanan-2 [0037] “In certain examples, the electronic device 10 may include an artificial neural network (“ANN”). For example, the crossbar array 100, the row driver circuitry 200, and the column output circuits 300, may correspond to a first layer of the ANN. In such an example, each MAC of the crossbar array 100 may correspond to an induvial neuron. Specifically, each column may correspond to an individual neuron, and the neuron may include each of the memristors 101 in the corresponding column together with the column output circuit 300 of the corresponding column. In certain examples, each column of the crossbar array 100 corresponds to exactly one neuron (e.g., there is a one-to-one correspondence between columns and neurons), while in other examples (e.g., see FIG. 5) more than one column may correspond to multiple neurons (e.g., there is a many-to-one correspondence between columns and neurons).”
Claim 4 is rejected under 35 U.S.C 103 as being unpatentable over Hu in view of Buchanan-1 in farther view of Otsuka et al. (US 20190332927 A1, hereinafter Otsuka)
Regarding Claim 4
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu teaches:
applying the first … voltage to the second column comprising: applying … the voltage to the second column.
Hu [0034] In one example, each of the resistance (or conductance) values is set by sequentially imposing a voltage drop over each of the junctions in the crossbar array 302. For example, the conductance value G2,3 (where G is a matrix representing the conductances of memristors 308 in the crossbar array 302, and where G2,3 represents the conductance of the memristor 308 in the second row and third column) may be set by applying a voltage equal to VRow2 at the row electrode 304 at the second row of the crossbar array 302 (e.g., at location 330) and a voltage equal to VCol3 at the column electrode 306 at the third column of the crossbar array 302. In one example, when applying a voltage at one of the column electrodes 306, the sense circuit 316 for the column electrode may be switched out and a voltage driver switched in.
EN: this paragraph reads on applying different voltages to different columns and rows
The combination of Hu and Buchanan-1 does not distinctly disclose:
scaled voltage … comprising:
applying five-fourths of the voltage
However, Otsuka teaches:
scaled voltage … comprising:
applying five-fourths of the voltage
Otsuka [0062] “When the offset voltage Voff is generated in the sense amplifier 7, the output voltage Vout is obtained by adding to the offset voltage Voff, the output voltage +Vbias at when the bias voltage +Vb having the opposite polarity is applied.”
EN: the bias voltage is being added to output voltage which makes the input voltage larger than the original input
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu method of scaled larger input of Otsuka in order to reduce power consumption.
Otsuka [0002-3] “The present disclosure relates to a neural network circuit including a storage portion that includes memristors, as storage elements, connected in a lattice shape. A neural network circuit includes an element having two terminals as a synapse, the element being nonvolatile and capable of varying a conductance value and being referred to as a memristor.”
At the time the invention was made, it would have been an obvious matter of design choice to a person of ordinary skill in the art to increase the voltage input to 5/4 of the voltage because Applicant has not disclosed that 5/4 voltage provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Otsuka’s method and the applicant’s method to perform equally well with either the increasing of voltage using the addition of a voltage bias of Buchanan-1 or the claimed application of 5/4 of the voltage because both scaling methods are equally capable of increasing the voltage. Accordingly, it would have been obvious one of ordinary skill in the art at the effective filing date of the claimed invention to modify Otsuka to obtain the invention as specified in claim 5 because such a modification would have been considered a mere design consideration which fails to patentably distinguish over the prior art of Otsuka.
Claim 9 and 18 is rejected under 35 U.S.C 103 as being unpatentable over Hu in view of Buchanan-1 and further in view of Li et al. (WO 2022192864 A1., hereinafter Li)
Regarding Claim 9
The combination of Hu and Buchanan-1 teaches all of the limitations of claim 1 as cited above and Hu does not distinctly disclose:
the memristor crossbar comprising memristors of different types.
However, Li teaches:
Li [0004] “In some embodiments, the plurality of memristors are in the form of a memristor crossbar array. In an illustrative embodiment, each memristor in the plurality of memristors includes a pin-hole free, uniform, and atomically thin tunneling barrier. In another embodiment, the plurality of memristors are ultra-thin memristors having a thickness of less than 3 nanometers. In another embodiment, each memristor in the plurality of memristors includes tunable high resistance state (HRS), on/off ratio, and switching speed in at least three orders of magnitude such that different memristors in different layers of the neuromorphic computing circuit have different properties and such that different columns in a given layer of the neuromorphic computing circuit have different properties.”
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with the use of different memristors of Li in order to be more robust to errors.
Li [0024] “Described herein are neuromorphic computing (NC) systems and methods which improve upon traditional computing technologies. For example, the data-movement bottleneck (von Neumann bottleneck) problem in modem computing systems can be overcome in a NC system, where the information is processed and stored in the same units. Additionally, the basic weighted sum operation, also called multiply and accumulate (MAC), in NC is a crucial computation of artificial neural networks. In an illustrative embodiment, NC is a physical system directly mapped to an artificial intelligence (AI) algorithm. Furthermore, it has been shown that NC with quantum hardware will provide an exponential advantage in storage capability over alternative implementations, and that quantum neuromorphic computing is more robust to errors than purely gate-based quantum computing. In general, NC provides next-generation advanced computing that includes high energy efficiency, high speed, intelligence, and parallel computing capabilities.”
Regarding Claim 18
Claim 18 recites substantially similar limitations for claim 9 and is therefore rejected on the same basis.
Claim 15-16 is rejected under 35 U.S.C 103 as being unpatentable over Hu and Buchanan-1 in view of Dumitru ("Analog IGZO Memristor With Extended Capabilities", hereinafter Dumitru).
Regarding Claim 15
Hu teaches all of the limitations of claim 11 as cited above and but does not distinctly disclose:
the memristor crossbar comprising Indium gallium zinc oxide (IGZO) based memristors.
However, Dumitru teaches: the memristor crossbar comprising Indium gallium zinc oxide (IGZO) based memristors.
Dumitru [Introduction 4th paragraph] “IGZO is widely used for realization of transparent thin films transistors (TTFTs). IGZO based memristors are attractive as could be easily integrated with TTFTs and allow for the realization of transparent memories and neuromorphic devices. Noteworthy, IGZO memristors with attractive synaptic behavior have been achieved [8]–[18]. For instance, Wang et al. [11] reported an IGZO memristor based on oxygen ion migration and diffusion with synaptic and memory functions, which further possessed a “learning-experience” behavior. Also, Kimura et al. [12] studied the utilization of an IGZO thin film device as an artificial synapse based on the continuous decrease of the electric conductance by flowing electrical current in the device due to electrons trapping.”
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the memristor crossbar array of Hu with IGZO-memristors of Dumitru in order to achieve higher stability.
Dumitru [conclusion paragraph] “IGZO based memristors with in-plane geometry having multiple states and analog tuning extended capability were successfully fabricated and characterized. The memristor resistance could be reversibly increased and decreased over one order of magnitude. A larger resistance changing range (more than two orders of magnitude) could be also obtained, but in this case the resistance changes are mostly irreversible ones.
The fabricated memristor device seems adequate for use as electronic synapse in hardware implemented artificial neural networks or for various applications such as analogue computing or cryptography.
Regarding Claim 16
Hu teaches all of the limitations of claim 11 as cited above and but does not distinctly disclose:
the memristor crossbar comprising memristors having electrodes situated on a same plane.
However, Dumitru teaches:
the memristor crossbar comprising memristors having electrodes situated on a same plane.
Dumitru [conclusion paragraph] “IGZO based memristors with in-plane geometry having multiple states and analog tuning extended capability were successfully fabricated and characterized.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIAHE NIU whose telephone number is (571)270-0152. The examiner can normally be reached 8am-5pm.
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/JIAHE NIU/Examiner, Art Unit 2128
/OMAR F FERNANDEZ RIVAS/Supervisory Patent Examiner, Art Unit 2128
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